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  • Crash Dump

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    Ignacio Matiasz
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    An unhandled SIG_SEGV error occurred during instruction strmi r6, [r0, r0, lsl #21] caused by accessing an invalid memory address. Register information and debug counts are provided for the emulated ARM9 and ARM7 processors. Translation cache details are also listed.

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    crash_dump.txt

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    An unhandled SIG_SEGV error occurred during instruction strmi r6, [r0, r0, lsl #21] caused by accessing an invalid memory address. Register information and debug counts are provided for the emulated ARM9 and ARM7 processors. Translation cache details are also listed.

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    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
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    4 views2 pages

    Crash Dump

    Uploaded by

    Ignacio Matiasz
    An unhandled SIG_SEGV error occurred during instruction strmi r6, [r0, r0, lsl #21] caused by accessing an invalid memory address. Register information and debug counts are provided for the emulated ARM9 and ARM7 processors. Translation cache details are also listed.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 2

    Unhandled SIG_SEGV in ''

    caused by instruction strmi r6, [r0, r0, lsl #21] (at cb7d9b42), address 28
    Version: r2.5.2.2a build 104
    Reference: BAEAB5E4
    Registers:
    r00: 00000000
    r01: 00000000
    r02: 00000018
    r03: 00001980
    r04: CB7D9B01
    r05: DF011754
    r06: 00000000
    r07: 00000012
    r08: DF011750
    r09: B92447D0
    r10: CCA3F284
    r11: B88B02BC
    r12: E7149B70
    r13: B88AE9D8
    r14: CC81FFB1

    Emulated ARM9:
    Mode 00, IRQ 00000000, CPSR 00000000, PC 00000000, cycles 00000000
    r0: 00000000
    r1: 00000000
    r2: 00000000
    r3: 00000000
    r4: 00000000
    r5: 00000000
    r6: 00000000
    r7: 00000000
    r8: 00000000
    r9: 00000000
    r10: 00000000
    r11: 00000000
    r12: 00000000
    r13: 00000000
    r14: 00000000
    r15: 00000000
    Debug instruction count: 0

    Emulated ARM7:
    Mode 00, IRQ 00000000, CPSR 00000000, PC 00000000, cycles 00000000
    r0: 00000000
    r1: 00000000
    r2: 00000000
    r3: 00000000
    r4: 00000000
    r5: 00000000
    r6: 00000000
    r7: 00000000
    r8: 00000000
    r9: 00000000
    r10: 00000000
    r11: 00000000
    r12: 00000000
    r13: 00000000
    r14: 00000000
    r15: 00000000
    Debug instruction count: 0

    Translation cache details:


    main: 0xbb085000 - 0xbc085000
    main: 1157083136 + -1140305920 bytes
    itcm: 0xbc085000 - 0xbc185000
    itcm: 1140305920 + -1139257344 bytes
    alternate: 0xbc185000 - 0xbc385000
    alternate: 1139257344 + -1137160192 bytes

    0 texture cache bytes allocated, 0 texture cache elements.

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