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  • Crash Dumpy

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    3m1r.2000.22
    13 views2 pages
    An error occurred due to an invalid memory access caused by an instruction. The document provides details of register values and memory addresses at the time of the error for an emulated ARM9 and ARM7 processor. Memory allocation details for different cache areas are also listed.

    Original Description:

    Crash

    Original Title

    crash_dumpy

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    An error occurred due to an invalid memory access caused by an instruction. The document provides details of register values and memory addresses at the time of the error for an emulated ARM9 and ARM7 processor. Memory allocation details for different cache areas are also listed.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    13 views2 pages

    Crash Dumpy

    Uploaded by

    3m1r.2000.22
    An error occurred due to an invalid memory access caused by an instruction. The document provides details of register values and memory addresses at the time of the error for an emulated ARM9 and ARM7 processor. Memory allocation details for different cache areas are also listed.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 2

    Unhandled SIG_SEGV in ''

    caused by instruction stmdb sp!, {r1, lr} (at ece0c490), address fffffff8
    Version: r2.6.0.4a build 109
    Reference: BBC8CAEC
    Registers:
    r00: BE8A8AC0
    r01: 00000000
    r02: BE8A8B14
    r03: 00000000
    r04: 00000000
    r05: 00000000
    r06: 00000000
    r07: 00000000
    r08: 00000000
    r09: 00000000
    r10: 00000000
    r11: 00000000
    r12: 00000000
    r13: 00000000
    r14: 00000000

    Emulated ARM9:
    Mode 00, IRQ 00000000, CPSR 00000000, PC 00000000, cycles 00000000
    r0: 00000000
    r1: 00000000
    r2: 00000000
    r3: 00000000
    r4: 00000000
    r5: 00000000
    r6: 00000000
    r7: 00000000
    r8: 00000000
    r9: 00000000
    r10: 00000000
    r11: 00000000
    r12: 00000000
    r13: 00000000
    r14: 00000000
    r15: 00000000
    Debug instruction count: 0

    Emulated ARM7:
    Mode 00, IRQ 00000000, CPSR 00000000, PC 00000000, cycles 00000000
    r0: 00000000
    r1: 00000000
    r2: 00000000
    r3: 00000000
    r4: 00000000
    r5: 00000000
    r6: 00000000
    r7: 00000000
    r8: 00000000
    r9: 00000000
    r10: 00000000
    r11: 00000000
    r12: 00000000
    r13: 00000000
    r14: 00000000
    r15: 00000000
    Debug instruction count: 0

    Translation cache details:


    main: 0xbbe49000 - 0xbce49000
    main: 1142648832 + -1125871616 bytes
    itcm: 0xbce49000 - 0xbcf49000
    itcm: 1125871616 + -1124823040 bytes
    alternate: 0xbcf49000 - 0xbd149000
    alternate: 1124823040 + -1122725888 bytes

    0 texture cache bytes allocated, 0 texture cache elements.


    he elements.

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