Homework 1

Carlos Rebelo - 100294

BSc in Engineering Physics

1. Flash Memories

● Design of a typical architecture of the storage element

A flash memory is a nonvolatile electron charge based memory, which means that it
has two distinguishable states for the presence or absence of electrons in a location called
the charge storage node, and can retain information without its power supply. The basic
element of flash memory is a floating gate cell, which can then be connected by Word
Lines and Bit Lines to form an array.
The constitution of a floating gate cell is the storage node, where the information is
stored; the sensor, which reads the state of the bit and typically is formed by transistors; and
the selector, which allows to choose a cell to perform reading or writing operations and is
usually a non-linear component like diode or transistor. The size of the floating gate cell is
about 15 nm.
Typically, the storage node is on a conducting layer, called the floating gate, and it is
surrounded by a dielectric or oxide material (the physical importance of this is going to be
discussed later). Attached to this is the sensing device, which has to be in immediate
proximity with the storage node, and is commonly a field effect transistor (FET). The FET is
controlled by the Control Gate. A scheme of this is represented in Figure 1.

Figure 1: Representation of a floating gate cell

Two examples of flash memories are NAND flash and NOR flash. Although they have
the same basic element, in the NOR flash, one end of each memory cell is connected to the
bit line, in contrast to NAND, where several memory cells are connected in series.

● Physical operation principle and basic equations

As it was explained before, in flash memory an electron is placed in the storage

node, and the presence or absence gives the state 1 or 0, correspondingly. In order to be
able to retain information without a power source, the electrons must be trapped between
two energy barriers. A representation of this can be found in Figure 2.
 Figure 2: Representation of memory cell

The barriers are made of insulating materials. The height and width of the barrier are
very important to prevent leakages, either over the barrier (if it is not high enough), or by the
tunneling effect (if it is not wide enough). In the event of a leak, the information present in the
memory is lost, so to prevent this it is essential that the barriers are high and wide.
As it was stated before, the FET has the purpose of reading the information,
functioning as the sensor. As it is controlled by the voltage applied in the control gate, the
state influences the current on the FET, which makes it able to, by measuring this current,
understand if the state is 0 (high current) or 1 (low current).
There are several ways of writing (changing the state of the memory by injecting
electrons into the storage node), being two of them the Fowler-Nordheim Tunneling and
the Hot Electron Injection. The first method occurs when the potential difference across the
barrier between the storage node and the external contact is larger than the barrier height,
so it requires a high voltage to write. The second consists of accelerating the electrons in the
FET, giving them sufficient energy to overcome the barrier.

● Physical limits of scaling (i.e, what are the limitations to reduce the size
towards a ultrahigh density memory)

The main obstacle to reducing the size is the barrier insulator thickness. As it was
stated before, the memory cell depends on the parameters of the barrier (width and height).
With this in mind, these dimensions are a huge constraint on the possible dimensions that
the element can have. With that being said, the total size of an hypothetical floating gate cell
would be 13 nm (with only one electron stored). This size does not take into account the
degradation of the FET performance, due short-channel effects. An additional problem
arises when we consider that the reduced spacing between neighbor floating gates will lead
to communication between them and changes in their information.

● Indicate how the retention time can be calculated, and what are the key
physical parameters that affect the retention of a bit state

The expression that gives the retention time is given by:

𝑒𝑁𝑠
𝑡𝑟 = 4(𝐼𝑜−𝐵−𝐼𝑇)
where 𝑁𝑠 is the number of electrons stored, 𝐼𝑜−𝑏 and 𝐼𝑇 are the leakage currents, if the
barrier is not wide and high enough, respectively.

The charge retention depends on parameters related to the barrier, namely the width
and height, as it was stated. With a barrier that is not high or wide enough, the electron can
escape the storage node and the bit information is lost. Typically, for practical cases, the
barrier width should be superior to 7 nm, for long retention (superior to 10 years). However,
this depends on the dielectric material that is chosen, so this is an important factor. Another
essential parameter is the number of electrons in the floating gate, because the potential
created by these electrons deform the barrier, which can lead to superior tunneling leakages.

● Reliability issues

The first reliability issue in the practical application of these concepts is imperfections
on the dielectric used, which lead to more mechanisms of leakaging. Also, the repeated
action of writing and erasing results in degradation of the insulating properties, which then
leads to more leaks and limits the lifetime of the memory cell.

The second issue occurs due to the fact that the Control Gate is connected to the
FET by coupled capacitors. The parameter that gives the ability of controlling the FET is the
coupling ratio:

𝐶𝐶𝐺
α = 𝐶𝐶𝐺+𝐶𝐹𝐺

In order for the control gate to be effective, the ratio has to be bigger than 0.60. However,
using the same material for top and bottom dielectrics, this is impossible to achieve.

● Example of manufacture companies for such a memory device

There are several examples, namely Samsung, Toshiba/Kioxia and Intel.

● Example of research groups working on the topic

Institute of Memory Technology Research and Development (high-speed flash

memory), researchers from National University of Singapore, IBM Research.
 2. DRAM

● Design of a typical architecture of the storage element

The DRAM is a volatile memory whose basic element is constituted by a Transistor

next to a Capacitor (which represents a Si-based dielectric), connected by a Si substrate. In
Figure 3, a representation of the cell of a DRAM is shown, where it can be seen that the
transistor is connected to the word line and the capacitor is connected to the bit line by the
transistor.
2
The minimal achievable size for the DRAM cell is 8𝐹 , where F is the minimum
feature size, for example a line or a space width. It is possible to achieve a smaller size, but
it is necessary to rearrange the structure that has been explained before. In practical
applications, this feature size varies between 70 and 120 nm.

Figure 3: Example of a cell of a DRAM

● Physical operation principle and basic equations

The principle is divided in the writing and reading operations. The writing operation
occurs when the transistor, which functions as a switch, is closed, and enables the capacitor
to charge with the voltage from the bit line. If the voltage is 0, the state of the bit is 0,
otherwise it is 1. This relationship arises from the capacitor charge equation Q=V.C, where it
can be seen that, if V=0, the capacitor has no charge. To reduce the electric voltage stress in
the capacitor, the capacitor can be connected to a constant voltage of 𝑉𝐷𝐷, which leads to
the capacitor voltage being ± 𝑉𝐷𝐷/2, and the charge being Q=± 𝑉𝐷𝐷𝐶/2. When the switch is
opened, the capacitor maintains its state (the discussion about its retention time is present in
the next sections).
The reading operation only occurs if an external circuit is connected and commonly a
flip-flop circuit is used to translate the charge into digital information. To begin the reading,
an equalising signal of 𝑉𝐷𝐷/2 is applied to both the differential inputs of the flip-flops, and this
brings the flip-flop to an unstable state. Then, when the switch is open, the charge on the
capacitor is redistributed between the storage capacitor and a capacitor that is part of the
external circuit and is connected to the bit line. This redistribution leads to a voltage change.
𝐶𝑆 𝑉𝐷𝐷
The final voltage is given by 𝑉𝐵𝐿 = (1 ± 𝐶𝑆+𝐶𝐵𝐿
) 2
, where the plus and minus sign depend
on whether the state is 1 or 0, respectively. In this way, the flip-flop will interpret the
increment or decrement of the voltage as the corresponding state.

● Physical limits of scaling

The scaling of the product is related to the feature size F. The reduction of F has an
impact on the bit line capacitance and resistance. Although the delay time for capacitor
charging and discharging may increase, the timing is not the critical factor, but the sense
amplifier and capacitor geometry.

Beginning with the sense amplifier problem, if F is too low, the voltage at the
capacitor is going to be reduced, and there won’t be much room left for further reduction
between the voltage in the bit line and the voltage of the amplifier devices.

A thin film capacitor can have various shapes, but for a cylinder of diameter F, the
2
π(𝑋𝐴𝑅+1/4)𝐹
capacitance can be estimated by 𝐶𝐶 = ε0ε𝑟 𝑡𝑚𝑖𝑛
, where 𝑡𝑚𝑖𝑛 is the minimum thickness

of the capacitor dielectric and 𝑋𝐴𝑅 the aspect ratio of the capacitor. The minimum thickness
is restricted to a minimum of 5 nm, to prevent leakages by tunneling effects, for example.
2
Assuming a resulting capacitor area of 𝐴𝑆 equal to 4𝐹 , it is possible to calculate 𝑋𝐴𝑅, and
conclude that the top electrode, which covers the cylindrical capacitor, approaches a zero
thickness for F = 10 nm. Having this no practical application, and considering the impact on
the resistance on the top electrode, the limit of the thickness of the top electrode is
approximately 1 nm, which brings the limit of F to 12 nm. It might be feasible to reduce F, but
it would be necessary for the inner electrode to be smaller than F.

● Indicate how the retention time can be calculated, and what are the key
physical parameters that affect the retention of a bit state

The retention time depends on two key aspects, the time of discharging the
capacitor, and the time that the electric charge takes to move. The law of the voltage in a
𝑡
− 𝑅𝐶
capacitor is given by 𝑉 = 𝑉0𝑒 . After five periods (periods are given by the characteristic
𝑞
time RC), the capacitor has been practically discharged, so the total time is 𝑡 = 5𝑅𝐶 + 𝐼
.

● Reliability issues

In order to be able to evaluate the reliability of the whole system, it would be

necessary to consider the stability of all the components. In this discussion, the focus will be
the reliability of the cell capacitors.

As the materials are not ideal, the stored charge decreases with time and this leads
to charge losses. One phenomenon that originates this is the leakage current, a result of the
non-zero conductivity of the dielectric of the capacitor. Following this is a period of resistance
degradation, which ultimately results in more leakage currents and loss of insulating
properties. This is what determines the reliability of the capacitor and defines its lifetime.
Lifetime is defined by the time when leakage current increases by a factor of ten, compared
to the value of the steady state minimum.

● Example of manufacture companies for such a memory device

There are several examples, namely Micron Technology, Alliance Memory and
Advantech.

● Example of research groups working on the topic

TrendForce, SAFARI, DRAM Systems Research: Bruce Jacob.

 3. Magnetic Memories MRAM

● Design of a typical architecture of the storage element

MRAM is a non-volatile memory whose cell has a Magnetic Tunnel Junction (MTJ),
which is the storage element of the memory, connected in series with a selection transistor
functioning as a switch, allowing or not current to flow through the MTJ.
The MTJ is composed of two ferromagnets separated by an insulator typically 1 or 2
nm thick. Although it is an insulator, because the thickness is very small, electrons can
tunnel from one layer of ferromagnet to another, being this a strictly quantum mechanical
phenomenon. Several materials have been used, for example junctions of iron separated by
an amorphous aluminium oxide or by a crystalline magnesium oxide. A representation of this
is in Figure 4. This structure has a typical size of about 50 nm.

Figure 4: Representation of the Magnetic Tunnel Junction (MJT)

● Physical operation principle and basic equations

Unlike other memory elements, MRAM does not use electron charge to store data,
but instead it uses electron spin. The advantage that comes with this is that electron spin is
inherently permanent, in opposite to charge.
The principle of operation is based on one magnetic layer having a magnetization
pinned in a fixed direction and the other being able to switch its direction. This layer is called
the storage layer because the two possible orientations are associated with a resistance
state that codifies binary information.
During writing operation, the switch (transistor) is open, so no current flows through
the MTJ, and the storage layer has its orientation modified according to what is being
written. During the reading operation, the switch is closed and current flows through the MTJ
and, as it was stated before, by analysing the resistance of the stack, it is possible to know in
what state the bit is.
 There are several approaches to how write selectivity is achieved. The first and most
basic is the Stoner-Wolfarth approach, where this can be achieved by combining two
perpendicular pulses of magnetic field generated from the bit and word lines. This method is
represented in Figure 5.

Figure 5: Representation of the Stoner-Wolfarth approach

The Stoner-Wolfarth approach is based on the relationship between the strength of

the field required and its direction. In order to do this, it is used the relation
2/3 2/3 2/3
𝐻𝑥 + 𝐻𝑦 ≥ 𝐻𝐾 , where 𝐻𝑥 and 𝐻𝑦 are the fields originated by the word and bit lines and

𝐻𝐾 is the magnetic anisotropy field of the storage layer. Using this expression, it is possible
to derive the appropriate combinations of the bit and word line fields to encode 0 or 1, where
if both are positive, it is the state 1, and if the field from bit line is positive and from the word
line is negative, it encodes a 0. The problem with this approach is that it is only efficient if all
the bits in an array have similar magnetic properties. In practical applications, this approach
led to many writing errors, so different methods were developed, such as the Toggle MRAM
and Spin-Transfer Torque RAM.

● Physical limits of scaling

All MRAM technologies that are based on field induced switching, such as SW and
Toggle MRAM, are poorly scalable, due to the energy barrier necessary to have a 10 years
retention. In fact, in order for this to be viable, it would be needed to increase the magnetic
volume or effective magnetic anisotropy. Having to decrease the word lines and bit lines, the
effect is that current density increases drastically. Besides, the write power continuously
increases, which makes these concepts only viable until the minimum of 45 nm.
 ● Indicate how the retention time can be calculated, and what are the key
physical parameters that affect the retention of a bit state

The retention time of the bit can be calculated using the characteristic time to switch
above a barrier of height ∆𝐸:

∆𝐸
τ = τ0𝑒𝑥𝑝( 𝑘 𝑇 )
𝐵

where ∆𝐸 = 𝐾𝑉, with V being the volume of the storage layer and K its magnetic
anisotropy.

● Reliability issues

The SW writing scheme presented before is only efficient if all the bits in the array
have very similar magnetic properties. A defect in the shape of the MTJ ends in a
broadening of the distribution of the switching field. When scaling, defining the right shape is
essential to control the switching distribution. The half select instability is a problem
occurring if the switching field of some bits is simply too near the astroid curve, there’s a
reduction of magnetic balance, and an unintentional write action due to thermal fluctuations.

● Example of manufacture companies for such a memory device

Everspin, Antaios, Freescale

● Example of research groups working on the topic

SPINTEC, Fujitsu Laboratories, Nano-Science Center at the Niels Bohr Institute of

Copenhagen University.
 4. Phase change memories PCM

● Design of a typical architecture of the storage element

The PCRAM is a non-volatile memory element, whose basic element is represented

in Figure 6. The cell has different layers, with a bottom electrode, followed by a heater, that
makes the contact between the electrode and the programmable region, heating it and
providing the electrical access, and it is coated by an insulator. The programmable region is
inside a crystalline phase change material, typically the GeSbTe. The programmable region
is made from the same material, but can vary between the crystalline and amorphous state
(this is the key of the process, which will be detailed in the next section).
The PCM cell is then connected to the worldline by the bottom electrode, which is
connected to a transistor, and to the bitline by the top electrode, as it is shown in Figure 7.
The size of these cells have varied a lot since the beginning of the research, but for
example Samsung announced a prototype with a cell size of approximately 46.7 nm.

Figure 6: Scheme of a PCRAM cell Figure 7: Representation of the architecture of a cell array

● Physical operation principle and basic equations

The principle of the operation of this memory device is based on the contrast of
electrical resistance between crystalline and amorphous phases of a phase-change material.
The crystalline phase is characterised by an inferior electrical resistance, in contrast to the
amorphous phase. In order to be able to switch the phase of the material, it is necessary to
apply electrical pulses, that can be short in time but with high current, which lead to a
temperature superior that the melting temperature, and, consequently, ables the melting and
quenching of the material, reaching the amorphous state. In contrast, if a long low current
pulse is applied, the device reaches a temperature superior to the crystallisation temperature
for a sufficiently long time, which leads to the organisation of the atoms into the
crystallisation form. With this in mind, the state 1 corresponds to the crystal form and the 0
state corresponds to the amorphous form. In general, the time of crystallising pulse is in the
order of 200 ns, and the amorphization pulse is in the few tens of nanoseconds. A scheme of
these operations are in Figure 8. The reading is then possible by measuring the resistance
of each cell, which will correspond to a binary state.
 Figure 8: Scheme of the operations of crystallisation and amorphization

● Physical limits of scaling

The ultimate limit of PCRAM in terms of scaling is when the phase change materials
lose this property, which means that this physical operation is no longer viable.
Several studies have been performed to evaluate the behaviour of these materials
with scaling. For ultra-thin films, it has been shown that for films larger than 10 nm, the
crystallisation behaviour does not depend on the thickness. On the other hand, when the
thickness is less than 10 nm, the behaviour depends on the thickness and interface, which
means that the crystallisation temperature is a function of the substrate and capping layer
and can increase or decrease. Phase change nanoparticles were reported to have about 2
nm and were stable at the amorphous state at room temperature. It was also observed that if
they were reduced, the temperature rose.

● Indicate how the retention time can be calculated, and what are the key
physical parameters that affect the retention of a bit state:

The retention time is predicted to be about 10 years and the main parameters that
affect the retention of a bit state are the temperature of crystallisation and melting and the
time of crystallisation.

● Reliability Issues

The main reliability issue that this memory faces is the stuck SET and stuck RESET.
As the name suggests, the stuck SET happens when the cell cannot change to the
high resistance anymore. It is often caused by a change in the composition of the phase
change material (in the switching region). Besides this, electromigration and elemental
segregation are other issues in situations where the phase change material is in the molten
state and has a very high current density flowing. This leads to an enrichment of the area in
Sb, which means that, even if the cell switches the state, it will retain the data in the
amorphous phase.
The stuck RESET happens when the cell cannot change to the low resistance state
anymore and is often caused by void formation over the bottom electrode or delamination
between the material and the heater. This problem can be mitigated by techniques like
doping.
Another parameter that is important to look at is the endurance of the cell, which
depends on the way which the cells are operated, for example, long and high RESET pulses
can lead to an earlier failure of the cells.

● Example of manufacture companies for such a memory device

Intel, Micron, IBM, Samsung

● Example of research groups working on the topic

IBM Research, Forschungszentrum Jülich, RWTH Aachen University, Shanghai

Institute of Micro-system and Information Technology (SIMIT)