Tutorial Problems: Bipolar Junction Tran: BIT Amplifiers) 1. For the circuit shown in Figure 1, the transistor parameters are J = 100 and V = ©, Design the circuit such that Zeg = 0.25 mA and Verg = 3 V. Find the small-signal voltage gain 4, = v./ vz. Find the input resistance seen by the signal source v, Figure 1 Rs 100 Solution: For de analysis, the capacitors Ce and Ce both act as open circuit. Given the desired operating point Jeg = 0.25 mA and Veep = 3 V. we have OV = Ly Ry + Veron) tLe9 (Rs + Re) BB Nout (¥ } Veo (R +R) 0.25 0-(-5)=| (iso Joopea ei 0290. I+Ry) = R, =16.43 (kQ) ve Tego + ¥eeo they (Rs + Re) S—(-S)=(0.25)R- (ie) Jo2s)(.416:8) oR 1.30 (kQ)The small-signal parameters are: 1, Bl 0010028) 19.5 4a I, 0.25 co Too _ 0.25 = 9.6154 (mA/V) 0.026 For small-signal ac analysis, all de voltages and capacitors act as short circuit. The following expressions are obtained: ~BiRe ist (4 BYR =~ BRe re +(I+B)Re (100) (11.30) 10.4+(101)(0.1) 55.12 The input resistance R, seen by the signal source is: R=Ry\ Ry =Ry |, +(1+B)Re) =50|)20.5 =14.54 (kQ) 2. Consider the circuit shown in Figure 2. The transistor parameters are 6 = 100 and Vy = 100 V. Determine Ri, Ay = vo ve and Ay= io! icSolution: A de analysis is performed to determine the de operating point by treating all capacitors as open circuit. _ Rk _(_15 _ Fn RR, Te (alo 3.2143 (V) 15)(27, Roy =R, | 1, LIE) 6409 (kQ) v, 1 = Vw 3.214307 Ray +14 BYR, 9.6429+(101)(1.2) Teg = Bl yg =1.922 (mA) Ing = (14 B) Ing =1.941 (MA) Very =Veo—HepRe ~MpR, = 9-(1.922)(2.2)-(1.941)(1.2) = 2.44 (V) 9.22 (WA) The small-signal parameters are 1, — Ble = 000.028) _ 953 40) Tog ‘1922 1922 _ 73.993 (mA/V) 0.026 7-2 = 152.029 4K) ° Teg 192 For small-signal ac analysis, all de voltages and capacitors act as short circuit. The following small-signal ac equivalent circuit is obtained: ‘Small-signal model of transistor circuit (*g4¥.— Bis) Bi, (R, || Re l",) Row |e Rot Rey lie Pthb hel} Ray llr | m Ry Roy Fe 1353 (10+#1.187 _ oon 1.187 Jeoy, Rs + Row Ihe Ry tRry Ute Yo R, ¥, i, a a R, I Ry + Rr lhe BRN Re lt, (Row ite) Rut SD 2411 I 9.6429 ) DLAI | 1.353+9.6429 45.05 The input resistance R, is: (9.6429)|| (1.393)= 1.187 (kQ) 3. The parameters of the transistor in Figure 3 are B= 100 and V,= 100 V. (a) Find the de voltages at the base and emitter terminals, (b) Find Re such that Vezo = 3.5 V. (©) Assuming Cc and Ce act as short circuits, determine the small-signal voltage gain 4, =v, (a) Repeat part (c) if a $00 © source resistor is in series with the v, signal source. R= 1009Solution (a) A de analysis is performed to determine the de operating point by treating all capacitors as open circuit B 100 Log =—— = (0.35) = 0.347 (mA) co = 4 0“ F100 [O89 om _ Tip _ 035 =/ = 3.47 (UA) "2146 14100 way V, =0-IygR, =~ (3.47%10* (10) = 0.0347 (V) V,=V,-V 737 (V) ‘2 = Vs Veen) (b) Given Vogo is desired to be 3.5 V, hence: VO RV, MV ec9 + LeoRe (©) ‘The small-signal parameters are: 100} 0.026) _ 5 493 (ka) 0.347 = 13.346 (mA/V) = 288.184 (kQ) Using the small-signal ac equivalent circuit, the following expressions are obtained: v, =—Bi, (Rell) __ Rell . Rs +R, |r Anton BR) Rolls re (Rot Rally __(000)(6.309)/ 4.283, “7.493 | 0.144.283 } 82.28 5@ If the source resistor is changed to 500 Q, the new value of , is Atel | " Rs t Ry lity 100)(6.309)/ 4.283) 45 4 7.493 0.5+4.283 Therefore the voltage gain 4, decreases as the source resistance Rs increases due to a larger voltage drop across the source resistor 4. The transistor in the circuit in Figure 4 has a de current gain of B= 100. (a) Determine the small-signal voltage gain 4 (b) Find the input and output resistances R, and R,, iv. Figure 4 Solution: (a) A de analysis is performed to determine the de operating point by treating all capacitors as open circuit. VO LR t Vega t Ln 7 = ems 4-07 "2 R,+(1+B)R, 5+(101)(5) Jeg = Bl gg = (100) (6.47107 )= 0.647 (mA) Jeg = (1+ B) I gy = 0.654 (mA) Vecg =V7 V7 = 1 epR p= TegRe= = 4~(-6)~ (0.654) (5) (0.647)(4)= 4.14 (V) ‘reo moa) tH ng =6.47 (UA)The small-signal parameters are: (100)(0.026) _ 4 615 aay 0.647 7 94.885 (mAV) 26 = we ® aot t t + iy" ve Sm Sr p> Bie pag ke Sh vy, = Bi, (RI Re ll7,) Rall RAR lr BR self Rell } ¥, ” RoR lhe Vv, 34.35 (100)(2)/_ 2.228 4.019 (142.228 ) The input resistance R. is: Rey li (5)|| 4.019) = 2.228 (k2) To calenlate the ontput resistance Rj, the signal source v; is short-circuited and this gives i = 0. The following equation can be written by KCL at node v, i, +22 =0 RePart B. Common-Collector Amplifier (Emitter Follower 5. The transistor parameters for the cireuit in Figure 5 are B= 180 and V7 =o (a) Find Jeg and Vezg. (b) Plot the de and ac load lines. (c) Calculate the small-signal voltage gain. (d) Determine the input and output resistances Rs and Ry Figure 5 Solution: (a) For de aualysis, the capacitors Cc: aud Co2 act as open circuit. Rp) p-_{ 10 yy tu a vy (asi + 9)=0(V) 10)(10 Ra, = R= LN. 5.0 40) 10+10 7 at Vee 2) $6.91 (uA) RH BR, SH(ISI(OS) Teg = Bly = 15.644 (mA) Teg = (1+ B)Iyg =15.731 (mA) Vosg =V* >= LpgR, =9-(-9)= (15.731)(0.5)= 10.13 (V) (b) The de load line is given by: VO AV> Vig + 1pRy =Vop + TR, (for large B) (Vv -v- peta Oe aysThe ac load line is given by: ve Hi,(R, | R)=0 elead ine ec lead ine © operating point (10,13, 15.644 mA) Collector currant, fe (mA) ° 5 10 6 20 Collector-emitter voltage, Ver (V) ©) The small-signal parameters are: B¥,, _ (180)(0.026) "15.644 15.644 _ 691.692 (mA/V) 0.026 .299 (kQ)@ v= (+B) i (Re IIR.) =3 2 =(14 B)(R, || R, )= (181) (0.1875) = 33.9375 i, wake ty, =i + (1+ Bi, (Rell R) HER, =r, +(1+ BYR, || R, = 0.2994 33.9375 = 34.2365 i, Rall RI = Ye Ry + Ro || Ri || Re RAIRIR 43028 9 oi 55 Ro+Ry || RR, 144.3628 Padi OF PRN R RRL RIR (+ BYR taf Rell RAR, } Ry RoR | R | Re 1 34,2365 =¢s.9379, (0.8135) = 0.8064 The input resistance Ry is: et (+ B)Re IR.) = 0.299 +33.9375 = 34.24 (kQ) rn To calculate the output resistance 2,, the signal source v. is short-circuited and the following equations can be written by KCL at node v, and node v» ita} —"5__4.j, <0 (KCL at node v,) Ry \|R Ry Yn v rls i 0 =r, +R, RIK RRR 6 ) i404 B)i= y, aRIREyE 6.18 (Q) 106. For the cireuit shown in Figure 6, let Voo= 5 V, Rr = 4 kQ, Re = 3 KO, Ry = 60 KO, and Ry = 40 KO. ‘The transistor parameters are B= 50 and Vs = 80 V. (a) Determine Jeo and Vasco (b) Plot the de and ac load lines. (©) Determine 4y =v, /v, and Ay= ig / i (@) Determine Ri, and R, Figure 6 Solution: @) For de analysis, the capacitors Coy and Cz act as open circuit. 7. Ry _{_40 - Voy = Veo (ata }o-20 (64) 94.0 42) 60+40 I Koo —Vemen Vm __5-0.7-2 = 12,99 WA) 00 Ry FUFBYR, 24+(51)(3) i“ Tyo = 0.650 (mA) 14 B)Iyy = 0.663 (mA) ‘co ~TpgR, = S~(0.663)(3)=3.01 (V) (b) ‘The de load line is given by: Veo =1pRy +V (SP Ye Vc B Vc Voc +: aes ul = 0.32687 ge +1.6340The ac load line is given by: voi, (Re | R= 0 va th (“Pe | RJ=0=1, “EP ein —scloadine operating point (201 v, 0680 ma) Collector euerent, © Emitercliectorvokage, Vez V) The small-signal parameters are _ BY, _ (50)(0.026 2.0 (kQ) To) 0.650 _, = Heo = 9.650 95.0 (AV) ¥, 0.026 y= t= - 193.077 4) Tey 0.650fs pie] 7) G4) ReI RY _GSILT3) __ 9 9995 +(e RY, L7143123.077 “| SB 1], 1+ (Re RY/r, =r ar | Ct PVREIR)]_ = =R,=r, [SDE -2ovsoznes-snaze ino hy 4M ow BNR), 1 WR Rr, Re 1 [opi 14)| 14(Re Rr Ry =(86 2283 1 pe 9773 88.2283 pe] WR) (PHAR) _GNUT 6s rs 14(R,[.R, Yr, 141.7143/123.077 RR, Ry +R R* Rik 24 Ry, +R,|R, 88.2283+24 = 0.2138 1 BVRe WR) R 1+(Re ||R.) RAR RytR | Ry =(F 6 2283)(0.2138)=4.61 B(d) The input resistance Ry is: =r,+ 0+ 86.2283 = 88.23 (kQ) [epee RR h To caleulate the output resistance R,, the signal source v, is short-circuited and the following equations can be written by KCL at node v.: 7. For the transistor in Figure 7, the parameters are = 100 and V4 =o, (a) Design the circuit such that Jeg = 1 mA and the O-point is in the center of the de load line. (b) If the peak-to-peak sinusoidal output voltage is 4 V, determine the peak-to-peak sinusoidal signals at the base of the transistor and the peak-to-peak value of v, (o) If the load resistor Rx = 1 kQ is connected to the output through a coupling capacitor, determine the peak-to-peak value in the output voltage, assuming v, is equal to the value determined in part (b). Veo=+10¥ Figure 7 4Solution: (a) For de analysis, the capacitor Ce acts as open circuit Vor = TagRa + Vecion + leoRe R, =p foot R, ~— 9.3 (kQ) well Tol (kQ) AI) Very + TopRe Veco “ex tor Q-point is in the center of the deload line) 10=S+(I)R, R,=5(kQ) 12) = R, =(101)(0.3-R,)= 434.3 (KO) Teg (55) = (Hi]o- 0.990 (mA) BV, _ (100)(0.026) _ To 0990 2.6263 (kQ) 0990 _ 33,0769 (ma/V) 0.026 (b)vy, Rot Rell Ro th Polls 234.0545 _ 9 go 79 vy, Ro+Ry|R, _ 0.71234.0545 YM & ve +04 B)Re ~ (1+B)Re 507-265 _1 9952.3) 505 =505x x0,9970 = 0.9918 44) 507.6263 Ifthe peak-to-peak output voltage Vojectpaab is 4 V, E9.(3) = Vscpeat-peat) = 1-0052¥ ¢ peat poay = 4-021 (V) y, peak poa) 0.9918 Eq) % peat peay = 033 (V) © If the load resistor R; = 1 kG is added in parallel to Re. Eq. (4) must be modified accordingly: (1+ B)(Rs R,) ( RyllRy } VFI BY(Re IR Re # Roll Re ___(101)(0.8333) _ © 2,6263+(101)(0. 4393) (29970)= 0.9068 = Vicpent-poat) = 0.9668, peux pay = (0.9668) (4.033) = 3.90 (V) Therefore Varaotreah becomes smaller due to the loading effect by Rr 168. An emitter-follower amplifier, with the configuration shown in Figure 8, is to be designed such that an audio signal given by v, = 5 sin(3000F) V but with a source resistance of Rs = 10 ©2 can drive a small speaker. Assume the supply voltages are 7” = + 12 V and J” =~ 12 V and B= 50. The load, representing the speaker, is Rr = 12 . The amplifier should be capable of delivering approximately 1 W of average power to the load. What is the signal power gain of your amplifier? Ves fy Figure & R= Ce Co ve-RVv Solution: To deliver 1 W of average power to the load, the peak-to-peak output voltage should be Petpet 2R, = Vejpaty = 4.899 (V) > hacpeat) = — = 0.408 (A) Vat pat- pooh) = 9-798 (V) The required voltage gain 4, is Choose Zeg = 0.8 A and Vezg = 12 V. Vi-V Vong Teo 1 31 jolt BYR =| Zp |(15)=76.5 (@) (For bias-stable circuit)Voy =Vo + TpgRe +V grog) +L ‘v¢00) + Fp AR, eo) ny =-2+0sy¢s)eo7+[ SF Je 5)=19(V) et Ve = (RYU) = R=132(Q) R= 182 (Q) The small-signal ac equivalent circuit is given by Choosing Jeg = 0.5 A gives: B 50 jap “(Fe 0.784 (A) Br, 600) 5 5) "|, 0.784 co The small-signal voltage gain is taken from Q.7 with some modifications OB) (Re IR) ( RRA Ry } Re H(EBY(R| RRR WR | R, ___G1)(6.667) 62.5116 “TOT eas = 0.8579 Due to the presence of the source resistance Rs (loading effect) the required voltage gain of 4, = 0.9798 cannot be achieved. Note that 4, = 0.9951 if R= 0 Therefore the maximum achievable peak output voltage is: Yospest) — 0.8579 => Veipoaty = 4-290 (V) ot) 18Hence the output power delivered to the load Rz is: 767 (W) tomy Yams S/N Kom = = = 48.758 (mA) RSF RRR, 104625116 Joss 72.386 (mW) 0.767 P, 172.386x10 Part CAC Load Line Anal Maximum Symmetrical Swing 9. For the circuit in Figure 9, the transistor parameters are f= 100 and V7, = 100 V. The values of Re. Re and Ry are as shown in the figure. Design a bias-stable circuit to achieve the maximum undistorted swing in the output voltage if the total instantaneous C-E voltage is to remain in the range 1 < ver < 8 V and the minimum collector current is to be ic (min) = 0.1 mA. Vecn9¥ 1 19Solution: To obtain a bias-stable circuit. let: Rog = RI Ry alte PORe=( Fh \o2)=12.12 4) The de load line of the circuit is given by Voo= =1R, vie SP B Re Ven +1 Ry —— 0.2931... + 2.6377 Al) 1B R (Se R.+| FE The ac load line of the circuit is given by: Yao ti (Re (IR) )=0 ~0.9545v,, (2) Given vcriaia = 1 V and icin) = 0.1 mA, the maximum swing of vez and ic from the Q-point (Ieg. Veg) would be: |Averimmul= Pero Vero! [Aieunas| = ep ~einim = Log — O41 Since Avg, and |Aicinns are related by the ac load line im |Ai.|=0.9545Avee| Jeg —0.1= 0.9545 Very 1) Tog = 0.954¥ cpg ~ 0.8545 (G) Solving (1) and (3) at the Q-point (Icg. Veeg) 0.9845V, 5 ~ 0.8545 = -0.293 gp + 2.6377 1.2476V cpg = 3.4922 Very = 2.80 (V) Tog = 1.817 (mA) 20To decide the value for Vz Vou = LagB rns + Voc + 4eoRs “(ee iayvoral iy sir 2 100 100 =3.122(V) L sh = —(R, || RY Rak oo RRR Mee = R,=34.93(kQ) RK, =18.56 (KO) de load ine oad line © operating point 28 (280, 1.817 may Collector current, c (mA) Collector-omitter voltage, Vee (V) 10. In the circuit in Figure 10 with transistor parameters = 180 and V/,= oe, design the bias resistors Ri and R) to achieve maximum symmetrical swing in the output voltage and to maintain a bias-stable circuit. The total instantaneous C-E voltage is to remain in the range 0.5 < ver < 4.5 V and the total instantaneous collector current is to be ic > 0.25 mA. R ete Figure 10 Cer R= 12kO auSolution: To obtain a bias-stable circuit. let: Rog = Ry || Ry 1 181 =i PRe=[ Teo 81 (kQ) The de load line of the circuit is given by Voc =1cRe Ven +1 eRe 1+ 8 BT Re+Vop + SE + (5 =-0.9086V., 44.5432.) The ac load line of the circuit is given by: Ye ti (Re [IR J=0 Given verixiny = 0.5 V and tc Vegg) would be 0.25 mA, the maximum swing of vez and ic trom the O-point (Ico. [A¥ rina ~0.5 [Aims =Vewy Veena = Vero = Teg ~deraiay = Log 0-25 Since |Av,, and |Aicinns are related by the ac load line 1.8333 (Mz9-0.5) Tog =1.833 eq — 0.6667 @) Solving (1) and (3) at the Q-point (Icg. Veeg) 1.833309 0.6667 = 0.90800 49 +4.5 2.741 opp = 5.2099 Very =1.90 (V) =2.817 (mA)To decide the value for Vrs Fag Bu + Veins * Leake “(BE jean o7s{ ep ese 80 =1.012 (VY) R, 1 = Voc =— (RRM, RR ral ec => R,=8.95(kQ) RK, = 2.27 (kQ) ‘=e fod ine ac fod tne © operating point (1.90, 2817 may Collector current, fe (mA) off. 2 3 4 5 6 Collector-emitter voltage, Vee (V) 2B