Basics

• An interconnection network in a parallel machine transfers

information from any source node to any desired destination node.
This task should be completed with as small latency as possible. It
Interconnection Networks should allow a large number of such transfers to take place
concurrently. Moreover, it should be inexpensive as compared to the
cost of the rest of the machine.
• The network is composed of links and switches, which helps to send
the information from the source node to the destination node. A
network is specified by its topology, routing algorithm, switching
strategy, and flow control mechanism.

Organizational Structure Types of Interconnection Networks

• Links − A link is a cable of one or more optical fibers or electrical wires with a
connector at each end attached to a switch or network interface port. Through
this, an analog signal is transmitted from one end, received at the other to obtain
the original digital information stream.
• Switches − A switch is composed of a set of input and output ports, an internal
“cross-bar” connecting all input to all output, internal buffering, and control logic
to effect the input-output connection at each point in time. Generally, the
number of input ports is equal to the number of output ports.
• Network Interfaces − The network interface behaves quite differently than switch
nodes and may be connected via special links. The network interface formats the
packets and constructs the routing and control information. It may have input and
output buffering, compared to a switch. It may perform end-to-end error checking
and flow control. Hence, its cost is influenced by its processing complexity,
storage capacity, and number of ports.
Static Networks Example of Static Network

Dynamic Interconnection Network

• Here links can be re-configured by switches. Some of themost
well-known categories for dynamic networks are bus-based, crossbar
andMIN (multistage Interconnection Network)
(2) (PDF) Dynamic routing of data stream tuples among parallel query
plan running on multi-core processors. Available from:
https://www.researchgate.net/publication/232703417_Dynamic_rou
ting_of_data_stream_tuples_among_parallel_query_plan_running_o
n_multi-core_processors#fullTextFileContent [accessed Apr 03 2023].
Examples of Dynamic Networks Multistage Interconnection Networks
• In a MIN, processors are connected to the others via a set of
Switching Elements(SE)

Omega Network
• Properties
• An N-input omega network requires log2N stages of 2 x 2 switches.
• Each stage of this network is interconnected in the same manner.
• Each stage consists of N/2 switch boxes. Each switch box is in any of
the four states (i.e. straight, exchange, upper broadcast, or lower
broadcast).
• There is perfect shuffle exchange interconnection between every
adjacent stage.
• The interconnections between the stages in an Omega Network are
defined by the “rotate left” of the bits.
Omega Network Delta Network
• There is a unique path from each network input to each output.
• It is a Type of Banyan Network
• If bit is 0 then take upper port
• If bit is 1 take lower port
• In Banyan Networks there is a single path from each input port to
each output port
• Delta network has self-routing property
• The path for a cell to take to reach its destination can be determined
directly from its routing tag (i.e., destination port id)

Delta Network Delta Network

Path Contention Crossbar Switch
• Crossbar Switch system contains of a number of crosspoints that are
kept at intersections among memory module and processor buses
paths.
• In each crosspoint, the small square represents a switch which
obtains the path from a processor to a memory module.
• Each switch point has control logic to set up the transfer path among
a memory and processor.
• It calculates the address which is placed in the bus to obtain whether
its specific module is being addressed. In addition, it eliminates
multiple requests for access to the same memory module on a
predetermined priority basis.

Crossbar Switch Crossbar Switch

A crossbar switch system

permits simultaneous
transfers from all memory
modules because there is a
separate path associated
with each module. Thus,
the hardware needed to
implement the switch may
become quite large and
complex.