[Date]

HAWASSA
UNIVERSITY
DAYEE CAMPUS
MICROPROCCESSOR AND
ASSEMBLY LANGUAGE

STUDENT
SAMUEL ABIYE ID/NO 2142/13
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1. Virtual memory, Cache memory and

The Floating Point Unit (FPU)
Virtual Memory
Virtual memory is a technique used by operating systems to allow a
computer to compensate for shortages of physical memory by
temporarily transferring pages of data from random access memory
(RAM) to disk storage.

This enables programs to run despite insufficient physical memory.

● It is a concept used in some large computer systems that

permit the user to construct programs as though a large

memory space were available, equal to the totality of

auxiliary memory.

Cache Memory

Cache memory refers to a small amount of high-speed memory that's

available on a computer's microprocessor. Its purpose is to reduce the
time taken to access data stored in RAM by temporarily storing
frequently utilized data from RAM in less than 1 nanosecond so they can
be accessed faster. The cache's close location to the processor enables it
to rapidly provide data to the CPU, thus enhancing overall system
performance.

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The Floating Point Unit (FPU)

The Floating Point Unit (FPU) is a specialized processor core or circuit

designed to perform arithmetic and mathematical operations such as add,
subtract, multiply, and divide on floating-point numbers used in
mathematics, engineering, physics, and other technical fields. The FPU
enhances computational accuracy and effectiveness, improving
numerical performance in applications that involve complex
calculations.

2. Register and Memory in Microprocessor

In a microprocessor, register and memory are two different types of
storage used to hold data or instructions.

Registers

Registers are small, high-speed memory locations within the

microprocessor itself. They are used to hold data that is being actively
manipulated by the microprocessor, such as program counters, status
flags, and operands. Registers are very fast and can be accessed much
more quickly than memory, which makes them ideal for storing
frequently used data.

Memory

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Memory, on the other hand, is a larger storage area outside the

microprocessor that holds data and instructions that are not currently in
use. It is much slower compared than registers in terms of access times
since access might include an extra cycle to fetch form external memory.
Memory is often used to store program code, constants and variables
that are less frequently used.

To summarize, registers are fast and temporary storage areas inside the
processor, while memory is slower and external storage where data and
instructions can be stored for longer term to be accessed as required

3. Deferent types of register indirect addressing

language Size, operation
Register indirect addressing is a memory addressing mode where the
operand of an instruction is stored in a register, rather than directly
specifying a memory address. This method is often used to improve
performance in computer programs.

There are different types of register indirect addressing in programming

languages, which vary in their size and operation. Some commonly used
register indirect addressing modes include:

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1. Base Offset Addressing:

. This addressing mode uses a base register value as an offset to
calculate the memory address of the operand. The size of the base
offset value depends on the computer architecture.

2. Indexed Addressing:
.In this addressing mode, a register value is added to the address
specified by the instruction to get the final memory address. This
type of addressing can be useful for accessing fields in arrays or
tables.

3. Displacement Addressing:
.Displacement addressing involves adding a fixed value or
displacement to the value stored in a register to obtain the memory
address of the operand.

4. Indirect to Firmware Addressing:

.In this addressing mode, the address of the operand is stored in
firmware, rather than in memory. The instruction contains the
address of the firmware location containing the operand address.

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The operation of register indirect addressing modes will depend on the

specific assembly language or programming language used. However,
generally speaking, the use of register indirect addressing can help
reduce the number of memory references needed for a program, which
can lead to improved execution speeds and overall performance

4. List the 8,16 and 32 bit registers that are used

for register addressing.
The 8-bit registers that can be used for register addressing in a
processor are:

- Accumulator (A)
- Temp Register (Temp)
- Stack Pointer (SP)
- Program Counter (PC)

The 16-bit registers that can be used for register addressing in a

processor are:

- Stack Pointer (SP)

- Program Counter (PC)
- Data Pointer (DP)
- Index Register (X)
- Index Register (Y)

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The 32-bit registers that can be used for register addressing in a

processor depend on the architecture and may vary from processor
to processor, but some examples include:

- Base Pointer (BP)

- Frame Pointer (FP)
- Extended Address Register (EAR)
- Memory Management Unit Registers (MMU

5. Define super scalar of architecture of a Pentium

processor?

❖Superscalar architecture is a type of processor architecture that enables

a CPU to execute more than one instruction per clock cycle. This type of
architecture is used in the Pentium processor and many other modern
CPUs.
❖ A scalar processor executes single instruction for each clock cycle; a
superscalar processor can execute more than one instruction during a
clock cycle.
➢ The design techniques of superscalar normally comprise parallel
register renaming, parallel instruction decoding, out-of-order
executions & speculative execution.
❖ The Intel Pentium processor superscalar pipelined architecture
means the CPU executes a minimum of two or above instructions for
each cycle. This processor is widely used in personal computers. Intel
Pentium processor devices are normally built for online use, cloud
computing, & collaboration.

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6. What is clock period of a clock frequency of 1

Ghz?
The clock period is the amount of time that elapses between
consecutive clock edges. It is calculated as the inverse of the clock
frequency.

The clock period of a clock frequency of 1 GHz is:

Clock period = 1 / Clock frequency

Clock period = 1 / 1 GHz
Clock period = 1 ns

Therefore, the clock period would be 1 nanosecond (ns) for a clock

frequency of 1 GHz

7.Suppose memory bytes 0-4 have the

following contents
Address Contents
1 01101010
2 11011101
3 00010001
4 11111111
5 01010101
Assume that a word is 2 bytes; what are the contents in (Hex)

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A, -the word of memory address of 2 is

00010001 11111111.
11FF(In Hex)
B, - the word of memory address of 3 is
11111111 01010101.
FF55 (In Hex)
C, - what is bit 7 of byte 2 is
Byte 2=00010001
Bit 7=0.
8. The processor has only 4 instructions (Conditional branch, Add,
LDW, SDW). The processor has 16-bit 8 registers and 256B Memory.
The ISA is a fixed-length ISA and it has 16 bits.
You need to implement, BR, ADD, LDW and SDW. Architectural
states, you need to implement PC, Registers, Memory, and 3-bit CC
(NZP).

The calculation of each instruction can be as follows.

1. Branch Instruction (BR):

The processor reads the offset from the instruction and

checks the condition code bits. If they match the specified

condition, the program counter is updated with the current

PC plus the offset shifted left by 1. Otherwise, the program

counter is simply incremented by one.

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Opcode (4 bits): xxxx

CC (3 bits): zpn

Offset (9 bits): yyyyyyyyy

Implementation:

- If CC matches the current state of the processor's NZP flags, increment

PC by signed offset and fetch the next instruction. Otherwise, simply
fetch the next instruction.

2. Add Instruction (ADD):

The add instruction adds the value of two source registers and stores the
result in a destination register.

Opcode (4 bits): xxx1

Source Register 1 (3 bits): xx1

Source Register 2 (3 bits): xx2

Destination Register (3 bits): xxx

Implementation:

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- Load the contents of Source Register 1 and Source Register 2 into two
temporary registers, TR1 and TR2, respectively.

- Add the contents of TR1 and TR2 and store the result in the destination
register.

- Update the NZP flag based on the result.

3. Load Word Instruction (LDW):

The Load Word Instruction loads a 16-bit word from memory into a
register.

Opcode (4 bits): xx10

Base Register (3 bits): xxx

Destination Register (3 bits): xxx

Offset (6 bits): yyyyyy

Implementation:

- Calculate the effective memory address by adding the contents of Base

Register and Offset.

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- Load the 16-bit word at the calculated memory address into the
destination register.

- Update the NZP flag based on the result.

4. Store Word Instruction (SDW):

The Store Word Instruction stores a 16-bit word from a register into
memory.

Opcode (4 bits): xx11

Source Register (3 bits): xxx

Base Register (3 bits): xxx

Offset (6 bits): yyyyyy

Implementation:

- Calculate the effective memory address by adding the contents of Base

Register and Offset.

- Store the contents of Source Register into the word at the calculated
memory address.

- Update the NZP flag based on the result.

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REFERANCES

Google.com

ChatGPT

techtarget.com
elprocus.com
chegg.com

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