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    This document describes a lab assignment to design an 8-function arithmetic logic unit (ALU) using Verilog behavioral modeling and case statements. It includes code for the main ALU module that uses a case statement to perform different operations (addition, subtraction, AND, OR, etc.) based on a 3-bit select input. It also includes a test bench module that applies different select inputs over time and monitors the output. The goal is to implement an 8-function ALU and synthesize the design in Xilinx.

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    eee111 lab7

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    ETE 419_lab7

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    This document describes a lab assignment to design an 8-function arithmetic logic unit (ALU) using Verilog behavioral modeling and case statements. It includes code for the main ALU module that uses a case statement to perform different operations (addition, subtraction, AND, OR, etc.) based on a 3-bit select input. It also includes a test bench module that applies different select inputs over time and monitors the output. The goal is to implement an 8-function ALU and synthesize the design in Xilinx.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    5 views3 pages

    ETE 419 - Lab7

    Uploaded by

    nsu admission
    This document describes a lab assignment to design an 8-function arithmetic logic unit (ALU) using Verilog behavioral modeling and case statements. It includes code for the main ALU module that uses a case statement to perform different operations (addition, subtraction, AND, OR, etc.) based on a 3-bit select input. It also includes a test bench module that applies different select inputs over time and monitors the output. The goal is to implement an 8-function ALU and synthesize the design in Xilinx.

    Copyright:

    © All Rights Reserved
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    of 3

    EEE413/ETE419/CSE413

    Verilog-HDL: Modeling and simulation

    Lab07: Design a 8 function ALU using case statement in Behavioral


    modeling. Also do the synthesis in Xilinx

    CODE
    Main Module:

    module alu(out,select,a,b);
    output [4:0]out;
    input [3:0] a,b;
    input [2:0] select;
    reg [4:0]out;
    always@(select,a,b)
    begin
    case(select)
    3’b000: out =a;
    3’b001: out =a+b;
    3’b010: out =a-b;
    3’b011: out =a&b;
    3’b100: out =a|b;
    3’b101: out =a<<b;
    3’b110: out =a>>b;
    3’b111: out =a>b;
    default:$display(“invalid”);
    endcase
    end
    endmodule
    Test Bench:

    module stimulus;
    wire [4:0] out;
    reg [3:0] a, b;
    reg [2:0] select;
    alu a1(out, select, a, b);

    initial
    begin
    $monitor (“out=%d, a=%d, b=%d, select=%b”, out, a, b, select);
    end

    initial
    begin
    a=4’d10; b=4’d5; S=3’b000;
    #5 S=3’b001;
    #5 S=3’b010;
    #5 S=3’b011;
    #5 S=3’b100;
    #5 S=3’b101;
    #5 S=3’b110;
    #5 S=3’b111;
    #5$stop;
    end
    endmodule

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