EC403 U20EC073

Experiment – 8
Aim: Write a Verilog code to implement a 8-bit ring counter using blocking and non-blocking.
Verify the functionality using test bench. Report utilization, timing and power. Also perform
post synthesis and post implementation functional stimulation.
Software: Xilinx Vivado
Non – blocking
1. Code
module non-blocking_ring(
input clk_073, reset_073,
output reg [7:0]output_073 = 8'b10000000
);
always@(posedge clk_073, posedge reset_073)
begin
if(reset_073 == 1'b1) output_073 = 8'b10000000;
else begin
output_073 <= output_073 << 1;
output_073[0] <= output_073[7];
end
end
endmodule

2. Test Bench
module test;
reg CLK;
reg RESET;
wire [7:0]count_out;

non_blocking_ring RingCounter_inst (
.clk_073(CLK),
.reset_073(RESET),
.output_073(count_out)
);

always begin
#5 CLK = ~CLK;
end

initial begin
CLK = 0;
RESET = 1;
#10 RESET = 0;
end

always @(count_out) begin

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EC403 U20EC073

$display("count_out = %b", count_out);

end

initial begin
#1000;
$finish;
end

endmodule
3. RTL Analysis Schemati
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EC403 U20EC073

i. Behavioral Simulation

ii. Post-Synthesis Timing Simulation

iii. Post-Implementation Timing Simulation

4. Report

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EC403 U20EC073

i. Timing

ii. Utilization

iii. Power

Blocking
1. Code
module ring_counter_blocking(
input clk_073, reset_073,
output reg [7:0]output_073 = 8'b10000000
);
always@(posedge clk_073, posedge reset_073)
begin
if(reset_073 == 1'b1) output_073 = 8'b10000000;
else begin
output_073 = {output_073[6:0],output_073[7]};
end
end
endmodule

2. Test Bench

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EC403 U20EC073

module test;

reg CLK;
reg RESET;
wire [7:0]count_out;

blocking RingCounter_inst (
.clk_073(CLK),
.reset_073(RESET),
.output_073(count_out)
);

always begin
#5 CLK = ~CLK;
end

initial begin
CLK = 0;
RESET = 1;
#10 RESET = 0;
end

always @(count_out) begin

$display("count_out = %b", count_out);
end

initial begin
#1000;
$finish;
end

endmodule

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EC403 U20EC073

3. RTL Analysis Schematic

_073

_073
_073

_073

4. Simulation
a. Behavioral Simulation

b. Post-Synthesis Timing Simulation

c. Post-Implementation Timing Simulation

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EC403 U20EC073

5. Report
a. Timing

b. Utilization

c. Power

Conclusion: After performing this experiment, we tested the functionality of 8-bit ring
counter using both non-blocking and blocking methodology and got satisfactory results.

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