Accelerating RTL Simulation

Techniques
Lior Grinzaig
ADVA Optical Networking

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 Agenda
• Why simulation time is crucial?

• Variety of methods for acceleration

– “micro code” modifications

– “macro code” modifications

• Finding the bottlenecks

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 Why simulation time is crucial?
• Development and Debug becomes slow and clumsy.

• Frequent context-switches, reduce efficiency and

lead to mistakes.

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Variety of methods for acceleration
• Hardware level.

• Simulator level.

• Code level.
– General programming coding style.

– Coding style for HDL simulation & verification.

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 Variety of methods for acceleration
• I divide the code level acceleration methods into 2 types:
 Micro code modifications.

 Macro code modifications.

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 Examples for micro code modification
• Sensitivity Lists/Triggering Events

• Time tracking

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 Sensitivity Lists/Triggering Events
• Remember - triggering event causes code execution.

• Remove unnecessary triggering conditions.

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 Synchronous Example
• Consider this code:

always @(posedge clk)

begin
if ( (VALID == 1) && (READY == 1) )
begin
count++;
end
end

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 Synchronous Example
• Modification:

Initial begin
forever
begin
wait ( (VALID == 1) && (READY == 1) );
count++;
@(posedge clk);
end
end

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 Asynchronous Example
• Consider this code:
wire IN0 = IN;
wire #(25) IN1 = IN0;
wire #(25) IN2 = IN1;
wire #(25) IN3 = IN2;

always @(*)
begin
case (DELAY_SEL)
2'd0 : OUT = IN0 ;
2'd1 : OUT = IN1 ;
2'd2 : OUT = IN2 ;
2'd3 : OUT = IN3 ;
endcase
end

• Complexity of ~N2 (N is the number of phases).

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 Asynchronous Example
• Modification based on system understanding:
wire IN0 = IN && (DELAY_SEL=='d0);
wire #(25) IN1 = IN && (DELAY_SEL=='d1);
wire #(50) IN2 = IN && (DELAY_SEL=='d2);
wire #(75) IN3 = IN && (DELAY_SEL=='d3);

always @(*)
begin
case (DELAY_SEL)
4'd0 : OUT = IN0 ;
4'd1 : OUT = IN1 ;
4'd2 : OUT = IN2 ;
4'd3 : OUT = IN3 ;
endcase
end

• Complexity of ~N.
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 Asynchronous Example
This type of modification caused a simulation of SoC of
40M gates to run faster by a factor of 2.

How?
– The delay module was instantiated on each bit of 128 bits
bus.
– There where 128 possible phases.
– That bus run on the fastest bus in the testbench.

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 Time tracking
• Many times we need to have this code:
Wait ‘X’ time after event ‘Y’ occurred.

• The simplest way - use #<time>.

• But, what if the time depends on clock cycles?

And what if the clock frequency can change?

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 Time tracking
• The obvious solution is to use cycle counter:
int cycleDelay=100;
event startDelay; //triggered by some logic

initial
begin
@( startDelay);
repeat (cycleDelay) @(posedge clk);
do_something();
end
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 Time tracking
• It is possible to keep using #:
initial begin
@( startDelay);
@(posedge clk);
samplePosedge1 = $realtime;
@(posedge clk);
samplePosedge2 = $realtime;
period = samplePosedge2 - samplePosedge1;
->delay;
end

initial begin
@(delay);
#( period * ( cycleDelay – 2 ) ); // 2 clocks were "wasted"
do_somthing();
end
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 Macro code modifications

• Looking at the DUT/testbench as a system of blocks.

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Examples for macro code modification
• Using different Code for regression, development,
and debug.

• System modes.

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 Using Different Code
• Flexible use of BFM/stub.
• Disable analysis components.

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Example For Flexible Use
parameter DIVIDER1_SIMPLIFIED_MODEL = 0;

generate if ( ! DIVIDER1_SIMPLIFIED_MODEL )
begin :package_model
divider u_divider1
(
.port_A (a),
.port_B (b),
.port_C (c)
);
end
else
begin : simplified_model
simpified_divider u_divider1
(
.port_A (a),
.port_B (b),
.port_C (c)
);
end endgenerate 19
 Flexible Use of BFM/stub
• You can choose when to use what:
– Debug/development mode.
– Full / mini regression.
– Per test/tests-list.

• The same principal can be used for disabling analysis

components at the TB.

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 System modes
• Understand the system scenarios.

• Leave in reset. Gate clocks.

• Find optimal clock scheme for simulation time.

• Use Non-system scenarios for debug mode.

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 Finding the bottlenecks
• How to find out where is my problem?
– profiler.
– Analyze by stages.

• Measure the results:

– Measure it right.
– Compare it right.
– Statistical analysis.

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 To Conclude…
• There is hope!
– Slow simulations are not necessarily decreed by fate.

• There are tools!

– Use the profiler.

• It worth your time!

– Faster simulation will save both debug and development time.
– Engineers as well as managers should pay attention to the
importance of coding efficiently for simulation.

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 Questions

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