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  • A73 Lab-6

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    Prashant Lalwani
    2 views6 pages
    This document describes an experiment with the aim of designing circuits with select inputs that can function as either a half subtractor, half adder, full subtractor, or full adder depending on the select input. The experiment involves coding the circuits in Xilinx Vivado, analyzing the RTL schematic, synthesizing the design, implementing the design, and simulating the behavior, post-synthesis timing, and post-implementation timing. Results for timing analysis, resource utilization, and power analysis are presented for two circuit assignments. The conclusion indicates that the design was optimized and verified successfully per the given specifications.

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    A73 lab-6

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    This document describes an experiment with the aim of designing circuits with select inputs that can function as either a half subtractor, half adder, full subtractor, or full adder depending on the select input. The experiment involves coding the circuits in Xilinx Vivado, analyzing the RTL schematic, synthesizing the design, implementing the design, and simulating the behavior, post-synthesis timing, and post-implementation timing. Results for timing analysis, resource utilization, and power analysis are presented for two circuit assignments. The conclusion indicates that the design was optimized and verified successfully per the given specifications.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    2 views6 pages

    A73 Lab-6

    Uploaded by

    Prashant Lalwani
    This document describes an experiment with the aim of designing circuits with select inputs that can function as either a half subtractor, half adder, full subtractor, or full adder depending on the select input. The experiment involves coding the circuits in Xilinx Vivado, analyzing the RTL schematic, synthesizing the design, implementing the design, and simulating the behavior, post-synthesis timing, and post-implementation timing. Results for timing analysis, resource utilization, and power analysis are presented for two circuit assignments. The conclusion indicates that the design was optimized and verified successfully per the given specifications.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 6

    EC403 U20EC073

    Experiment – 6
    Aim:
    1. Design a circuit with select input(s), such that
    a. If s = 0, circuit will work as Half Subtractor.
    b. If s = 1, circuit will work as Half Adder.
    2. Design a circuit with select input(s), such that
    a. If s = 0, circuit will work as Full Subtractor.
    b. If s = 1, circuit will work as Full Adder.
    Software: Xilinx Vivado
    Assignment - 1
    a. Code

    073 073 073


    073 073

    073 073 073


    073 073
    073 073

    b. RTL Analysis Schematic

    073

    073
    073

    073

    073 073

    073

    c. Synthesis Schematic
    073
    073 073
    073
    073
    073
    073
    073
    073 073
    073 073

    VLSI Design
    EC403 U20EC073

    d. Implementation Schematic
    073
    073 073
    073
    073
    073
    073
    073
    073 073
    073 073

    e. Simulation
    i. Behavioral Simulation

    073
    073
    073
    073
    073

    ii. Post-Synthesis Timing Simulation

    073
    073
    073
    073
    073

    073

    073
    073

    iii. Post-Implementation Timing Simulation

    073
    073
    073
    073
    073

    073

    073
    073

    VLSI Design
    EC403 U20EC073

    Report
    a. Timing

    b. Utilization

    c. Power

    Assignment – 2
    Codes
    a. RTL Analysis Schematic

    073

    073

    073

    073
    073
    073

    073
    073

    VLSI Design
    EC403 U20EC073

    b. Synthesis Schematic
    073
    073

    073
    073
    073
    073
    073 073
    073

    073 073
    073 073
    073

    c. Implementation Schematic
    073
    073

    073
    073
    073
    073
    073 073
    073

    073 073
    073 073
    073

    d. Simulation
    i. Behavioral Simulation

    073
    073
    073
    073
    073
    073

    VLSI Design
    EC403 U20EC073

    ii. Post-Synthesis Timing Simulation

    073
    073
    073
    073
    073
    073
    073

    073
    073
    073
    073

    iii. Post-Implementation Timing Simulation

    073
    073
    073
    073
    073
    073
    073

    073
    073
    073
    073

    Report
    a. Timing

    b. Utilization

    VLSI Design
    EC403 U20EC073

    c. Power

    Conclusion: In this experiment I got results as per the given design, got optimized and good
    results in the synthesis and Implementation. Overall design verified Successfully.

    VLSI Design

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