LAB 6

EXPERIMENT 5

4:1 multiplexer using gates

QUCS
SUBCIRCUIT

CIRCUIT
OUTPUT

VERILOG
FOUR INPUT AND GATE

FOUR INPUT OR GATE

VERILOG CODE

TESTBENCH
GTKWAVE

8:1 multiplexer using gates

QUCS
SUBCIRCUIT (CASCADING)
CIRCUIT

OUTPUT
VERILOG
VERILOG CODE

TESTBENCH
GTKWAVE

LOGIC IMPLIMENTATION OF f(A, B, C, D) = ∑ m(1, 3, 4, 7)

QUCS
CIRCUIT
OUTPUT

LOGIC IMPLIMENTATION OF f(A, B, C, D) = ∑ m(1, 4, 9, 12, 14)

QUCS
CIRCUIT
OUTPUT

1: 4 de-multiplexer
QUCS
CIRCUIT
OUTPUT

VERILOG
VERILOG CODE

TESTBENCH
GTKWAVE