Professional Documents
Culture Documents
PART I
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Page 1
INDEX
Sr.
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Date
Sign
Marks
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Practical 1
Implementation of Basic Digital Gates using VHDL
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Page 3
SYMBOL:
RTL VIEWER:
DELAY MATRIX:
Y~0
A
B
OUTPUT WAVEFORM:
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SYMBOL:
RTL VIEWER:
DELAY MATRIX:
Y~0
A
B
OUTPUT WAVEFORM:
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OUTPUT WAVEFORM:
*****************************************************
TO IMPLEMENT THE NOR GATE USING VHDL
VHDL PROGRAM:
LIBRARY IEEE;
ENTITY NOR2 IS
PORT (A,B : IN
BIT;
Y : OUT BIT);
END NOR2;
ARCHITECTURE NORGATE OF NOR2 IS
BEGIN
Y <= A NOR B;
END NORGATE;
OUTPUT WAVEFORM:
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OUTPUT WAVEFORM:
*******************************************************
TO IMPLEMENT THE XNOR GATE USING VHDL
VHDL PROGRAM:
LIBRARY IEEE;
ENTITY XNOR2 IS
PORT (A,B : IN BIT;
Y : OUT BIT);
END XNOR2;
ARCHITECTURE XNORGATE OF XNOR2 IS
BEGIN
Y <= A XNOR B;
END XNORGATE;
OUTPUT WAVEFORM:
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Page 7
Practical 2
Implementation of Boolean Logic functions using
VHDL
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Page 8
Function-1
VHDL PROGRAM:
LIBRARY IEEE;
ENTITY example1 IS
PORT (x1, x2, x3 : IN BIT ;
f : OUT BIT) ;
END example1;
ARCHITECTURE LogicFunc OF example1 IS
BEGIN
f <= (x1 AND x2) OR (NOT x2 AND x3);
END LogicFunc;
OUTPUT WAVFORM:
FLOORPLAN EDITOR:
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Page 9
Function-2
VHDL PROGRAM:
LIBRARY IEEE;
ENTITY example2 IS
PORT ( x1, x2, x3, x4 : IN
BIT ;
f, g
: OUT BIT ) ;
END example2;
ARCHITECTURE LogicFunc OF example2 IS
BEGIN
f <= (x1 AND x3) OR (NOT x3 AND x2);
g <= (NOT x3 OR x1) AND (NOT x3 OR x4);
END LogicFunc;
OUTPUT WAVEFORM:
DELAY MATRIX:
FLOORPLAN EDITOR:
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Page 11
Practical 3
Implementation of 1-bit Half-Adder and Full-Adder
using VHDL
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Page 12
OUTPUT WAVEFORM:
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OUTPUT WAVEFORM:
DELAY MATRIX:
FLOORPLAN EDITOR:
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Page 14
Practical 4
Implementation of 4-bit Full-Adder in VHDL
using different methodology
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Page 15
X(0)
X(1)
X(2)
X(3)
S(1)
S(2)
S(3)
S(0)
1 BIT
FULL
ADDER
Cin
Y(0)
1 BIT
FULL
ADDER
C0
Y(1)
1 BIT
FULL
ADDER
C1
Y(2)
1 BIT
FULL
ADDER
C2
Y(3)
VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.fulladd_package.all;
ENTITY adder IS
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
Cout : OUT STD_LOGIC);
END adder;
ARCHITECTURE Structure OF adder IS
SIGNAL C : STD_LOGIC_VECTOR(1 TO 3);
BEGIN
stage0: fulladd PORT MAP ( Cin, X(0), Y(0), S(0), C(1) );
stage1: fulladd PORT MAP ( C(1), X(1), Y(1), S(1), C(2) );
stage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) );
stage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout );
END Structure;
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Cout
SYMBOL:
OUTPUT WAVEFORM:
DELAY MATRIX:
FLOORPLAN EDITOR:
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OUTPUT WAVEFORM:
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OUTPUT WAVEFORM:
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OUTPUT WAVEFORM:
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Practical 5
USE OF PROCESS STATEMENT
Implementation of Basic Digital Gates
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OUTPUT WAVEFORM:
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FLOORPLAN EDITOR:
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Practical 6
Implementation of 4-bit Comparator in VHDL
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Page 25
OUTPUT WAVEFORM:
DELAY MATRIX
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FLOORPLAN EDITOR:
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Practical 7
A. Implementation of BCD Generator using VHDL
B. Implementation of BCD-to-7-Segment Decoder
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Page 28
a
b
c
d
e
f
g
w0
w1
w2
w3
d
(b) 7-segment display
w3 w2 w1 w0
0
0
0
0
1
1
1
1
0
0
(a) Code
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
1
1
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Page 29
VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY seg7 IS
PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
leds : OUT STD_LOGIC_VECTOR(1 TO 7) );
END seg7;
ARCHITECTURE Behavior OF seg7 IS
BEGIN
PROCESS ( bcd )
BEGIN
CASE bcd IS
---- abcdefg
WHEN "0000" => leds <= "1111110";
WHEN "0001" => leds <= "0110000";
WHEN "0010" => leds <= "1101101";
WHEN "0011" => leds <= "1111001";
WHEN "0100" => leds <= "0110011";
WHEN "0101" => leds <= "1011011";
WHEN "0110" => leds <= "1011111";
WHEN "0111" => leds <= "1110000";
WHEN "1000" => leds <= "1111111";
WHEN "1001" => leds <= "1110011";
WHEN OTHERS => leds <= "-------";
END CASE;
END PROCESS;
END Behavior;
OUTPUT WAVEFORM:
DELAY MATRIX:
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Page 30
Practical 8
Implementation of Multiplexers using VHDL
2 to 1 MUX (Behavioral Level)
4 to 1 MUX (Behavioral Level)
16 to 1 MUX using Package (Structural Level)
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Page 31
VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux2to1 IS
PORT ( w0, w1, s : IN STD_LOGIC;
f : OUT STD_LOGIC );
END mux2to1;
ARCHITECTURE Behavior OF mux2to1 IS
BEGIN
WITH s SELECT
f <= w0 WHEN '0',
w1 WHEN OTHERS;
END Behavior;
SYMBOL:
OUTPUT WAVEFORM:
DELAY MATRIX:
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Page 32
VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux4to1 IS
PORT ( w0, w1, w2, w3 : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
f : OUT STD_LOGIC );
END mux4to1;
ARCHITECTURE Behavior OF mux4to1 IS
BEGIN
WITH s SELECT
f <= w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS;
END Behavior;
SYMBOL:
OUTPUT WAVEFORM:
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Page 33
PACKAGE DEFINITION
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE mux4to1_package IS
COMPONENT mux4to1
PORT ( w0, w1, w2, w3 : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
f : OUT STD_LOGIC );
END COMPONENT;
END mux4to1_package;
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Page 34
VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
USE work.mux4to1_package.all;
ENTITY mux16to1 IS
PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15);
s : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
f : OUT STD_LOGIC );
END mux16to1;
ARCHITECTURE Structure OF mux16to1 IS
SIGNAL m : STD_LOGIC_VECTOR(0 TO 3);
BEGIN
Mux1: mux4to1 PORT MAP
( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) );
Mux2: mux4to1 PORT MAP
( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) );
Mux3: mux4to1 PORT MAP
( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) );
Mux4: mux4to1 PORT MAP
( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) );
Mux5: mux4to1 PORT MAP
( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f );
END Structure;
OUTPUT WAVEFORM:
DELAY MATRIX:
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Page 35
Practical 9
Implementation of Decoders using VHDL
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Page 36
<=
<=
<=
<=
<=
"0001";
"0010";
"0100";
"1000";
"0000";
OUTPUT WAVEFORM:
DELAY MATRIX:
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Page 37
OUTPUT WAVEFORM:
DELAY MATRIX:
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OUTPUT WAVEFORM:
DELAY MATRIX:
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Practical 10
Implementation of a Priority Encoder using VHDL
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Page 40
OUTPUT WAVEFORM:
DELAY MATRIX:
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Page 41
Practical 11
Implementation of various Flip-Flops using VHDL
D-type LATCH
D Flip-Flop
JK Flip-Flop
T Flip-Flop
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Page 42
IMPLEMENTATION OF D-LATCH
VHDL PROGRAM:
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY D_latch IS
PORT ( D, clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC ) ;
END D_latch ;
ARCHITECTURE Behavior OF D_latch IS
BEGIN
PROCESS ( D, clk )
BEGIN
IF clk = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
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: IN STD_LOGIC;
: IN STD_LOGIC;
: IN STD_LOGIC;
: OUT STD_LOGIC);
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: IN STD_LOGIC ;
: IN STD_LOGIC ;
: BUFFER STD_LOGIC);
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Page 47
Practical 12
Implementation of 4-Bit Shift Register using VHDL
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Page 48
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Practical 13
Implementation of 4-bit Binary Up-Counter
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Page 50
: IN
STD_LOGIC;
: IN
STD_LOGIC;
: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
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Page 51
Practical 14
FINITE STATE MACHINE (FSM) DESIGN
MOORE FSM
MEALY FSM
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Page 52
DESIGN STATEMENT:
1. The circuit has one input, w and one output z
2. All changes in the circuit occur on the positive edge of a clock signal
3. The output z equal to 1 if during two immediately preceding clock cycles the input
w was equal to 1. Otherwise the value of z equal to 0.
Sequences of input and output signals
Clockcycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 0 1 0 0 1 1 0
Combinational
circuit
Flip-flops
Combinational
circuit
Clock
STATE DIAGRAM
Reset
w = 1
w = 0
A z = 0
B z = 0
w = 0
w = 1
w = 0
C z = 1
w = 1
STATE TABLE
Present State
A
B
C
Next State
w=0
A
A
A
w =1
B
C
C
Out Put
z
0
0
1
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Page 53
VHDL PROGRAM:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MOORE IS
PORT ( CLOCK : IN STD_LOGIC ;
W : IN STD_LOGIC ;
RESETN : IN STD_LOGIC ;
Z : OUT STD_LOGIC );
END MOORE;
ARCHITECTURE BEHAVIOR OF MOORE IS
TYPE STATE_TYPE IS (A, B, C);
SIGNAL Y : STATE_TYPE;
BEGIN
PROCESS (RESETN, CLOCK)
BEGIN
IF RESETN = '0' THEN
Y <= A;
ELSIF (CLOCK'EVENT AND CLOCK = '1') THEN
CASE Y IS
WHEN A => IF W = '0' THEN
Y <= A;
ELSE
Y <= B;
END IF ;
WHEN B => IF W = '0' THEN
Y <= A;
ELSE
Y <= C;
END IF ;
WHEN C => IF W = '0' THEN
Y <= A;
ELSE
Y <= C;
END IF;
END CASE;
END IF;
END PROCESS;
Z <= '1' WHEN Y = C ELSE '0';
END BEHAVIOR;
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Page 54
Combinational
circui
Flip-flops
Combinational
circuit
Clock
STATE DIAGRAM
Reset
w = 1z = 0
w = 0z = 0
w = 1 z = 1
w = 0z = 0
STATE TABLE
Present State
A
B
Next State
w=0
A
A
w =1
B
B
Out Put
z
w=0
w =1
0
1
0
1
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Page 55
VHDL PROGRAM:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MEALY IS
PORT ( CLOCK, RESETN : IN STD_LOGIC;
W : IN STD_LOGIC;
Z : OUT STD_LOGIC);
END MEALY;
ARCHITECTURE BEHAVIOR OF MEALY IS
TYPE STATE_TYPE IS (A, B);
SIGNAL Y : STATE_TYPE;
BEGIN
PROCESS ( RESETN, CLOCK )
BEGIN
IF RESETN = '0' THEN
Y <= A;
ELSIF (CLOCK'EVENT AND CLOCK = '1') THEN
CASE Y IS
WHEN A =>
IF W = '0' THEN Y <= A;
ELSE Y <= B;
END IF ;
WHEN B =>
IF W = '0' THEN Y <= A;
ELSE Y <= B;
END IF;
END CASE;
END IF;
END PROCESS;
PROCESS (Y, W)
BEGIN
CASE Y IS
WHEN A =>
Z <= '0';
WHEN B =>
Z <= W;
END CASE;
END PROCESS;
END BEHAVIOR;
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