NAME : A.

SAI KUMAR DATE :

ROLL NO : 18H61A0461 PAGE NO : 1

EXPERIMENT -1
HDL CODE TO REALIZE ALL THE LOGIC GATES
AIM:
To realize all logic gates using Xilinx VIVADO 2015.2 with Verilog HDL programming language
and to implement on FPGA Kit.

APPARATUS:
SOFTWARE REQUIRED: Xilinx VIVADO 2015.2

HARDWARE REQUIRED: FPGA kit, Personal Computer

THEORY:
AND GATE: AND gate is an electronic circuit that gives a high output (1) results only if all the
inputs to the AND gate are high(1). If none or not all inputs to the AND gate are high, a low output
results.

OR GATE: The OR gate is an electronic circuit that gives a high output (1) results if one or both
the inputs to the gate are high (1). If neither input is high, a low output (0) results.

NOT GATE: NOT gate is a logical gate which only inverts the input digital signal.

NAND GATE: The output of the NAND gate is always at logic 1 and only goes to logic 0 when
all the inputs to the NAND gate are at logic 1.

NOR: A high output (1) results if both the inputs to the gate are low (0); if one or both input is
high (1), a low output (0) results.

X-OR: It is a digital logic gate that gives a true (1 or HIGH) output when the number of true inputs
is odd. An XOR gate implements an exclusive or; that is, a true output results if one, and only one,
of the inputs to the gate is true

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 2

LOGIC GATES SYMBOLS AND TRUTH TABLES:

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 3

SOURCE CODE: (Data Flow Model)

module logicgates(c,d,e,f,g,h,i,a,b);

input a,b; #define inputs

output c,d,e,f,g,h,i; #define outputs

assign c=a&b; #AND logic

assign d=a|b; #OR logic

assign e=~(a&b); #NAND logic

assign f=~(a|b); #NOR logic

assign g=~a; #NOT logic

assign h=a^b; #EX-ORlogic

assign i=~(a^b); #EX-NOR logic

endmodule

TEST BENCH:
module logicgates_tb();

reg a,b;

wire c,d,e,f,g,h,i;

logicgates uut(.c(c),.d(d),.e(e),.f(f),.g(g),.h(h),.i(i),.a(a),.b(b));

initial begin

a=0;b=0;#10;

a=0;b=1;#10;

a=1;b=0;#10;

a=1;b=1;

end

endmodule

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 5

SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 4

CONSTRAINT FILE:
set_property IOSTANDARD LVCMOS33 [get_ports a]

set_property IOSTANDARD LVCMOS33 [get_ports b]

set_property IOSTANDARD LVCMOS33 [get_ports c]

set_property IOSTANDARD LVCMOS33 [get_ports d]

set_property IOSTANDARD LVCMOS33 [get_ports e]

set_property IOSTANDARD LVCMOS33 [get_ports f]

set_property IOSTANDARD LVCMOS33 [get_ports g]

set_property IOSTANDARD LVCMOS33 [get_ports h]

set_property IOSTANDARD LVCMOS33 [get_ports i]

set_property PACKAGE_PIN H17 [get_ports a]

set_property PACKAGE_PIN G22 [get_ports b]

set_property PACKAGE_PIN T22 [get_ports c]

set_property PACKAGE_PIN T21 [get_ports d]

set_property PACKAGE_PIN U22 [get_ports e]

set_property PACKAGE_PIN U21 [get_ports f]

set_property PACKAGE_PIN V22 [get_ports g]

set_property PACKAGE_PIN W22 [get_ports h]

set_property PACKAGE_PIN U19 [get_ports i]

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 7

SYNTHESIS REPORT:

DESIGN

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 6

PROCEDURE:
1. Start the Xilinx VIVADO 2015.2 project navigator by using desktop shortcut or by using start
and create a new project. Specify the project name and location and select the project type as RTL
project and click on NEXT project. In the window go to File.

2. Select board as Zed board Zynq evaluation & development kit and click NEXT and finish.

3. Click on design sources in project manager window and select add sources. A new screen will
appear then select add or create design sources.

4. Click on „+‟ symbol and select file and create new file and select file type as Verilog and give
file location.

5. Define ports and verify defined I/O ports.

6. Verify name of the source file and also go to project manager window check whether design
source file is added or not.

7. Write the Verilog code in the Verilog editor and save it.

8. For TESTBENCH go to project manager window and right click on the simulation sources and
select add sources again a new screen will appear then click on create add simulation sources.

9. Click on „+‟ symbol and select file and create new file and select file type as Verilog and give
file location for simulation source file.

10. In project manager window check the add source and click on “set as top”.

11. Then write the test bench code and set all input combinations of the design in the editor window
and save it.

12. Run simulation and select on behavioural simulation then the simulation waveform will appear
in the new window, take the snapshot of that simulation waveform.

13. Now click on RTL analysis and open elaborated design and take the snapshot of schematic
diagram.

14. Finally click on synthesis design and click on RUN synthesis and check the project summary.

15. Take the snapshot of project summary on power device utilization reports.

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 8

APPLICATIONS:
1. Logic gates used for building blocks for all the computers, smart phones and internet.
2. They are used for combinational circuits such as adders, subtractors.
3. They are used for flip-flops as memory units.

ADVANTAGES:

1. Logic gates perform logical operations on behalf of Boolean logics.

2. Less expensive in design and use.
3. Switching time is faster than analog circuits.

DISADVANTAGES:
1. Logic gates use more energy than analog circuits and produce more heat.
2. For activation it requires a power system as battery.

PRECAUTIONS:
Make sure that there is no syntax error and verify the functionality of the program

RESULT:
Verilog code in data flow modeling is implemented for all logic gates using Xilinx VIVADO
2015.2.Synthesis report is obtained and simulation is done for all logic gates using different
input combinations. The simulation result are verified with the truth table.

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 10

EXPERIMENT -2
DESIGN OF FULL ADDER

AIM:
To design the full adder using Xilinx VIVADO 2015.2 with Verilog HDL programming language
and to implement on FPGA Kit.

APPARATUS:
SOFTWARE REQUIRED: Xilinx VIVADO 2015.2

HARDWARE REQUIRED: FPGA kit, Personal Computer

THEORY:
Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs
are A and B and the third input is an input carry as C-IN. The output carry is designated as C-
OUT and the normal output is designated as S which is SUM. A full adder logic is designed in
such a manner that can take eight inputs together to create a byte-wide adder and cascade the
carry bit from one adder to the another. A full adder can also be constructed from two half
adders by connecting A and B to the input of one half adder, then taking its sum-output S as one
of the inputs to the second half adder and Cin as its other input, and finally the carry outputs from
the two half-adders are connected to an OR gate. The sum-output from the second half adder is
the final sum output (S) of the full adder and the output from the OR gate is the final carry output
(Cout). The critical path of a full adder runs through both XOR gates and ends at the sum bit s.

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 11

FULL ADDER

TRUTH TABLE

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 14

SOURCE CODE: (Data Flow Model)

module fulladder(
input a,

input b,

input cin,

output s,

output cout

);

assign s=a^b^cin;

assign cout=(a&b)|(b&cin)|(cin&a);

endmodule

SOURCE CODE: (Behavioural Model)

module fulladder1(

input a,

input b,

input cin,

output s,

output cout

);

reg s,cout;

always@({a,b,cin})

begin

case({a,b,cin})

3'b000:begin s=0;cout=0;end

3'b001:begin s=1;cout=0;end

3'b010:begin s=1;cout=0;end

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

 NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 17
:

Schematic Diagram:

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 15

3'b011:begin s=0;cout=1;end

3'b100:begin s=1;cout=0;end

3'b101:begin s=0;cout=1;end

3'b110:begin s=0;cout=1;end

3'b111:begin s=1;cout=1;end

endcase

end

endmodule

TEST BENCH:
module fulladder_tb();

reg a,b,cin;

wire s,cout;

fulladder uut(.s(s),.cout(cout),.a(a),.b(b),.cin(cin));

initial begin

a=0;b=0;cin=0;#10;

a=0;b=0;cin=1;#10;

a=0;b=1;cin=0;#10;

a=0;b=1;cin=1;#10;

a=1;b=0;cin=0;#10;

a=1;b=0;cin=1;#10;

a=1;b=1;cin=0;#10;

a=1;b=1;cin=1;

end

endmodule

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 18

SIMULATION WAVEFORM

SYNTHESIS REPORT

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 12

PROCEDURE:

1. Start the Xilinx VIVADO 2015.2 project navigator by using desktop shortcut or by using start
and create a new project. Specify the project name and location and select the project type as RTL
project and click on NEXT project. In the window go to File.

2. Select board as Zed board Zynq evaluation & development kit and click NEXT and finish.

3. Click on design sources in project manager window and select add sources. A new screen will
appear then select add or create design sources.

4. Click on „+‟ symbol and select file and create new file and select file type as Verilog and give
file location.

5. Define ports and verify defined I/O ports.

6. Verify name of the source file and also go to project manager window check whether design
source file is added or not.

7. Write the Verilog code in the Verilog editor and save it.

8. For TESTBENCH go to project manager window and right click on the simulation sources and
select add sources again a new screen will appear then click on create add simulation sources.

9. Click on „+‟ symbol and select file and create new file and select file type as Verilog and give
file location for simulation source file.

10. In project manager window check the add source and click on “set as top”.

11. Then write the test bench code and set all input combinations of the design in the editor window
and save it.

12. Run simulation and select on behavioural simulation then the simulation waveform will appear
in the new window, take the snapshot of that simulation waveform.

13. Now click on RTL analysis and open elaborated design and take the snapshot of schematic
diagram.

14. Finally click on synthesis design and click on RUN synthesis and check the project summary.

15. Take the snapshot of project summary on power device utilization reports.

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

 NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 19

DESIGN:

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE

NAME : A. SAI KUMAR DATE :
ROLL NO : 18H61A0461 PAGE NO : 16

APPLICATIONS:
1. A Full Adder's circuit can be used as a part of many other larger circuits like Ripple
Carry Adder, which adds n-bits simultaneously.
2. The dedicated multiplication circuit uses Full Adder's circuit to perform Carryout
Multiplication.
3. Full Adders are used in ALU- Arithmetic Logic Unit.

ADVANTAGES:

Full swing output.

Low power consumption.

High speed and robustness to supply voltage scaling.

Transistor sizing

DISADVANTAGES:

It does not incorporate (or take care of) previous carry for addition.

PRECAUTIONS:

Make sure that there is no syntax error and verify the functionality of the program

RESULT:
Verilog code in data flow modeling and behavioural model is implemented for a full adder using
Xilinx VIVADO 2015.2.Synthesis report is obtained and simulation is done for all logic gates
using different input combinations. The simulation result are verified with the truth table.

VLSI LAB ANURAG GROUP OF INSTITUTIONS ECE