IRF520

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Power MOSFET
D
FEATURES
• Dynamic dV/dt rating
TO-220AB
• Repetitive avalanche rated Available

• 175 °C operating temperature Available

G • Fast switching
• Ease of paralleling Available

S
• Simple drive requirements
D • Material categorization: for definitions of compliance
G S
please see www.vishay.com/doc?99912
N-Channel MOSFET
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
PRODUCT SUMMARY example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
VDS (V) 100
RDS(on) (Ω) VGS = 10 V 0.27 DESCRIPTION
Qg max. (nC) 16 Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
Qgs (nC) 4.4
ruggedized device design, low on-resistance and
Qgd (nC) 7.7 cost-effectiveness.
Configuration Single The TO-220AB package is universally preferred for all
commercial-industrial applications at power dissipation
levels to approximately 50 W. The low thermal resistance
and low package cost of the TO-220AB contribute to its
wide acceptance throughout the industry.

ORDERING INFORMATION
Package TO-220AB
Lead (Pb)-free IRF520PbF
Lead (Pb)-free and halogen-free IRF520PbF-BE3

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS 100
V
Gate-source voltage VGS ± 20
TC = 25 °C 9.2
Continuous drain current VGS at 10 V ID
TC = 100 °C 6.5 A
Pulsed drain current a IDM 37
Linear derating factor 0.40 W/°C
Single pulse avalanche energy b EAS 200 mJ
Repetitive avalanche current a IAR 9.2 A
Repetitive avalanche energy a EAR 6.0 mJ
Maximum power dissipation TC = 25 °C PD 60 W
Peak diode recovery dV/dt c dV/dt 5.5 V/ns
Operating junction and storage temperature range TJ, Tstg -55 to +175
°C
Soldering recommendations (peak temperature) d For 10 s 300
10 lbf · in
Mounting torque 6-32 or M3 screw
1.1 N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 25 V, starting TJ = 25 °C, L = 3.5 mH, Rg = 25 Ω, IAS = 9.2 A (see fig. 12)
c. ISD ≤ 9.2 A, dI/dt ≤ 110 A/μs, VDD ≤ VDS, TJ ≤ 175 °C
d. 1.6 mm from case

S21-0819-Rev. C, 02-Aug-2021 1 Document Number: 91017

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THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT
Maximum junction-to-ambient RthJA - 62
Case-to-sink, flat, greased surface RthCS 0.50 - °C/W
Maximum junction-to-case (drain) RthJC - 2.5

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = 250 μA 100 - - V
VDS temperature coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.13 - V/°C
Gate-source threshold voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V
Gate-source leakage IGSS VGS = ± 20 V - - ± 100 nA
VDS = 100 V, VGS = 0 V - - 25
Zero gate voltage drain current IDSS μA
VDS = 80 V, VGS = 0 V, TJ = 150 °C - - 250
Drain-source on-state resistance RDS(on) VGS = 10 V ID = 5.5 A b - - 0.27 Ω
Forward transconductance gfs VDS = 50 V, ID = 5.5 Ab 2.7 - - S
Dynamic
Input capacitance Ciss - 360 -
VGS = 0 V,
Output capacitance Coss VDS = 25 V, - 150 - pF
f = 1.0 MHz, see fig. 5
Reverse transfer capacitance Crss - 34 -
Total gate charge Qg - - 16
ID = 9.2 A, VDS = 80 V,
Gate-source charge Qgs VGS = 10 V - - 4.4 nC
see fig. 6 and 13 b
Gate-drain charge Qgd - - 7.7
Turn-on delay time td(on) - 8.8 -
Rise time tr VDD = 50 V, ID = 9.2 A, - 30 -
ns
Turn-off delay time td(off) Rg = 18 Ω, RD = 5.2 Ω, see fig. 10 b - 19 -
Fall time tf - 20 -
Gate input resistance Rg f = 1 MHz, open drain 1.0 - 5.0 Ω
Between lead, D
Internal drain inductance LD - 4.5 -
6 mm (0.25") from
package and center of G
nH
Internal source inductance LS die contact - 7.5 -
S

Drain-Source Body Diode Characteristics

Continuous source-drain diode current IS MOSFET symbol D

- - 9.2
showing the
A
integral reverse G

Pulsed diode forward current a ISM p - n junction diode S

- - 37

Body diode voltage VSD TJ = 25 °C, IS = 9.2 A, VGS = 0 Vb - - 1.8 V

Body diode reverse recovery time trr - 110 260 ns
TJ = 25 °C, IF = 9.2 A, dI/dt = 100 A/μs b
Body diode reverse recovery charge Qrr - 0.53 1.3 μC
Forward turn-on time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %

S21-0819-Rev. C, 02-Aug-2021 2 Document Number: 91017

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

RDS(on), Drain-to-Source On Resistance

VGS 3.0
ID = 9.2 A
Top 15 V
10 V VGS = 10 V
2.5
8.0 V
101
ID, Drain Current (A)

7.0 V
6.0 V
5.5 V 2.0

(Normalized)
5.0 V
Bottom 4.5 V
1.5

4.5 V
100 1.0

0.5
20 µs Pulse Width
TC = 25 °C
0.0
10-1 100 101 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 180
91017_01 VDS, Drain-to-Source Voltage (V) 91017_04 TJ, Junction Temperature (°C)

Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 4 - Normalized On-Resistance vs. Temperature

750
VGS VGS = 0 V, f = 1 MHz
Top 15 V Ciss = Cgs + Cgd, Cds Shorted
10 V Crss = Cgd
101 600
8.0 V Coss = Cds + Cgd
ID, Drain Current (A)

Capacitance (pF)

7.0 V
6.0 V
5.5 V 450
Ciss
5.0 V
Bottom 4.5 V 4.5 V
300
100 Coss

150
Crss
20 µs Pulse Width
TC = 175 °C
0
10-1 100 101 100 101

91017_02 VDS, Drain-to-Source Voltage (V) 91017_05 VDS, Drain-to-Source Voltage (V)

Fig. 2 - Typical Output Characteristics, TC = 175 °C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

20
ID = 9.2 A
VGS, Gate-to-Source Voltage (V)

25 °C VDS = 80 V
101
16
ID, Drain Current (A)

VDS = 50 V
175 °C
VDS = 20 V
12

100
4
20 µs Pulse Width For test circuit
VDS = 50 V see figure 13
0
4 5 6 7 8 9 10 0 4 8 12 16 20
91017_03 VGS, Gate-to-Source Voltage (V) 91017_06 QG, Total Gate Charge (nC)

Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

S21-0819-Rev. C, 02-Aug-2021 3 Document Number: 91017

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RD
101 VDS
175 °C
ISD, Reverse Drain Current (A)

VGS
D.U.T.
RG
+
- VDD

25 °C 10 V
100
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

VGS = 0 V
10-1 VDS
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
90 %
91017_07 VSD, Source-to-Drain Voltage (V)

Fig. 7 - Typical Source-Drain Diode Forward Voltage

10 %
VGS
103 td(on) tr td(off) tf
5
Operation in this area limited
by RDS(on)
2
Fig. 10b - Switching Time Waveforms
ID, Drain Current (A)

102
5
10 µs
2
100 µs
10
5 1 ms
2
10 ms
1
5
TC = 25 °C
2 TJ = 175 °C
Single Pulse
0.1
2 5 2 5 2 5 2 5
0.1 1 10 102 103

91017_08 VDS, Drain-to-Source Voltage (V)

Fig. 8 - Maximum Safe Operating Area

10

8
ID, Drain Current (A)

0
25 50 75 100 125 150 175

91017_09 TC, Case Temperature (°C)

Fig. 9 - Maximum Drain Current vs. Case Temperature

S21-0819-Rev. C, 02-Aug-2021 4 Document Number: 91017

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Vishay Siliconix

10
Thermal Response (ZthJC)

0 - 0.5
1
0.2
0.1 PDM
0.05
0.1 0.02 t1
0.01 Single Pulse t2
(Thermal Response) Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-2
10-5 10-4 10-3 10-2 0.1 1 10

91017_11 t1, Rectangular Pulse Duration (s)

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

L VDS
VDS
Vary tp to obtain tp
required IAS VDD
RG D.U.T +
V DD
- VDS
IAS A
10 V
tp 0.01 Ω
IAS

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

600
ID
EAS, Single Pulse Energy (mJ)

Top 3.8 A
500 6.5 A
Bottom 9.2 A
400

300

200

100

VDD = 25 V
0
25 50 75 100 125 150 175

91017_12c Starting TJ, Junction Temperature (°C)

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

S21-0819-Rev. C, 02-Aug-2021 5 Document Number: 91017

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Current regulator
Same type as D.U.T.

QG 50 kΩ
10 V 12 V 0.2 µF
0.3 µF

QGS QGD +
VDS
D.U.T. -

VG
VGS

3 mA

Charge
IG ID
Current sampling resistors

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

Peak Diode Recovery dV/dt Test Circuit

+ Circuit layout considerations

D.U.T.
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- +
-

Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test

Driver gate drive

Period P.W.
D=
P.W. Period

VGS = 10 Va

D.U.T. lSD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD

Re-applied
voltage
Body diode forward drop
Inductor current

Ripple ≤ 5 % ISD

Note
a. VGS = 5 V for logic level devices

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91017.

S21-0819-Rev. C, 02-Aug-2021 6 Document Number: 91017

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 Package Information
www.vishay.com
Vishay Siliconix
TO-220-1

A
E
F

ØP

Q
H(1)
D

1 2 3
L(1)

M*

b(1)
L

C
b
e
J(1)
e(1)

MILLIMETERS INCHES
DIM.
MIN. MAX. MIN. MAX.
A 4.24 4.65 0.167 0.183
b 0.69 1.02 0.027 0.040
b(1) 1.14 1.78 0.045 0.070
c 0.36 0.61 0.014 0.024
D 14.33 15.85 0.564 0.624
E 9.96 10.52 0.392 0.414
e 2.41 2.67 0.095 0.105
e(1) 4.88 5.28 0.192 0.208
F 1.14 1.40 0.045 0.055
H(1) 6.10 6.71 0.240 0.264
J(1) 2.41 2.92 0.095 0.115
L 13.36 14.40 0.526 0.567
L(1) 3.33 4.04 0.131 0.159
ØP 3.53 3.94 0.139 0.155
Q 2.54 3.00 0.100 0.118
ECN: E21-0621-Rev. D, 04-Nov-2021
DWG: 6031
Note
• M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM

Revison: 04-Nov-2021 1 Document Number: 66542

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Revision: 01-Jan-2023 1 Document Number: 91000