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ATtiny824/826/827
tinyAVR® 2 Family
Introduction
The ATtiny424/426/427 and ATtiny824/826/827 microcontrollers of the tinyAVR® 2 family are using the AVR® CPU
with hardware multiplier, running at up to 20 MHz, with 4/8 KB Flash, 512B/1 KB of SRAM, and 128B of EEPROM
available in a 14-, 20-, and 24-pin package. The family uses the latest technologies from Microchip with a flexible and
low-power architecture, including an Event System, advanced digital peripherals, and accurate analog features such
as a 12-bit differential ADC with Programmable Gain Amplifier (PGA).
Pins
14 20 24
Devices with different flash memory sizes typically also have different SRAM and EEPROM.
The name of a device in the tinyAVR® 2 family is decoded as follows:
Memory Overview
The following table shows the memory overview of the entire family, but further documentation describes only the
ATtiny424/426/427 and ATtiny824/826/827 devices.
Table 1. Memory Overview
Peripheral Overview
Table 2. Peripheral Overview
...........continued
Device ATtiny424 ATtiny426 ATtiny427
ATtiny824 ATtiny826 ATtiny827
External interrupts 12 18 22
Event system channels 6 6 6
CCL LUTs 4 4 4
Real-Time Counter (RTC) 1 1 1
16-bit Timer/Counter type A (TCA) 1 1 1
16-bit Timer/Counter type B (TCB) 2 2 2
12-bit Timer/Counter type D (TCD) - - -
USART/SPI host 2 2 2
SPI 1 1 1
TWI (I2C) 1 1 1
ADC (channels) 1 (9) 1 (15) 1 (15)
DAC - - -
Analog Comparators (inputs) 1 (2p/2n) 1 (3p/3n) 1 (4p/3n)
Peripheral Touch Controller (PTC) (self cap/mutual cap - - -
channels)
Unified Program and Debug Interface (UPDI) activated by 1 1 1
shared pin using high-voltage signal or fuse override
Features
• High-Performance Low-Power AVR® CPU
– Running at up to 20 MHz
– Single-cycle I/O access
– Two-level interrupt controller with vectored interrupts
– Two-cycle hardware multiplier
– Supply voltage range: 1.8V to 5.5V
• Memories
– 4/8 KB In-System self-programmable Flash memory
– 512B/1 KB SRAM
– 128B EEPROM
– 32B of user row in nonvolatile memory that can keep data during chip-erase and be programmed while the
device is locked
– Write/erase endurance
• Flash 10,000 cycles
• EEPROM 100,000 cycles
– Data retention: 40 years at 55°C
• System
– Power-on Reset (POR)
– Brown-out Detection (BOD)
– Clock options
• Lockable 20 MHz Low-Power internal oscillator
• 32.768 kHz Ultra-Low Power (ULP) internal oscillator
• 32.768 kHz external crystal oscillator
• External clock input
– Single-pin Unified Program and Debug Interface (UPDI)
– Three sleep modes
• Idle with all peripherals running and immediate wake-up time
• Standby with configurable operation of selected peripherals
• Power-Down with full data retention
• Peripherals
– One 16-bit Timer/Counter type A (TCA) with a dedicated period register and three PWM channels
– Two 16-bit Timer/Counters type B (TCB) with input capture and simple PWM functionality
– One 16-bit Real-Time Counter (RTC) running from external 32.768 kHz crystal or internal 32.768 kHz ULP
oscillator
– Two Universal Synchronous Asynchronous Receiver Transmitters (USART) with fractional baud rate
generator, auto-baud, and start-of-frame detection
– Host/Client Serial Peripheral Interface (SPI)
– Host/Client Two-Wire Interface (TWI) with dual address match
• Standard mode (Sm, 100 kHz)
• Fast mode (Fm, 400 kHz)
• Fast mode plus (Fm+, 1 MHz)
– Event System for CPU independent and predictable inter-peripheral signaling
– Configurable Custom Logic (CCL) with four programmable Look-Up Tables (LUT)
– One Analog Comparator (AC) with scalable reference input
– One 12-bit differential 375 ksps Analog-to-Digital Converter (ADC) with Programmable Gain Amplifier
(PGA) and up to 15 input channels
– Multiple internal voltage references
• 1.024V
• 2.048V
• 2.500V
• 4.096V
• VDD
– Automated Cyclic Redundancy Check (CRC) flash memory scan
– Watchdog Timer (WDT) with Window Mode, with a separate on-chip oscillator
– External interrupt on all general purpose pins
• I/O and Packages
– Up to 22 programmable I/O pins
– 14-pin
• SOIC
• TSSOP
– 20-pin
• SOIC
• SSOP
• VQFN 3x3 mm
– 24-pin
• VQFN 4x4 mm
• Temperature Ranges
– -40°C to 85°C (industrial)
– -40°C to 125°C (extended)
• Speed Grades (-40°C to 85°C)
– 0-5 MHz @ 1.8V – 5.5V
– 0-10 MHz @ 2.7V – 5.5V
– 0-20 MHz @ 4.5V – 5.5V
• Speed Grades (-40°C to 125°C)
– 0-8 MHz @ 2.7V - 5.5V
– 0-16 MHz @ 4.5V - 5.5V
• VAO variants available: Designed, manufactured, tested, and qualified in accordance with AEC-Q100
requirements for automotive applications.
Table of Contents
Introduction.....................................................................................................................................................1
Features......................................................................................................................................................... 4
1. Block Diagram.......................................................................................................................................13
2. Pinout.................................................................................................................................................... 14
2.1. 14-Pin SOIC, TSSOP................................................................................................................. 14
2.2. 20-Pin SOIC, SSOP................................................................................................................... 15
2.3. 20-Pin VQFN.............................................................................................................................. 16
2.4. 24-Pin VQFN.............................................................................................................................. 17
4. Hardware Guidelines.............................................................................................................................19
4.1. General Guidelines.....................................................................................................................19
4.2. Connection for Power Supply.....................................................................................................19
4.3. Connection for RESET............................................................................................................... 20
4.4. Connection for UPDI Programming............................................................................................21
4.5. Connecting External Crystal Oscillators..................................................................................... 21
4.6. Connection for External Voltage Reference............................................................................... 22
5. Conventions.......................................................................................................................................... 23
5.1. Numerical Notation.....................................................................................................................23
5.2. Memory Size and Type...............................................................................................................23
5.3. Frequency and Time...................................................................................................................23
5.4. Registers and Bits...................................................................................................................... 24
5.5. ADC Parameter Definitions........................................................................................................ 25
6. AVR® CPU............................................................................................................................................ 28
6.1. Features..................................................................................................................................... 28
6.2. Overview.................................................................................................................................... 28
6.3. Architecture................................................................................................................................ 28
6.4. Arithmetic Logic Unit (ALU)........................................................................................................ 30
6.5. Functional Description................................................................................................................30
6.6. Register Summary......................................................................................................................34
6.7. Register Description................................................................................................................... 34
7. Memories.............................................................................................................................................. 38
7.1. Overview.................................................................................................................................... 38
7.2. Memory Map.............................................................................................................................. 38
7.3. In-System Reprogrammable Flash Program Memory................................................................38
7.4. SRAM Data Memory.................................................................................................................. 39
33.14. TWI..........................................................................................................................................487
33.15. VREF.......................................................................................................................................490
33.16. ADC.........................................................................................................................................491
33.17. TEMPSENSE.......................................................................................................................... 493
33.18. AC........................................................................................................................................... 493
33.19. UPDI........................................................................................................................................494
33.20. Programming Time..................................................................................................................495
Trademarks................................................................................................................................................ 573
1. Block Diagram
Flash
EEPROM
I
N NVMCTRL
/
ADCn O
AINm
PGA PORTS U
Pxn
T
PORTMUX
AINPm D
AINNm ACn E D
A
OUT V A GPIOR T
A
E T B
VREFA VREF N A U
T B
U CPUINT S
R S
O Detectors/power
EVOUTx EVSYS U
T
control VDD
I System
LUTn_INm N POR VREG
LUTn_OUT CCL G
Management
RSTCTRL BOD VLM
N
E
T CLKCTRL
WOm TCAn W
O SLPCTRL
R
K Clock generation
WO TCBn
CLKOUT
OSC20M
RXD
EXTCLK
TXD
USARTn WDT
XCK
OSCULP32K
XDIR TOSC1
SDA
SCL TWIn
2. Pinout
VDD 1 14 GND
PA4 2 13 PA3 (EXTCLK)
PA5 3 12 PA2
PA6 4 11 PA1
PA7 5 10 PA0 (UPDI/RESET)
(TOSC1) PB3 6 9 PB0
(TOSC2) PB2 7 8 PB1
Power Functionality
Ground Clock/Crystal
VDD 1 20 GND
PA4 2 19 PA3 (EXTCLK)
PA5 3 18 PA2
PA6 4 17 PA1
PA7 5 16 PA0 (UPDI/RESET)
PB5 6 15 PC3
PB4 7 14 PC2
(TOSC1) PB3 8 13 PC1
(TOSC2) PB2 9 12 PC0
PB1 10 11 PB0
Power Functionality
Ground Clock/Crystal
PA0 (UPDI/RESET)
PC1
PC3
PC2
PA1
16
20
19
18
17
PA2 1 15 PC0
(EXTCLK) PA3 2 14 PB0
GND 3 13 PB1
VDD 4 12 PB2 (TOSC2)
PA4 5 11 PB3 (TOSC1)
10
6
7
8
9
PB4
PA5
PA6
PA7
PB5
Power Functionality
Ground Clock/Crystal
PA0 (UPDI/RESET)
PC5
PC4
PC3
PC2
PA1
24
23
22
21
20
19
PA2 1 18 PC1
(EXTCLK) PA3 2 17 PC0
GND 3 16 PB0
VDD 4 15 PB1
PA4 5 14 PB2 (TOSC2)
PA5 6 13 PB3 (TOSC1)
10
11
12
7
8
9
PA6
PA7
PB7
PB6
PB5
PB4
Power Functionality
Ground Clock/Crystal
VQFN 20-pin
SSOP/SOIC 20-pin
TSSOP/SOIC 14-pin
Name
(1,2)
Notes:
1. Pin names are of type Pxn with x being the PORT instance (A, B) and n the pin number. Notation for signals is
PORTx_PINn.
2. All pins can be used for external interrupt where pins Px2 and Px6 of each port have full asynchronous
detection. All pins can be used as event input.
3. AIN[15:8] can not be used as negative ADC input for differential measurements.
4. Alternative pin location. For selecting an alternative pin location, refer to the PORTMUX section.
4. Hardware Guidelines
This section contains guidelines for designing or reviewing electrical schematics using AVR 8-bit microcontrollers.
The information presented here is a brief overview of the most common topics. More detailed information can be
found in application notes, listed in this section where applicable.
This section covers the following topics:
• General guidelines
• Connection for power supply
• Connection for RESET
• Connection for UPDI (Unified Program and Debug Interface)
• Connection for external crystal oscillators
• Connection for VREF (external voltage reference)
As mentioned at the beginning of this section, all values used in examples are typical values. The actual design may
require other values.
C3 C2 C1
GND
Important: For systems that frequently cycle VDD or experience fast VDD transients, it is recommended
to add an additional decoupling capacitor (C3) if the power supply slew rate exceeds the slew rate limits.
Refer to the Supply Voltage section in the Electrical Characteristics for details about power supply slew
rate limits.
SW1
C1
GND
A resistor in series with the switch can safely discharge the filtering capacitor. This prevents a current surge when
shorting the filtering capacitor, as this may cause a noise spike that can harm the system.
VDD
UPDI 1 2 VDD
NC 3 4 NC C2 C1
NC 5 6 GND
GND
100-mil 6-pin
2x3 connector
The decoupling capacitor between VDD and GND must be placed as close to the pin pair as possible. The
decoupling capacitor must be included even if the UPDI connector is not included in the circuit.
The following figure shows how to connect an external 32.768 kHz crystal oscillator.
Figure 4-4. Recommended External 32.768 kHz Oscillator Connection Circuit Schematic
TOSC1
C1
32.768 kHz
Crystal Oscillator
TOSC2
C2
+ VREFA
Voltage
Reference
C1
- GND
5. Conventions
Symbol Description
165 Decimal number
0b0101 Binary number
‘0101’ Binary numbers are given without prefix if unambiguous
Symbol Description
KB kilobyte (210B = 1024B)
MB megabyte (220B = 1024 KB)
GB gigabyte (230B = 1024 MB)
b bit (binary ‘0’ or ‘1’)
B byte (8 bits)
1 kbit/s 1,000 bit/s rate
1 Mbit/s 1,000,000 bit/s rate
1 Gbit/s 1,000,000,000 bit/s rate
word 16-bit
Symbol Description
kHz 1 kHz = 103 Hz = 1,000 Hz
MHz 1 MHz = 106 Hz = 1,000,000 Hz
GHz 1 GHz = 109 Hz = 1,000,000,000 Hz
ms 1 ms = 10-3s = 0.001s
µs 1 µs = 10-6s = 0.000001s
ns 1 ns = 10-9s = 0.000000001s
Symbol Description
R/W Read/Write accessible register bit. The user can read from and write to this bit.
R Read-only accessible register bit. The user can only read this bit. Writes will be ignored.
W Write-only accessible register bit. The user can only write this bit. Reading this bit will return an
undefined value.
BITFIELD Bitfield names are shown in uppercase. Example: INTMODE.
BITFIELD[n:m] A set of bits from bit n down to m. Example: PINA[3:0] = {PINA3, PINA2, PINA1, PINA0}.
Reserved Reserved bits, bit fields, and bit field values are unused and reserved for future use. For
compatibility with future devices, always write reserved bits to ‘0’ when the register is written.
Reserved bits will always return zero when read.
PERIPHERALn If several instances of the peripheral exist, the peripheral name is followed by a single number to
identify one instance. Example: USARTn is the collection of all instances of the USART module,
while USART3 is one specific instance of the USART module.
PERIPHERALx If several instances of the peripheral exist, the peripheral name is followed by a single capital
letter (A-Z) to identify one instance. Example: PORTx is the collection of all instances of the
PORT module, while PORTB is one specific instance of the PORT module.
Reset Value of a register after a Power-on Reset. This is also the value of registers in a peripheral after
performing a software Reset of the peripheral, except for the Debug Control registers.
SET/CLR/TGL Registers with SET/CLR/TGL suffix allow the user to clear and set bits in a register without doing
a read-modify-write operation.
Each SET/CLR/TGL register is paired with the register it is affecting. Both registers in a register
pair return the same value when read.
Example: In the PORT peripheral, the OUT and OUTSET registers form such a register pair. The
contents of OUT will be modified by a write to OUTSET. Reading OUT and OUTSET will return
the same value.
Writing a ‘1’ to a bit in the CLR register will clear the corresponding bit in both registers.
Writing a ‘1’ to a bit in the SET register will set the corresponding bit in both registers.
Writing a ‘1’ to a bit in the TGL register will toggle the corresponding bit in both registers.
Note: For peripherals with different register sets in different modes, <peripheral_instance_name> and
<peripheral_name> must be followed by a mode name, for example:
// TCA0 in Normal Mode (SINGLE) uses waveform generator in frequency mode
TCA0.SINGLE.CTRL=TCA_SINGLE_WGMODE_FRQ_gc;
Offset Error The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5
LSb). Ideal value: 0 LSb.
Figure 5-1. Offset Error
Output Code
Ideal ADC
Actual ADC
Offset
Error
VREF Input Voltage
Gain Error After adjusting for offset, the gain error is found as the deviation of the last transition (e.g.,
0x3FE to 0x3FF for a 10-bit ADC) compared to the ideal transition (at 1.5 LSb below
maximum). Ideal value: 0 LSb.
Ideal ADC
Actual ADC
Integral After adjusting for offset and gain error, the INL is the maximum deviation of an actual
Nonlinearity (INL) transition compared to an ideal transition for any code. Ideal value: 0 LSb.
Figure 5-3. Integral Nonlinearity
Output Code
INL
Ideal ADC
Actual ADC
Differential The maximum deviation of the actual code width (the interval between two adjacent
Nonlinearity (DNL) transitions) from the ideal code width (1 LSb). Ideal value: 0 LSb.
Figure 5-4. Differential Nonlinearity
Output Code
0x3FF
1 LSb
DNL
0x000
Quantization Error Due to the quantization of the input voltage into a finite number of codes, a range of input
voltages (1 LSb wide) will code to the same value. Always ±0.5 LSb.
Absolute Accuracy The maximum deviation of an actual (unadjusted) transition compared to an ideal transition
for any code. This is the compound effect of all errors mentioned before. Ideal value: ±0.5
LSb.
6. AVR® CPU
6.1 Features
• 8-Bit, High-Performance AVR RISC CPU:
– 135 instructions
– Hardware multiplier
• 32 8-Bit Registers Directly Connected to the ALU
• Stack in RAM
• Stack Pointer Accessible in I/O Memory Space
• Direct Addressing of up to 64 KB of Unified Memory
• Efficient Support for 8-, 16-, and 32-Bit Arithmetic
• Configuration Change Protection for System-Critical Features
• Native On-Chip Debugging (OCD) Support:
– Two hardware breakpoints
– Change of flow, interrupt, and software breakpoints
– Run-time read-out of Stack Pointer (SP) register, Program Counter (PC), and Status Register (SREG)
– Register file read- and writable in Stopped mode
6.2 Overview
The AVR CPU can access memories, perform calculations, control peripherals, execute instructions from the
program memory, and handle interrupts.
6.3 Architecture
To maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate buses for
program and data. The instructions in the program memory are executed with a single-level pipeline. While one
instruction is being executed, the next instruction is prefetched from the program memory. This enables instructions
to be executed on every clock cycle.
Refer to the Instruction Set Summary section for a summary of all AVR instructions.
Instruction
Decode
Status
Register ALU
CLK_CPU
The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALU operation
using two register operands is executed, and the result is stored in the destination register.
Figure 6-3. Single Cycle ALU Operation
T1 T2 T3 T4
clkCPU
Total Execution Time
During interrupts or subroutine calls, the return address is automatically pushed on the stack as a word, and the SP is
decremented by two. The return address consists of two bytes and the Least Significant Byte (LSB) is pushed on the
stack first (at the higher address). As an example, a byte pointer return address of 0x0006 is saved on the stack as
0x0003 (shifted one bit to the right), pointing to the fourth 16-bit instruction word in the program memory. The return
address is popped off the stack with RETI (when returning from interrupts) and RET (when returning from subroutine
calls), and the SP is incremented by two.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by
one when data are popped off the stack using the POP instruction.
To prevent corruption when updating the SP from software, a write to SPL will automatically disable interrupts for up
to four instructions or until the next I/O memory write, whichever comes first.
6.5.6.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
To write to registers protected by CCP, the following steps are required:
1. The software writes the signature that enables change of protected I/O registers to the CCP bit field in the
CPU.CCP register.
2. Within four instructions, the software must write the appropriate data to the protected register.
Most protected registers also contain a Write Enable/Change Enable/Lock bit. This bit must be written to ‘1’ in
the same operation as the data are written.
The protected change is immediately disabled if the CPU performs write operations to the I/O register or data
memory, if load or store accesses to Flash, NVMCTRL, or EEPROM are conducted, or if the SLEEP instruction
is executed.
0x00
... Reserved
0x03
0x04 CCP 7:0 CCP[7:0]
0x05
... Reserved
0x0C
7:0 SP[7:0]
0x0D SP
15:8 SP[15:8]
0x0F SREG 7:0 I T H S V N Z C
Name: CCP
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CCP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: SP
Offset: 0x0D
Reset: Top of stack
Property: -
The CPU.SP register holds the Stack Pointer (SP) that points to the top of the stack. After being reset, the SP points
to the highest internal SRAM address.
Only the number of bits required to address the available data memory, including external memory (up to 64 KB), is
implemented for each device. Unused bits will always read ‘0’.
The CPU.SPL and CPU.SPH register pair represents the 16-bit value, CPU.SP. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
To prevent corruption when updating the SP from software, a write to CPU.SPL will automatically disable interrupts
for the next four instructions or until the next I/O memory write, whichever comes first.
Bit 15 14 13 12 11 10 9 8
SP[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset
Bit 7 6 5 4 3 2 1 0
SP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset
Name: SREG
Offset: 0x0F
Reset: 0x00
Property: -
The Status Register contains information about the result of the most recently executed arithmetic or logic
instructions. For details about the bits in this register and how they are influenced by different instructions, see
the Instruction Set Summary section.
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
7. Memories
7.1 Overview
The main memories of the ATtiny424/426/427 and ATtiny824/826/827 devices are SRAM data memory space,
EEPROM data memory space, and Flash program memory space. Also, the peripheral registers are located in the
I/O memory space.
SIGROW 0x1100-0x11FF
FUSE 0x1280-0x1289
LOCKBIT 0x128A-0x12FF
USERROW 0x1300-0x137F
EEPROM 0x1400-0x14FF
256 Bytes
Flash Code
(Reserved)
32 KB
SRAM 0x3400-0x3FFF
3 KB
(Reserved) 0x4000-0x7FFF
In-System Reprogrammable
Flash 0x8000-0xFFFF
32 KB
APPEND: (CODESIZE*256)-1
Application Data
FLASHEND
...........continued
Property ATtiny42x ATtiny82x
Number of pages 4 4
Start address 0x1400 0x1400
...........continued
Memory Section CPU Access UPDI Access
Read Write Read Write
Other fuses including Yes No No No
LOCK
Notes:
1. Read operations marked No in the tables may appear to be successful, but the data is not valid. Hence, any
attempt of code validation through the UPDI will fail on these memory sections.
2. In the Locked mode, the USERROW can be written using the Fuse Write command, but the current
USERROW values cannot be read out.
Important: The only way to unlock a device is CHIPERASE. No application data is retained.
Name: LOCKBIT
Offset: 0x00
Default: 0xC5
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
LOCKBIT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 0 0 0 1 0 1
Name: WDTCFG
Offset: 0x00
Default: 0x00
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
WINDOW[3:0] PERIOD[3:0]
Access R R R R R R R R
Default 0 0 0 0 0 0 0 0
Name: BODCFG
Offset: 0x01
Default: 0x00
Property: -
The settings of the BOD will be loaded from this Fuse after a Reset.
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
LVL[2:0] SAMPFREQ ACTIVE[1:0] SLEEP[1:0]
Access R R R R R R R R
Default 0 0 0 0 0 0 0 0
Name: OSCCFG
Offset: 0x02
Default: 0x7E
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
OSCLOCK FREQSEL[1:0]
Access R R R
Default 0 1 0
Name: SYSCFG0
Offset: 0x05
Default: 0xF6
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
CRCSRC[1:0] TOUTDIS RSTPINCFG[1:0] EESAVE
Access R R R R R R
Default 1 1 1 0 1 0
Name: SYSCFG1
Offset: 0x06
Default: 0xFF
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
SUT[2:0]
Access R R R
Default 1 1 1
Name: APPEND
Offset: 0x07
Default: 0x00
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
APPEND[7:0]
Access R R R R R R R R
Default 0 0 0 0 0 0 0 0
Name: BOOTEND
Offset: 0x08
Default: 0x00
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
BOOTEND[7:0]
Access R R R R R R R R
Default 0 0 0 0 0 0 0 0
7.9.2.1 Device ID n
Name: DEVICEIDn
Offset: 0x00 + n*0x01 [n=0..2]
Reset: [Device ID]
Property: -
Each device has a device ID identifying the device and its properties such as memory sizes, pin count, and die
revision. This can be used to identify a device and hence, the available features by software. The Device ID consists
of three bytes: SIGROW.DEVICEID[2:0].
Bit 7 6 5 4 3 2 1 0
DEVICEID[7:0]
Access R R R R R R R R
Reset x x x x x x x x
Name: SERNUMn
Offset: 0x03 + n*0x01 [n=0..9]
Reset: [Byte n of device serial number]
Property: -
Each device has an individual serial number representing a unique ID. This can be used to identify a specific device
in the field. The serial number consists of ten bytes: SIGROW.SERNUM[9:0].
Bit 7 6 5 4 3 2 1 0
SERNUM[7:0]
Access R R R R R R R R
Reset x x x x x x x x
Name: OSCCAL16M0
Offset: 0x18
Reset: [Factory oscillator calibration value]
Property: -
Bit 7 6 5 4 3 2 1 0
OSCCAL16M[6:0]
Access R R R R R R R
Reset x x x x x x x
Name: OSCCAL16M1
Offset: 0x19
Reset: [Factory oscillator temperature calibration value]
Property: -
Bit 7 6 5 4 3 2 1 0
OSCCAL16MTCAL[3:0]
Access R R R R
Reset x x x x
Name: OSCCAL20M0
Offset: 0x1A
Reset: [Factory oscillator calibration value]
Property: -
Bit 7 6 5 4 3 2 1 0
OSCCAL20M[6:0]
Access R R R R R R R
Reset x x x x x x x
Name: OSCCAL20M1
Offset: 0x1B
Reset: [Factory oscillator temperature calibration value]
Property: -
Bit 7 6 5 4 3 2 1 0
OSCCAL20MTCAL[3:0]
Access R R R R
Reset x x x x
Name: TEMPSENSEn
Offset: 0x20 + n*0x01 [n=0..1]
Reset: [Temperature sensor calibration value]
Property: -
The Temperature Sensor Calibration registers contain correction factors for temperature measurements
from the on-chip sensor. SIGROW.TEMPSENSE0 is a correction factor for the gain/slope (unsigned) and
SIGROW.TEMPSENSE1 is a correction factor for the offset (signed).
Bit 7 6 5 4 3 2 1 0
TEMPSENSE[7:0]
Access R R R R R R R R
Reset x x x x x x x x
A
A
V
V
R
DATAH DATAH R
D
D
A
TEMP A
TEMP T
T
A
A
DATAL B DATAL B
U
U
S
S
For a 16-bit write operation, the low byte register (e.g., DATAL) of the 16-bit register must be written before the high
byte register (e.g., DATAH). Writing the low byte register will result in a write to the temporary (TEMP) register instead
of the low byte register, as shown in the left side of the figure above. When the high byte register of the 16-bit register
is written, TEMP will be copied into the low byte of the 16-bit register in the same clock cycle, as shown on the right
side of the same figure.
Figure 7-4. 16-Bit Register Read Operation
A
A
V
V
R
DATAH DATAH R
D
D
A
TEMP A
TEMP T
T
A
A
DATAL B DATAL B
U
U
S
S
For a 16-bit read operation, the low byte register (e.g., DATAL) of the 16-bit register must be read before the high
byte register (e.g., DATAH). When the low byte register is read, the high byte register of the 16-bit register is copied
into the temporary (TEMP) register in the same clock cycle, as shown on the left side of the figure above. Reading
the high byte register will result in a read from TEMP instead of the high byte register, as shown on the right side of
the same figure.
The described mechanism ensures that the low and high bytes of 16-bit registers are always accessed
simultaneously when reading or writing the registers.
Interrupts can corrupt the timed sequence if an interrupt is triggered during a 16-bit read/write operation, and a 16-bit
register within the same peripheral is accessed in the interrupt service routine. To prevent this, interrupts should
be disabled when writing or reading 16-bit registers. Alternatively, the temporary register can be read before and
restored after the 16-bit access in the interrupt service routine.
...........continued
Base Address Name Description
0x0F00 SYSCFG System Configuration
0x1000 NVMCTRL Nonvolatile Memory Controller
...........continued
Vector Program Peripheral Description
Number Address Source
(Word) (Name)
10 0x0A TCA0_CMP0 Normal: Timer/Counter Type A Compare channel 0 interrupt
TCA0_LCMP0 Split: Timer/Counter Type A Low Compare channel 0 interrupt
11 0x0B TCA0_CMP1 Normal: Timer/Counter Type A Compare channel 1 interrupt
TCA0_LCMP1 Split: Timer/Counter Type A Low Compare channel 1 interrupt
12 0x0C TCA0_CMP2 Normal: Timer/Counter Type A Compare channel 2 interrupt
TCA0_LCMP2 Split: Timer/Counter Type A Low Compare channel 2 interrupt
13 0x0D TCB0_INT Timer/Counter Type B Capture interrupt
14 0x0E TWI0_TWIS Two Wire Interface Client interrupt
15 0x0F TWI0_TWIM Two Wire Interface Host interrupt
16 0x10 SPI0_INT Serial Peripheral Interface 0 interrupt
17 0x11 USART0_RCX Universal Synchronous and Asynchronous Receiver and Transmitter 0
Receive Complete interrupt
18 0x12 USART0_DRE Universal Synchronous and Asynchronous Receiver and Transmitter 0
Data Register Empty interrupt
19 0x13 USART0_TXC Universal Synchronous and Asynchronous Receiver and Transmitter 0
Transmit Complete interrupt
20 0x14 AC0_AC Analog Comparator Compare interrupt
21 0x15 ADC0_ERROR Analog-to-Digital Converter Error interrupt
22 0x16 ADC0_RESRDY Analog-to-Digital Converter Result interrupt
23 0x17 ADC0_SAMPRDY Analog-to-Digital Converter Sample interrupt
24 0x18 PORTC_PORT PORT C External interrupt
25 0x19 TCB1_INT Timer/Counter Type B Capture interrupt
26 0x1A USART1_RCX Universal Synchronous and Asynchronous Receiver and Transmitter 1
Receive Complete interrupt
27 0x1B USART1_DRE Universal Synchronous and Asynchronous Receiver and Transmitter 1
Data Register Empty interrupt
28 0x1C USART1_TXC Universal Synchronous and Asynchronous Receiver and Transmitter 1
Transmit Complete interrupt
29 0x1D NVMCTRL_EE Non-Volatile Memory Controller Ready interupt
0x00 Reserved
0x01 REVID 7:0 REVID[7:0]
Name: REVID
Offset: 0x01
Reset: [revision ID]
Property: -
Bit 7 6 5 4 3 2 1 0
REVID[7:0]
Access R R R R R R R R
Reset
Name: GPIORn
Offset: 0x00 + n*0x01 [n=0..3]
Reset: 0x00
Property: -
These are general purpose registers that can be used to store data, such as global variables and flags, in the bit
accessible I/O memory space.
Bit 7 6 5 4 3 2 1 0
GPIOR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
10.1 Features
• Unified Memory
• In-System Programmable
• Self-Programming and Boot Loader Support
• Configurable Sections for Write Protection:
– Boot section for boot loader code or application code
– Application code section for application code
– Application data section for application code or data storage
• Signature Row for Factory-Programmed Data:
– ID for each device type
– Serial number for each device
– Calibration bytes for factory-calibrated peripherals
• User Row for Application Data:
– Can be read and written from software
– Can be written from UPDI on a locked device
– Content is kept after chip erase
10.2 Overview
The NVM Controller (NVMCTRL) is the interface between the CPU and Nonvolatile Memories (Flash, EEPROM,
Signature Row, User Row, and fuses). These are reprogrammable memory blocks that retain their values when they
are not powered. The Flash is mainly used for program storage and can also be used for data storage, while the
EEPROM, Signature Row, User Row, and fuses are used for data storage.
Nonvolatile
Memory Block
Program Memory Bus
`
Flash
EEPROM
Data Memory Bus
Signature Row
User Row
Fuses
Register access
NVMCTRL
10.3.1.1 Flash
The Flash is divided into a set of pages. A page is the basic unit addressed when programming the Flash. It is only
possible to write or erase a whole page at a time. One page consists of several words.
The Flash can be divided into three sections in blocks of 256 bytes for different security. The three different sections
are BOOT, Application Code (APPCODE), and Application Data (APPDATA).
BOOT
BOOTEND>0: 0x8000+BOOTEND*256
APPLICATION
CODE
APPEND>0: 0x8000+APPEND*256
APPLICATION
DATA
FLASHEND
Section Sizes
The sizes of these sections are set by the Boot Section End (FUSE.BOOTEND) fuse and the Application Code
Section End (FUSE.APPEND) fuse.
The fuses select the section sizes in blocks of 256 bytes. The BOOT section stretches from the start of the Flash until
BOOTEND. The APPCODE section runs from BOOTEND until APPEND, and the remaining area is the APPDATA
section.
Table 10-1. Setting Up Flash Sections
If BOOTEND is written to ‘0’, the entire Flash is regarded as the BOOT section. If APPEND is written to ‘0’ and
BOOTEND > 0, the APPCODE section runs from BOOTEND to the end of Flash (no APPDATA section). When
APPEND ≤ BOOTEND, the APPCODE section is removed, and the APPDATA runs from BOOTEND to the end of
Flash. When APPEND > BOOTEND, the APPCODE section spreads from BOOTEND until APPEND. The remaining
area is the APPDATA section.
If there is no boot loader software, it is recommended to use the BOOT section for Application Code.
Notes:
1. After Reset, the default vector table location is at the start of the APPCODE section. The peripheral interrupts
can be used in the code running in the BOOT section by relocating the interrupt vector table at the beginning
of this section. That is done by setting the IVSEL bit in the CPUINT.CTRLA register. Refer to the CPUINT
section for details.
2. If BOOTEND/APPEND, as resulted from BOOTEND and APPEND fuse setting, exceed the device
FLASHEND, the corresponding fuse setting is ignored, and the default value is used. Refer to “Fuse” in
the Memories section for default values.
10.3.1.2 EEPROM
The EEPROM is divided into a set of pages where one page consists of multiple bytes. The EEPROM has byte
granularity on the erase/write. Within one page, only the bytes marked to be updated will be erased/written. The byte
is marked by writing a new value to the page buffer for that address location.
10.3.2.1 Read
Reading of the Flash and EEPROM is done by using load instructions with an address according to the memory map.
Reading any of the arrays while a write or erase is in progress will result in a bus wait, and the instruction will be
suspended until the ongoing operation is complete.
10.3.2.3 Programming
For page programming, filling the page buffer and writing the page buffer into Flash, User Row, and EEPROM are
two separate operations.
Before programming a Flash page with the data in the page buffer, the Flash page must be erased. The page buffer
is also erased when the device enters a sleep mode. Programming an unerased Flash page will corrupt its content.
The Flash can either be written with the erase and write separately, or one command handling both:
Alternative 1:
1. Fill the page buffer.
2. Write the page buffer to Flash with the Erase and Write Page (ERWP) command.
Alternative 2:
1. Write to a location on the page to set up the address.
2. Perform an Erase Page (ER) command.
3. Fill the page buffer.
4. Perform a Write Page (WP) command.
The NVM command set supports both a single erase and write operation, and split Erase Page (ER) and Write
Page (WP) commands. This split commands enable shorter programming time for each command, and the erase
operations can be done during non-time-critical programming execution.
The EEPROM programming is similar, but only the bytes updated in the page buffer will be written or erased in the
EEPROM.
10.3.2.4 Commands
Reading the Flash/EEPROM and writing the page buffer is handled with normal load/store instructions. Other
operations, such as writing and erasing the memory arrays, are handled by commands in the NVM.
To execute a command in the NVM:
1. Confirm that any previous operation is completed by reading the Busy (EEBUSY and FBUSY) Flags in the
NVMCTRL.STATUS register.
2. Write the appropriate key to the Configuration Change Protection (CPU.CCP) register to unlock the NVM
Control A (NVMCTRL.CTRLA) register.
3. Write the desired command value to the CMD bit field in the Control A (NVMCTRL.CTRLA) register within the
next four instructions.
10.3.4 Interrupts
Table 10-2. Available Interrupt Vectors and Sources
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags
(NVMCTRL.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding bit in the Interrupt Control
(NVMCTRL.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the NVMCTRL.INTFLAGS register for
details on how to clear interrupt flags.
Register Key
NVMCTRL.CTRLA SPM
NVMCTRL.CTRLB IOREG
10.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
CMD[2:0]
Access R/W R/W R/W
Reset 0 0 0
10.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
BOOTLOCK APCWP
Access R/W R/W
Reset 0 0
10.5.3 Status
Name: STATUS
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
WRERROR EEBUSY FBUSY
Access R R R
Reset 0 0 0
Name: INTCTRL
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
EEREADY
Access R/W
Reset 0
Name: INTFLAGS
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
EEREADY
Access R/W
Reset 0
10.5.6 Data
Name: DATA
Offset: 0x06
Reset: 0x00
Property: -
The NVMCTRL.DATAL and NVMCTRL.DATAH register pair represents the 16-bit value, NVMCTRL.DATA. The low
byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset +
0x01.
Bit 15 14 13 12 11 10 9 8
DATA[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
10.5.7 Address
Name: ADDR
Offset: 0x08
Reset: 0x00
Property: -
The NVMCTRL.ADDRL and NVMCTRL.ADDRH register pair represents the 16-bit value, NVMCTRL.ADDR. The low
byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset +
0x01.
Bit 15 14 13 12 11 10 9 8
ADDR[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
11.1 Features
• All Clocks and Clock Sources are Automatically Enabled when Requested by Peripherals
• Internal Oscillators:
– 20 MHz oscillator (OSC20M)
– 32.768 kHz Ultra Low-Power Oscillator (OSCULP32K)
• External Clock Options:
– 32.768 kHz crystal oscillator (XOSC32K)
– External clock
• Main Clock Features:
– Safe run-time switching
– Prescaler with 1x to 64x division in 12 different settings
11.2 Overview
The Clock Controller (CLKCTRL) controls, distributes and prescales the clock signals from the available oscillators,
and supports internal and external clock sources.
The CLKCTRL is based on an automatic clock request system, implemented in all peripherals on the device. The
peripherals will automatically request the clocks needed. The request is routed to the correct clock source if multiple
clock sources are available.
The Main Clock (CLK_MAIN) is used by the CPU, RAM, and all peripherals connected to the I/O bus. The main clock
source can be selected and prescaled. Some peripherals can share the same clock source as the main clock or run
asynchronously to the main clock domain.
CLKOUT
NVM RAM CPU Peripherals RTC WDT BOD
BODCFG
CLK_MAIN
DIV8
Main Clock Switch RTC CLKSEL
DIV32
XOSC32K
EXTCLK
OSCULP32K
OSC20M
XOSC32KSEL
The clock system consists of the main clock and other asynchronous clocks:
• Main Clock
This clock is used by the CPU, RAM, Flash, the I/O bus, and all peripherals connected to the I/O bus. It is
always running in Active and Idle Sleep mode and can be running in Standby Sleep mode if requested.
The main clock CLK_MAIN is prescaled and distributed by the clock controller:
• CLK_CPU is used by the CPU, SRAM, and the NVMCTRL peripheral to access the nonvolatile memory
• CLK_PER is used by all peripherals that are not listed under asynchronous clocks
• Clocks running asynchronously to the main clock domain:
– CLK_RTC is used by the RTC/PIT. It will be requested when the RTC/PIT is enabled. The clock source for
CLK_RTC may only be changed if the peripheral is disabled.
– CLK_WDT is used by the WDT. It will be requested when the WDT is enabled.
– CLK_BOD is used by the BOD. It will be requested when the BOD is enabled in Sampled mode.
The clock source for the for the main clock domain is configured by writing to the Clock Select bits (CLKSEL) in
the Main Clock Control A register (CLKCTRL.MCLKCTRLA). The asynchronous clock sources are configured by
registers in the respective peripheral.
CAUTION
1. If an external clock source fails while used as the CLK_MAIN source, only the WDT can provide a
mechanism to switch back via System Reset.
2. Do not alter the properties of the external clock source while used as the CLK_MAIN source. This
can be interpreted as a clock failure.
CLK_MAIN is fed into a prescaler before it is used by the peripherals (CLK_PER) in the device. The prescaler divide
CLK_MAIN by a factor from 1 to 64.
Figure 11-1. Main Clock and Prescaler
OSC20M
Main Clock Prescaler
32.768 kHz Osc. CLK_MAIN CLK_PER
32.768 kHz crystal Osc. (Div 1, 2, 4, 8, 16, 32,
64, 6, 10, 24, 48)
External clock
The Main Clock and Prescaler configuration registers (CLKCTRL.MCLKCTRLA, CLKCTRL.MCLKCTRLB) are
protected by the Configuration Change Protection Mechanism, employing a timed write procedure for changing these
registers.
compensation values. The example code below demonstrates how to apply this value for a more accurate USART
baud rate:
#include <assert.h>
/* Baud rate compensated with factory stored frequency error */
/* Asynchronous communication without Auto-baud (Sync ) */
/* 16MHz Clock, 3V and 600 BAUD */
assert (baud_reg_val >= 0x4A); // Verify legal min BAUD register value with
max neg comp
baud_reg_val *= (1024 + sigrow_val); // sum resolution + error
baud_reg_val /= 1024; // divide by resolution
USART0.BAUD = (int16_t) baud_reg_val; // set adjusted baud rate
Register Key
CLKCTRL.MCLKCTRLB IOREG
CLKCTRL.MCLKLOCK IOREG
CLKCTRL.XOSC32KCTRLA IOREG
CLKCTRL.MCLKCTRLA IOREG
CLKCTRL.OSC20MCTRLA IOREG
CLKCTRL.OSC20MCALIBA IOREG
CLKCTRL.OSC20MCALIBB IOREG
CLKCTRL.OSC32KCTRLA IOREG
Name: MCLKCTRLA
Offset: 0x00
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
CLKOUT CLKSEL[1:0]
Access R/W R/W R/W
Reset 0 0 0
Name: MCLKCTRLB
Offset: 0x01
Reset: 0x11
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
PDIV[3:0] PEN
Access R/W R/W R/W R/W R/W
Reset 1 0 0 0 1
Name: MCLKLOCK
Offset: 0x02
Reset: Based on OSCLOCK in FUSE.OSCCFG
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
LOCKEN
Access R/W
Reset x
Name: MCLKSTATUS
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
EXTS XOSC32KS OSC32KS OSC20MS SOSC
Access R R R R R
Reset 0 0 0 0 0
Name: OSC20MCTRLA
Offset: 0x10
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
RUNSTDBY
Access R/W
Reset 0
Name: OSC20MCALIBA
Offset: 0x11
Reset: Based on FREQSEL in FUSE.OSCCFG
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
CAL20M[6:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset x x x x x x x
Name: OSC20MCALIBB
Offset: 0x12
Reset: Based on FUSE.OSCCFG
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
LOCK TEMPCAL20M[3:0]
Access R R/W R/W R/W R/W
Reset x x x x x
Name: OSC32KCTRLA
Offset: 0x18
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
RUNSTDBY
Access R/W
Reset 0
Name: XOSC32KCTRLA
Offset: 0x1C
Reset: 0x00
Property: Configuration Change Protection
The SEL and CSUT bits cannot be changed as long as the ENABLE bit is set or the XOSC32K Stable bit
(XOSC32KS) in CLKCTRL.MCLKSTATUS is high.
To change settings safely: Write a ‘0’ to the ENABLE bit and wait until XOSC32KS is ‘0’ before re-enabling the
XOSC32K with new settings.
Bit 7 6 5 4 3 2 1 0
CSUT[1:0] SEL RUNSTDBY ENABLE
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 0 – ENABLE Enable
When this bit is written to ‘1’, the configuration of the respective input pins is overridden to TOSC1 and TOSC2. Also,
the Source Select bit (SEL) and Crystal Start-Up Time (CSUT) become read-only.
This bit is I/O protected to prevent any unintentional enabling of the oscillator.
12.1 Features
• Power Management for Adjusting Power Consumption and Functions
• Three Sleep Modes:
– Idle
– Standby
– Power-Down
• Configurable Standby Mode Where Peripherals Can Be Configured as ON or OFF
12.2 Overview
Sleep modes are used to shut down peripherals and clock domains in the device to save power. The Sleep Controller
(SLPCTRL) controls and handles the transitions between Active and sleep modes.
There are four modes available: One Active mode in which software is executed, and three sleep modes. The
available sleep modes are Idle, Standby and Power-Down.
All sleep modes are available and can be entered from the Active mode. In Active mode, the CPU is executing
application code. When the device enters sleep mode, the program execution is stopped. The application code
decides which sleep mode to enter and when.
Interrupts are used to wake the device from sleep. The available interrupt wake-up sources depend on the configured
sleep mode. When an interrupt occurs, the device will wake up and execute the Interrupt Service Routine before
continuing normal program execution from the first instruction after the SLEEP instruction. Any Reset will take the
device out of sleep mode.
The content of the register file, SRAM and registers, is kept during sleep. If a Reset occurs during sleep, the device
will reset, start, and execute from the Reset vector.
Interrupt Request
SLPCTRL CPU
Sleep State
Interrupt Request
Peripheral
12.3.1 Initialization
To put the device into a sleep mode, follow these steps:
1. Configure and enable the interrupts that can wake the device from sleep.
Enable also the global interrupts.
If there are no interrupts enabled when going to sleep, the device cannot wake up again. Only a
WARNING
Reset will allow the device to continue operation.
2. Select which sleep mode to enter, and enable the Sleep Controller by writing to the Sleep Mode (SMODE) bit
field and the Enable (SEN) bit in the Control A (SLPCTRL.CTRLA) register.
The SLEEP instruction must be executed to make the device go to sleep.
12.3.2 Operation
Notes:
1. Set the RUNSTDBY bit of the corresponding peripheral to enter an active state.
2. In Standby sleep mode, only the RTC functionality requires the RUNSTDBY to be set to enter an active state.
In Power-Down sleep mode, only the PIT functionality is available.
3. Sampled mode only.
4. The clock domain depends on the clock source selected for CCL.
Notes:
1. Write the RUNSTDBY bit of the corresponding peripheral to enter an active state.
2. In Standby sleep mode, only the RTC functionality requires the RUNSTDBY to be set to enter an active state.
In Power-Down sleep mode, only the PIT functionality is available.
3. Sampled mode only.
Table 12-3. Sleep Mode Wake-Up Sources
Notes:
1. The I/O pin must be configured according to Asynchronous Sensing Pin Properties in the PORT section.
2. Set the RUNSTDBY bit of the corresponding peripheral to enter an active state.
3. CCL can wake up the device if the path through LUTn is asynchronous (FILTSEL=0x0 and EDGEDET=0x0 in
LUTnCTRLA register).
4. In Standby sleep mode, only the RTC functionality requires the RUNSTDBY to be set to enter an active state.
In Power-Down sleep mode, only the PIT functionality is available.
5. Start-of-Frame interrupt is only available in Standby sleep mode.
6. In Standby sleep mode, only the Start-of-Frame interrupt will trigger Wake-Up from USART.
• In Standby sleep mode, the main clock might be running depending on the peripheral configuration
• In Power-Down sleep mode, only the internal 32.768 kHz oscillator and the Real-Time Clock (RTC) clock source
may be running. These are used by the Brown-out Detector (BOD), Watchdog Timer (WDT) or Periodic Interrupt
Timer (PIT). All the other clock sources will be OFF.
Table 12-4. Sleep Modes and Start-Up Time
The start-up time for the different clock sources is described in the CLKCTRL - Clock Controller section.
In addition to the normal wake-up time, it is possible to make the device wait until the BOD is ready before executing
the code. This is done by writing 0x3 to the BOD operation mode in the Active and Idle (ACTIVE) bit field in the BOD
Configuration (FUSE.BODCFG) fuse. If the BOD is ready before the normal wake-up time, the total wake-up time will
be the same. If the BOD takes longer than the normal wake-up time, the wake-up time will be extended until the BOD
is ready. This ensures correct supply voltage whenever code is executed.
12.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SMODE[1:0] SEN
Access R R R R R R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
13.1 Features
• Returns the Device to an Initial State after a Reset
• Identifies the Previous Reset Source
• Power Supply Reset Sources:
– Power-on Reset (POR)
– Brown-out Detector (BOD) Reset
• User Reset Sources:
– External Reset (RESET)
– Watchdog Timer (WDT) Reset
– Software Reset (SWRST)
– Unified Program and Debug Interface (UPDI) Reset
13.2 Overview
The Reset Controller (RSTCTRL) manages the Reset of the device. It issues a device Reset, sets the device to its
initial state, and allows the Reset source to be identified by software.
VDD POR
Pull-up
resistor BOD UPDI
WDT
All other
peripherals
UPDI
CPU (SW)
13.3.1 Initialization
The RSTCTRL is always enabled, but some of the Reset sources must be enabled individually (either by Fuses or by
software) before they can request a Reset.
After a Reset from any source, the registers in the device with automatic loading from the Fuses or from the
Signature Row are updated.
13.3.2 Operation
tSUT tINIT
INTERNAL
RESET
VBOD+
VDD
VBOD-
DEVICE Active
Running Start-up Initialization Running
STATE Reset
INTERNAL
RESET
tRST tINIT
VDD
VRST+
RESET
VRST-
DEVICE Active
Running Initialization Running
STATE Reset
INTERNAL
RESET
tWDTR tINIT
VDD
WDT
TIME-OUT
DEVICE Active
Running Initialization Running
STATE Reset
INTERNAL
RESET
tSWR tINIT
VDD
SWRST
DEVICE Active
Running Initialization Running
STATE Reset
INTERNAL
RESET
Register Key
RSTCTRL.SWRR IOREG
Name: RSTFR
Offset: 0x00
Reset: 0xXX
Property: -
All flags are cleared by writing a ‘1’ to them. They are also cleared by a Power-on Reset (POR), except for the
Power-on Reset Flag (PORF).
Bit 7 6 5 4 3 2 1 0
UPDIRF SWRF WDRF EXTRF BORF PORF
Access R/W R/W R/W R/W R/W R/W
Reset x x x x x x
Name: SWRR
Offset: 0x01
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
SWRE
Access R/W
Reset 0
14.1 Features
• Short and Predictable Interrupt Response Time
• Separate Interrupt Configuration and Vector Address for Each Interrupt
• Interrupt Prioritizing by Level and Vector Address
• Non-Maskable Interrupts (NMI) for Critical Functions
• Two Interrupt Priority Levels: 0 (Normal) and 1 (High):
– One of the interrupt requests can optionally be assigned as a priority level 1 interrupt
– Optional round robin priority scheme for priority level 0 interrupts
• Interrupt Vectors Optionally Placed in the Application Section or the Boot Loader Section
• Selectable Compact Vector Table (CVT)
14.2 Overview
An interrupt request signals a state change inside a peripheral and can be used to alter the program execution. The
peripherals can have one or more interrupts. All interrupts are individually enabled and configured. When an interrupt
is enabled and configured, it will generate an interrupt request when the interrupt condition occurs.
The CPU Interrupt Controller (CPUINT) handles and prioritizes the interrupt requests. When an interrupt is enabled
and the interrupt condition occurs, the CPUINT will receive the interrupt request. Based on the interrupt’s priority level
and the priority level of any ongoing interrupt, the interrupt request is either acknowledged or kept pending until it
has priority. After returning from the interrupt handler, the program execution continues from where it was before the
interrupt occurred, and any pending interrupts are served after executing one instruction.
The CPUINT offers NMI for critical functions, one selectable high-priority interrupt, and an optional round robin
scheduling scheme for normal-priority interrupts. The round robin scheduling ensures servicing all interrupts within a
certain amount of time.
Interrupt Controller
Priority
Decoder
INT REQ
Peripheral 1
CPU RETI
CPU INT ACK
CPU
CPU INT REQ
INT REQ
Peripheral n
Global
STATUS Interrupt
LVL0PRI Enable Wake-up
LVL1VEC SLPCTRL
CPU.SREG
14.3.1 Initialization
Initialize an interrupt in the following order:
1. Optional: Configure the expected location of the interrupt vectors using the IVSEL bit in the Control A
(CPUINT.CTRLA) register.
2. Optional: Enable compact vector table by writing ‘1’ to the CVT bit in the Control A (CPUINT.CTRLA) register.
3. Optional: Enable vector prioritizing by round robin by writing a ‘1’ to the Round Robin Priority Enable (LVL0RR)
bit in CPUINT.CTRLA.
4. Optional: Select the Priority Level 1 vector by writing the interrupt vector number to the Interrupt Vector with
Priority Level 1 (CPUINT.LVL1VEC) register.
5. Optional: Modify the priority of the LVL0 interrupts by configuring Interrupt Priority Level 0 (LVL0PRI) register.
6. Configure the interrupt conditions within each peripheral and enable the peripheral’s interrupt.
7. Enable interrupts globally by writing a ‘1’ to the Global Interrupt Enable (I) bit in the CPU Status (CPU.SREG)
register.
14.3.2 Operation
After the Program Counter is pushed on the stack, the program vector for the interrupt is executed. See the following
figure.
Program Counter
"Instruction" (1)
INT REQ
INT ACK
If an interrupt occurs during the execution of a multi-cycle instruction, the instruction is completed before the interrupt
is served, as shown in the following figure.
Figure 14-3. Interrupt Execution of Multi-Cycle Instruction
Clock
Program Counter
"Instruction" (1)
INT REQ
INT ACK
If an interrupt occurs when the device is in a sleep mode, the interrupt execution response time is increased by five
clock cycles, as shown in the figure below. Also, the response time is increased by the start-up time from the selected
sleep mode.
Figure 14-4. Interrupt Execution From Sleep
Clock
Program Counter
"Instruction" (1)
INT REQ
INT ACK
A return from an interrupt handling routine takes four to five clock cycles, depending on the size of the Program
Counter. During these clock cycles, the Program Counter is popped from the stack, and the Stack Pointer is
incremented.
Note:
1. Devices with 8 KB of Flash or less use RJMP instead of JMP, which takes only two clock cycles.
Static Scheduling
If several level 0 interrupt requests are pending at the same time, the one with the highest priority is scheduled for
execution first. The following figure illustrates the default configuration, where the interrupt vector with the lowest
address has the highest priority.
Figure 14-5. Default Static Scheduling
Lowest Address IVEC 0 Highest Priority
IVEC 1
:
:
:
:
:
:
Here, value Y has been written to CPUINT.LVL0PRI so that the interrupt vector Y+1 has the highest priority. Note
that, In this case, the priorities will wrap so that the lowest address no longer has the highest priority, not including
RESET and NMI, which will always have the highest priority.
Refer to the interrupt vector mapping of the device for available interrupt requests and their interrupt vector number.
: :
: :
: :
IVEC n IVEC n
The round robin scheduling for LVL0 interrupt requests is enabled by writing a ‘1’ to the Round Robin Priority Enable
(LVL0RR) bit in the Control A (CPUINT.CTRLA) register.
Register Key
The IVSEL and CVT bit fields in CPUINT.CTRLA IOREG
14.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
IVSEL CVT LVL0RR
Access R/W R/W R/W
Reset 0 0 0
Note:
1. A system reset will cause the Program Counter to be reset to 0x0000, regardless of the IVSEL bit value.
14.5.2 Status
Name: STATUS
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
NMIEX LVL1EX LVL0EX
Access R R R
Reset 0 0 0
Name: LVL0PRI
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
LVL0PRI[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: LVL1VEC
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
LVL1VEC[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
15.1 Features
• System for Direct Peripheral-to-Peripheral Signaling
• Peripherals Can Directly Produce, Use, and React to Peripheral Events
• Short and Predictable Response Time
• Up to 6 Parallel Event Channels Available
• Each Channel Is Driven by One Event Generator and Can Have Multiple Event Users
• Events Can Be Sent and/or Received by Most Peripherals and by Software
• The Event System Works in Active, Idle, and Standby Sleep Modes
15.2 Overview
The Event System (EVSYS) enables direct peripheral-to-peripheral signaling. It allows a change in one peripheral
(the event generator) to trigger actions in other peripherals (the event users) through event channels, without
using the CPU. It is designed to provide a short and predictable response time between peripherals, allowing for
autonomous peripheral control and interaction, and for synchronized timing of actions in several peripheral modules.
Thus, the EVSYS peripheral makes it possible to implement Core Independent Peripherals (CIPs). Also, it is a
powerful tool for reducing the complexity, size, and execution time of the software.
A change of the event generator’s state is referred to as an event and usually corresponds to one of the peripheral’s
interrupt conditions. Events can be forwarded directly to other peripherals using the dedicated event routing network.
The routing of each channel is configured in software, including event generation and use.
Only one event signal can be routed on each channel. Multiple peripherals can use events from the same channel.
The EVSYS can connect peripherals such as ADCs, analog comparators, I/O PORT pins, the real-time counter,
timer/counters, and the configurable custom logic peripheral. Events can also be generated from software.
Event Channel n
SWEVENTx[n] To Channel
MUX for Async
Event User
From Event
.
Generators .
.
0 To Channel
D QD Q 1 MUX for Sync
CLK_PER Event User
Is
CHANNELn Async? EVOUTx pin
The block diagram shows the operation of an event channel. A multiplexer controlled by Channel n Generator
Selection (EVSYS.CHANNELn) register at the input selects which of the event sources to route onto the event
channel. Each event channel has two subchannels: one asynchronous and one synchronous. A synchronous user
will listen to the synchronous subchannel, and an asynchronous user will listen to the asynchronous subchannel.
An event signal from an asynchronous source will be synchronized by the Event System before being routed to the
synchronous subchannel. An asynchronous event signal to be used by a synchronous consumer must last for at least
one peripheral clock cycle to ensure that it will propagate through the synchronizer. The synchronizer will delay such
an event between two and three clock cycles, depending on when the event occurs.
Figure 15-2. Example of Event Source, Generator, User, and Action
Event Generator Event User
Timer/Counter ADC
Compare Match
Channel Sweep
Event
Over/Underflow
| Routing
Single
Network Conversion
Error
15.3.1 Initialization
To utilize events, the Event System, the generating peripheral, and the peripheral(s) using the event must be set up
accordingly:
1. Configure the generating peripheral appropriately. For example, if the generating peripheral is a timer, set the
prescaling, the Compare register, etc., so that the desired event is generated.
2. Configure the event user peripheral(s) appropriately. For example, if the ADC is the event user, set the ADC
prescaler, resolution, conversion time, etc., as desired, and configure the ADC conversion to start at the
reception of an event.
3. Configure the Event System to route the desired source. In this case, the Timer/Compare match to the desired
event channel. This may, for example, be Channel 0, which is accomplished by writing to the Channel 0
Generator Selection (EVSYS.CHANNEL0) register.
4. Configure the ADC to listen to this channel by writing to the corresponding User x Channel MUX
(EVSYS.USERx) register.
15.3.2 Operation
The properties of both the generated event and the intended event user must be considered in order to ensure
reliable and predictable operation.
The table below shows the available event generators for this device family.
...........continued
Generator Name Description Event Generating Length of Event
Type Clock Domain
Peripheral Event
RTC OVF Overflow Pulse CLK_RTC One CLK_RTC period
CMP Compare Match
PIT_DIV8192 Prescaled RTC clock Level Given by prescaled RTC
divided by 8192 clock divided by 8192
PIT_DIV4096 Prescaled RTC clock Given by prescaled RTC
divided by 4096 clock divided by 4096
PIT_DIV2048 Prescaled RTC clock Given by prescaled RTC
divided by 2048 clock divided by 2048
PIT_DIV1024 Prescaled RTC clock Given by prescaled RTC
divided by 1024 clock divided by 1024
PIT_DIV512 Prescaled RTC clock Given by prescaled RTC
divided by 512 clock divided by 512
PIT_DIV256 Prescaled RTC clock Given by prescaled RTC
divided by 256 clock divided by 256
PIT_DIV128 Prescaled RTC clock Given by prescaled RTC
divided by 128 clock divided by 128
PIT_DIV64 Prescaled RTC clock Given by prescaled RTC
divided by 64 clock divided by 64
CCL LUTn LUT output level Level Asynchronous Depends on CCL
configuration
ACn OUT Comparator output level Level Asynchronous Given by AC output level
ADCn RES Result ready Pulse CLK_PER One CLK_PER period
SAMP Sample ready
WCMP Window compare match
PORTx PINn Pin level Level Asynchronous Given by pin level
USARTn XCK USART Baud clock Level CLK_PER Minimum two CLK_PER
periods
SPIn SCK SPI Host clock Level CLK_PER Minimum two CLK_PER
periods
...........continued
Generator Name Description Event Generating Length of Event
Type Clock Domain
Peripheral Event
TCAn OVF_LUNF Normal mode: Overflow Pulse CLK_PER One CLK_PER period
Split mode: Low Byte
Timer underflow
TCBn CAPT CAPT flag set Pulse CLK_PER One CLK_PER period
OVF OVF flag set
...........continued
Input Detection Async/Sync Description
Level Sync An event user is triggered by an event level and requires that the
incoming event is generated from CLK_PER
Async An event user is triggered by an event level and has
asynchronous detection or an internal synchronizer
No detection Async An event user will use the event signal directly
The table below shows the available event users for this device family.
15.3.2.5 Synchronization
Events can be either synchronous or asynchronous to the peripheral clock. Each Event System channel has two
subchannels: one asynchronous and one synchronous.
The asynchronous subchannel is identical to the event output from the generator. If the event generator generates a
signal asynchronous to the peripheral clock, the signal on the asynchronous subchannel will be asynchronous. If the
event generator generates a signal synchronous to the peripheral clock, the signal on the asynchronous subchannel
will also be synchronous.
The synchronous subchannel is identical to the event output from the generator, if the event generator generates a
signal synchronous to the peripheral clock. If the event generator generates a signal asynchronous to the peripheral
clock, this signal is first synchronized before being routed onto the synchronous subchannel. Depending on when it
occurs, synchronization will delay the event by two to three clock cycles. The Event System automatically performs
this synchronization if an asynchronous generator is selected for an event channel.
Name: SWEVENTx
Offset: 0x00
Reset: 0x00
Property: -
Write bits in this register to create a software event on the corresponding event channels.
Bits 0-7 in the EVSYS.SWEVENTA register correspond to event channels 0-7. If the number of available event
channels is between eight and 15, these are available in the EVSYS.SWEVENTB register, where bit n corresponds to
event channel 8+n.
Refer to the Peripheral Overview section for the available number of Event System channels.
Bit 7 6 5 4 3 2 1 0
SWEVENTx[7:0]
Access W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Name: CHANNELn
Offset: 0x10 + n*0x01 [n=0..5]
Reset: 0x00
Property: -
Each channel can be connected to one event generator. Not all generators can be connected to all channels. Refer
to the table below to see which generator sources can be routed onto each channel and the generator value to
be written to EVSYS.CHANNELn to achieve this routing. Writing the value 0x00 to EVSYS.CHANNELn turns the
channel off.
Refer to the Peripheral Overview section for the available number of Event System channels.
Bit 7 6 5 4 3 2 1 0
CHANNELn[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
...........continued
GENERATOR Async/ Description Channel Availability
Sync
Value Name
Peripheral Output
0x40-0x47 PORTA PIN0-PIN7 Async PORTA PIN0-PIN7 level(2) CHANNEL0 and
CHANNEL1 only
0x48-0x4F CHANNEL2 and
CHANNEL3 only
0x40-0x47 PORTB PIN0-PIN7 Async PORTB PIN0-PIN7 level(2) CHANNEL4 and
CHANNEL5 only
0x48-0x4F CHANNEL0 and
CHANNEL1 only
0x40-0x47 PORTC (1) PIN0-PIN7 Async PORTC PIN0-PIN7 level (2) CHANNEL2 and
CHANNEL 3 only
0x48-0x4F CHANNEL4 and
CHANNEL5 only
0x60 USART0 XCK Sync Clock signal in SPI Host mode All channels
0x61 USART1 XCK and synchronous USART Host
mode
0x68 SPI0 SCK Sync SPI host clock signal All channels
0x80 TCA0 OVF_LUNF Sync Normal mode: Overflow All channels
Split mode: Low byte timer
underflow
0x81 HUNF Sync Normal mode: Not available
Split mode: High byte timer
underflow
0x84 CMP0_LCMP0 Sync Normal mode: Compare Channel
0 match
Split mode: Low byte timer
Compare Channel 0 match
0x85 CMP1_LCMP1 Sync Normal mode: Compare Channel
1 match
Split mode: Low byte timer
Compare Channel 1 match
0x86 CMP2_LCMP2 Sync Normal mode: Compare Channel
2 match
Split mode: Low byte timer
Compare Channel 2 match
0xA0 TCB0 CAPT Sync CAPT flag set(3) All channels
0xA1 OVF OVF flag set
0xA2 TCB1 CAPT Sync CAPT flag set(3) All channels
0xA3 OVF OVF flag set
Notes:
1. Not all peripheral instances are available for all pin counts. Refer to the Peripherals and Architecture section
for details.
2. An event from the PORT pin will be zero if the input driver is disabled.
3. The operational mode of the timer decides when raising the CAPT flag. Refer to the TCB section for details.
Name: USER
Offset: 0x20 + n*0x01 [n=0..19]
Reset: 0x00
Property: -
Each event user can be connected to one channel and several users can be connected to the same channel.
The following table lists all Event System users with their corresponding user ID number and name. The
user name is given by combining USER with Peripheral and Input from the table below in the following way:
USERPERIPHERALINPUT.
Notes:
1. Not all peripheral instances are available for all pin counts. Refer to the Peripherals and Architecture section
for details.
2. Depends on the timer operational mode.
Bit 7 6 5 4 3 2 1 0
USER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
16.1 Overview
The Port Multiplexer (PORTMUX) can either enable or disable the functionality of the pins, or change between default
and alternative pin positions. Available options are described in detail in the PORTMUX register map and depend on
the actual pin and its properties.
For available pins and functionalities, refer to the I/O Multiplexing and Considerations section.
Name: EVSYSROUTEA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
EVOUTB EVOUTA
Access R/W R/W
Reset 0 0
Name: CCLROUTEA
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
LUT3 LUT2 LUT1 LUT0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: USARTROUTEA
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
USART1[1:0] USART0[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: SPIROUTEA
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SPI0[1:0]
Access R/W R/W
Reset 0 0
Name: TCAROUTEA
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
TCA05 TCA04 TCA03 TCA02 TCA01 TCA00
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: TCBROUTEA
Offset: 0x05
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
TCB1 TCB0
Access R/W R/W
Reset 0 0
17.1 Features
• General Purpose Input and Output Pins with Individual Configuration:
– Pull-up
– Inverted I/O
• Interrupts and Events:
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
• Optional Slew Rate Control per I/O Port
• Asynchronous Pin Change Sensing that Can Wake the Device From all Sleep Modes
• Efficient and Safe Access to Port Pins
– Hardware Read-Modify-Write (RMW) through dedicated toggle/clear/set registers
– Mapping of often-used PORT registers into bit-accessible I/O memory space (virtual ports)
17.2 Overview
The I/O pins of the device are controlled by instances of the PORT peripheral registers. Each PORT instance
has up to eight I/O pins. The PORTs are named PORTA, PORTB, PORTC, etc. Refer to the I/O Multiplexing and
Considerations section to see which pins are controlled by what instance of PORT. The base addresses of the PORT
instances and the corresponding Virtual PORT instances are listed in the Peripherals and Architecture section.
Each PORT pin has a corresponding bit in the Data Direction (PORTx.DIR) and Data Output Value (PORTx.OUT)
registers to enable that pin as an output and to define the output state. For example, pin PA3 is controlled by DIR[3]
and OUT[3] of the PORTA instance.
The input value of a PORT pin is synchronized to the Peripheral Clock (CLK_PER) and then made accessible as the
data input value (PORTx.IN). The value of the pin can be read whether the pin is configured as input or output.
The PORT also supports asynchronous input sensing with interrupts and events for selectable pin change conditions.
Asynchronous pin change sensing means that a pin change can trigger an interrupt and wake the device from sleep,
including sleep modes where CLK_PER is stopped.
All pin functions are individually configurable per pin. The pins have hardware Read-Modify-Write functionality for a
safe and correct change of the drive values and/or input and sense configuration.
The PORT pin configuration controls input and output selection of other device functions.
Pull-up Enable
DIRn
D Q
Peripheral Override
R
OUTn
D Q
Pxn
Peripheral Override
R
Invert Enable
Synchronizer
INn
Synchronous
Q D Q D
Input
R R
Sense Configuration
Interrupt
Interrupt
Generator
Asynchronous
Input/Event
Input Disable
Peripheral Override
Analog
Input/Output
17.3.1 Initialization
After Reset, all outputs are tri-stated, and digital input buffers enabled even if there is no clock running.
The following steps are all optional when initializing PORT operation:
• Enable or disable the output driver for pin Pxn by respectively writing ‘1’ to bit n in the PORTx.DIRSET or
PORTx.DIRCLR register
• Set the output driver for pin Pxn to high or low level respectively by writing ‘1’ to bit n in the PORTx.OUTSET or
PORTx.OUTCLR register
• Read the input of pin Pxn by reading bit n in the PORTx.IN register
• Configure the individual pin configurations and interrupt control for pin Pxn in PORTx.PINnCTRL
Important: For lowest power consumption, disable the digital input buffer of unused pins and pins that
are used as analog inputs or outputs.
Specific pins, such as those used to connect a debugger, may be configured differently, as required by their special
function.
17.3.2 Operation
The input pull-up of pin n is enabled by writing a ‘1’ to the Pull-up Enable (PULLUPEN) bit in PORTx.PINnCTRL. The
pull-up is disconnected when the pin is configured as an output, even if PULLUPEN is ‘1’.
Pin interrupts can be enabled for pin n by writing to the Input/Sense Configuration (ISC) bit field in
PORTx.PINnCTRL. Refer to 17.3.3. Interrupts for further details.
The digital input buffer for pin n can be disabled by writing the INPUT_DISABLE setting to ISC. This can reduce
power consumption and may reduce noise if the pin is used as analog input. While configured to INPUT_DISABLE,
bit n in PORTx.IN will not change since the input synchronizer is disabled.
17.3.3 Interrupts
Table 17-2. Available Interrupt Vectors and Sources
Each PORT pin n can be configured as an interrupt source. Each interrupt can be individually enabled or disabled by
writing to ISC in PORTx.PINnCTRL.
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of the
peripheral (peripheral.INTFLAGS).
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGS register for
details on how to clear interrupt flags.
When setting or changing interrupt settings, take these points into account:
• If an Inverted I/O Enable (INVEN) bit is toggled in the same cycle as ISC is changed, the edge caused by the
inversion toggling may not cause an interrupt request
• If an input is disabled by writing to ISC while synchronizing an interrupt, that interrupt may be requested on
re-enabling the input, even if it is re-enabled with a different interrupt setting
• If the interrupt setting is changed by writing to ISC while synchronizing an interrupt, that interrupt may not be
requested
Note:
1. If a partially asynchronous input pin is used for wake-up from sleep with CLK_PER stopped, the required level
must be held long enough for the MCU to complete the wake-up to trigger the interrupt. If the level disappears,
the MCU can wake up without any interrupt generated.
17.3.4 Events
PORT can generate the following events:
Table 17-4. Event Generators in PORTx
Generator Name
Description Event Type Generating Clock Domain Length of Event
Peripheral Event
PORTx PINn Pin level Level Asynchronous Given by pin level
All PORT pins are asynchronous event system generators. PORT has as many event generators as there are PORT
pins in the device. Each event system output from PORT is the value present on the corresponding pin if the digital
input buffer is enabled. If a pin input buffer is disabled, the corresponding event system output is zero.
PORT has no event inputs. Refer to the Event System (EVSYS) section for more details regarding event types and
Event System configuration.
Important: The PORTs will always use the Peripheral Clock (CLK_PER). Input synchronization will halt
when this clock stops.
Name: DIR
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DIR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DIRSET
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DIRSET[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DIRCLR
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DIRCLR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DIRTGL
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DIRTGL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: OUT
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
OUT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: OUTSET
Offset: 0x05
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
OUTSET[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: OUTCLR
Offset: 0x06
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
OUTCLR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: OUTTGL
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
OUTTGL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: IN
Offset: 0x08
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
IN[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTFLAGS
Offset: 0x09
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
INT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: PORTCTRL
Offset: 0x0A
Reset: 0x00
Property: -
This register contains the slew rate limit enable bit for this port.
Bit 7 6 5 4 3 2 1 0
SRL
Access R/W
Reset 0
Name: PINnCTRL
Offset: 0x10 + n*0x01 [n=0..7]
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
INVEN PULLUPEN ISC[2:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Note:
1. If the digital input buffer for pin n is disabled, bit n in the Input Value (PORTx.IN) register will not be updated.
Name: DIR
Offset: 0x00
Reset: 0x00
Property: -
Access to the Virtual PORT registers has the same outcome as access to the regular registers but allows for memory
specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space
where the regular PORT registers reside.
Bit 7 6 5 4 3 2 1 0
DIR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: OUT
Offset: 0x01
Reset: 0x00
Property: -
Access to the Virtual PORT registers has the same outcome as access to the regular registers but allows for memory
specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space
where the regular PORT registers reside.
Bit 7 6 5 4 3 2 1 0
OUT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: IN
Offset: 0x02
Reset: 0x00
Property: -
Access to the Virtual PORT registers has the same outcome as access to the regular registers but allows for memory
specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space
where the regular PORT registers reside.
Bit 7 6 5 4 3 2 1 0
IN[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTFLAGS
Offset: 0x03
Reset: 0x00
Property: -
Access to the Virtual PORT registers has the same outcome as access to the regular registers but allows for memory
specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space
where the regular PORT registers reside.
Bit 7 6 5 4 3 2 1 0
INT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
18.1 Features
• Brown-out Detector Monitors the Power Supply to Avoid Operation Below a Programmable Level
• Three Available Modes:
– Enabled mode (continuously active)
– Sampled mode
– Disabled
• Separate Selection of Mode for Active and Sleep Modes
• Voltage Level Monitor (VLM) with Interrupt
• Programmable VLM Level Relative to the BOD Level
18.2 Overview
The Brown-out Detector (BOD) monitors the power supply and compares the supply voltage with the programmable
brown-out threshold level. The brown-out threshold level defines when to generate a System Reset. The Voltage
Level Monitor (VLM) monitors the power supply and compares it to a threshold higher than the BOD threshold. The
VLM can then generate an interrupt as an “early warning” when the supply voltage is approaching the BOD threshold.
The VLM threshold level is expressed as a percentage above the BOD threshold level.
The BOD is controlled mainly by fuses and has to be enabled by the user. The mode used in Standby sleep mode
and Power-Down sleep mode can be altered in normal program execution. The VLM is controlled by I/O registers as
well.
When activated, the BOD can operate in Enabled mode, where the BOD is continuously active, or in Sampled mode,
where the BOD is activated briefly at a given period to check the supply voltage level.
VDD
BOD
+
BOD
Reset
BOD Threshold -
VLM
+
VLM
Interrupt
VLM Threshold -
18.3.1 Initialization
The BOD settings are loaded from fuses during Reset. The BOD level and operating mode in Active and Idle sleep
mode are set by fuses and cannot be changed by software. The operating mode in Standby and Power-Down sleep
mode is loaded from fuses and can be changed by software.
The Voltage Level Monitor function can be enabled by writing a ‘1’ to the VLM Interrupt Enable (VLMIE) bit in
the Interrupt Control (BOD.INTCTRL) register. The VLM interrupt is configured by writing the VLM Configuration
(VLMCFG) bits in BOD.INTCTRL. An interrupt is requested when the supply voltage crosses the VLM threshold
either from above, below, or any direction.
The VLM functionality will follow the BOD mode. If the BOD is disabled, the VLM will not be enabled, even if the
VLMIE is ‘1’. If the BOD is using Sampled mode, the VLM will also be sampled. When the VLM interrupt is enabled,
the interrupt flag will be set according to VLMCFG when the voltage level is crossing the VLM level.
The VLM threshold is defined by writing the VLM Level (VLMLVL) bits in the Control A (BOD.VLMCTRLA) register.
18.3.2 Interrupts
Table 18-1. Available Interrupt Vectors and Sources
The VLM interrupt will not be executed if the CPU is halted in Debug mode.
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
Register Key
SLEEP in BOD.CTRLA IOREG
18.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: Loaded from fuse
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
SAMPFREQ ACTIVE[1:0] SLEEP[1:0]
Access R R R R/W R/W
Reset x x x x x
18.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: Loaded from fuse
Property: -
Bit 7 6 5 4 3 2 1 0
LVL[2:0]
Access R R R R R R R R
Reset 0 0 0 0 0 x x x
Notes:
• Refer to the BOD and POR Characteristics in Electrical Characteristics for further details
• Values in the description are typical values
Name: VLMCTRLA
Offset: 0x08
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
VLMLVL[1:0]
Access R/W R/W
Reset 0 0
Name: INTCTRL
Offset: 0x09
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
VLMCFG[1:0] VLMIE
Access R/W R/W R/W
Reset 0 0 0
Name: INTFLAGS
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
VLMIF
Access R/W
Reset 0
Name: STATUS
Offset: 0x0B
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
VLMS
Access R
Reset 0
19.1 Features
• Programmable Voltage Reference Source for:
– AC
– ADC
• Each Reference Source Supports the Following Voltages:
– 1.024V
– 2.048V
– 2.500V
– 4.096V
– VDD
19.2 Overview
The Voltage Reference (VREF) peripheral provides voltage reference sources used by several peripherals. The user
can select the reference voltages for the Analog Comparators by writing to the appropriate bit field in the Control A
(VREF.CTRLA) register.
A voltage reference source is enabled automatically when requested by a peripheral. The user can enable the
reference voltage sources (and thus, override the automatic disabling of unused sources) by writing to the respective
ALWAYSON bit in the Control B (VREF.CTRLB) register. This will decrease the start-up time at the cost of increased
power consumption.
Reference reque st
Reference enable
Reference se lect
1.024V
Bandgap 2.056V Inte rnal
Reference 2.500V BUF Reference
Gen erator 4.096V
Ban dgap VDD
ena ble
19.3.1 Initialization
The default configuration will enable the respective source when the ADC0 or the AC0 are requesting a reference
voltage.
The voltage references for the ADC0 and AC0 can be forced ON by writing a ‘1’ to the respective Reference Force
Enable bits (ADC0REFEN and AC0REFEN) in the Control B (VREF.CTRLB) register. This serves to reduce the
start-up time of the respective peripheral.
The default reference voltage for the AC0 is 1.024V but can be configured by writing to the AC0 Reference Select
(AC0REFSEL) bit field in the Control A (VREF.CTRLA) register.
The reference voltage for the ADC0 is configured by selecting the reference source within the ADC0 registers. Refer
to the ADC documentation for details.
19.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
AC0REFSEL[2:0]
Access R/W R/W R/W
Reset 0 0 0
19.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
NVMREFEN ADC0REFEN AC0REFEN
Access R/W R/W R/W
Reset 0 0 0
20.1 Features
• Issues a System Reset if the Watchdog Timer Is Not Cleared Before Its Time-Out Period
• Operates Asynchronously from the Peripheral Clock Using an Independent Oscillator
• Uses the 1.024 kHz Output of the 32.768 kHz Ultra-Low Power Oscillator (OSCULP32K)
• 11 Selectable Time-Out Periods, from 8 ms to 8s
• Two Operation Modes:
– Normal mode
– Window mode
• Configuration Lock to Prevent Unwanted Changes
20.2 Overview
The Watchdog Timer (WDT) is a system function for monitoring the correct program operation. When enabled, the
WDT is a constantly running timer with a configurable time-out period. If the WDT is not reset within the time-out
period, it will issue a system Reset. This allows the system to recover from situations such as runaway or deadlocked
code. The WDT is reset by executing the WDR (Watchdog Timer Reset) instruction from software.
In addition to the Normal mode as described above, the WDT has a Window mode. The Window mode defines a
time slot or “window” inside the time-out period during which the WDT must be reset. If the WDT is reset outside this
window, either too early or too late, a system Reset will be issued. Compared to the Normal mode, the Window mode
can catch situations where a code error causes constant WDR execution.
When enabled, the WDT will run in Active mode and all sleep modes. Since it is asynchronous (that is running from
a CPU independent clock source), it will continue to operate and be able to issue a system Reset, even if the main
clock fails.
The WDT has a Configuration Change Protection (CCP) mechanism and a lock functionality, ensuring the WDT
settings cannot be changed by accident.
CTRLA Closed
window
PERIOD + > System
Reset
CLK_WDT Time-out
COUNT =
WDR
(Instruction)
20.3.1 Initialization
1. The WDT is enabled when a non-zero value is written to the Period (PERIOD) bit field in the Control A
(WDT.CTRLA) register.
2. Optional: Write a non-zero value to the Window (WINDOW) bit field in WDT.CTRLA to enable the Window
mode operation.
All bits in the Control A register and the Lock (LOCK) bit in the Status (WDT.STATUS) register are write-protected by
the Configuration Change Protection (CCP) mechanism.
A fuse (FUSE.WDTCFG) defines the Reset value of the WDT.CTRLA register. If the value of the PERIOD bit field in
the FUSE.WDTCFG fuse is different than zero, the WDT is enabled and the LOCK bit in the WDT.STATUS register is
set at boot time.
20.3.2 Clocks
A 1.024 kHz oscillator clock (CLK_WDT_OSC) is sourced from the internal Ultra-Low Power Oscillator, OSCULP32K.
Due to the ultra-low power design, the oscillator is less accurate than other oscillators featured in the device, and
hence the exact time-out period may vary from device to device. This variation must be taken into consideration when
designing software that uses the WDT to ensure that the time-out periods used are valid for all devices. Refer to the
“Electrical Characteristics” section for more specific information.
The counter clock (CLK_WDT_OSC) is asynchronous to the peripheral clock. Due to this asynchronicity, writing to
the WDT Control register will require synchronization between the clock domains. Refer to 20.3.6. Synchronization
for further details.
20.3.3 Operation
WDT Time-out
System Reset
Here: 5 10 15 20 25 30 35 t [ms]
TO WDT ~ 16 ms TOWDT
Normal mode is enabled as long as the Window (WINDOW) bit field in the WDT.CTRLA register is 0x0.
• The closed window time-out period (TOWDTW) defines a duration, from 8 ms to 8s, where the WDT cannot be
reset. If the WDT is reset during this period, the WDT will issue a system Reset.
• The open window time-out period (TOWDT), which is also 8 ms to 8s, defines the duration of the open period
during which the WDT can (and needs to) be reset. The open period will always follow the closed period, so the
total duration of the time-out period is the sum of the closed window and the open window time-out periods.
When enabling the Window mode or when going out of the Debug mode, the window is activated after the first WDR
instruction.
The figure below shows a typical timing scheme for the WDT operating in Window mode.
Figure 20-3. Window Mode Operation
WDT Count
Timely WDT Reset (WDR)
Open
Here: 5 10 15 20 25 30 35 t [ms]
TOWDTW = TOWDT = 8 ms TOWDTW TOWDT
The Window mode is enabled by writing a non-zero value to the Window (WINDOW) bit field in the Control A
(WDT.CTRLA) register. The Window mode is disabled by writing the WINDOW bit field to ‘0x0’.
20.3.6 Synchronization
The Control A (WDT.CTRLA) register is synchronized when written, due to the asynchronicity between the WDT
clock domain and the peripheral clock domain. The Synchronization Busy (SYNCBUSY) flag in the STATUS
(WDT.STATUS) register indicates if there is an ongoing synchronization.
Writing to WDT.CTRLA while SYNCBUSY = 1 is not allowed.
Register Key
WDT.CTRLA IOREG
LOCK bit in WDT.STATUS IOREG
20.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: From FUSE.WDTCFG
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
WINDOW[3:0] PERIOD[3:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset x x x x x x x x
Note: Refer to the Electrical Characteristics section for specific information regarding the accuracy of the 32.768
kHz Ultra-Low Power Oscillator (OSCULP32K).
Note: Refer to the Electrical Characteristics section for specific information regarding the accuracy of the 32.768
kHz Ultra-Low Power Oscillator (OSCULP32K).
20.5.2 Status
Name: STATUS
Offset: 0x01
Reset: 0x00
Property: Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
LOCK SYNCBUSY
Access R/W R
Reset 0 0
Bit 7 – LOCK Lock
Writing this bit to ‘1’ write-protects the WDT.CTRLA register.
It is only possible to write this bit to ‘1’. This bit can be cleared in Debug mode only.
If the PERIOD bits in WDT.CTRLA are different from zero after boot code, the lock will automatically be set.
This bit is under CCP.
21.1 Features
• 16-Bit Timer/Counter
• Three Compare Channels
• Double-Buffered Timer Period Setting
• Double-Buffered Compare Channels
• Waveform Generation:
– Frequency generation
– Single-slope PWM (Pulse-Width Modulation)
– Dual-slope PWM
• Count on Event
• Timer Overflow Interrupts/Events
• One Compare Match per Compare Channel
• Two 8-Bit Timer/Counters in Split Mode
21.2 Overview
The flexible 16-bit PWM Timer/Counter type A (TCA) provides accurate program execution timing, frequency and
waveform generation, and command execution.
A TCA consists of a base counter and a set of compare channels. The base counter can be used to count clock
cycles or events or let events control how it counts clock cycles. It has direction control and period setting that can
be used for timing. The compare channels can be used together with the base counter to perform a compare match
control, frequency generation, and pulse-width waveform modulation.
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each timer/
counter clock or event input.
A timer/counter can be clocked and timed from the peripheral clock, with optional prescaling, or from the Event
System. The Event System can also be used for direction control or to synchronize operations.
By default, the TCA is a 16-bit timer/counter. The timer/counter has a Split mode feature that splits it into two 8-bit
timer/counters with three compare channels each.
A block diagram of the 16-bit timer/counter with closely related peripheral modules (in grey) is shown in the figure
below.
Timer/Counter
Base Counter Prescaler
CLK_PER
Timer Period
Control Logic
Counter Event
System
Compare Channel 0
Compare Channel 1
PORTS
Compare Channel 2
Comparator
Waveform
Buffer Generation
Base Counter
Clock Select
CTRL A
BV PERBUF
Mode
CTRL B
Event
PER Action
EVCTRL
‘‘count’’
Counter OVF
‘‘clear’’
(INT Req. and Event)
‘‘load’’
CNT Control Logic
‘‘direction’’
Event
TOP
UPDATE
=
BOTTOM
=0
Compare Unit n
CMPn
Waveform
Generation
WOn Out
‘‘match’’ CMPn
= (INT Req. and Event)
The Counter (TCAn.CNT) register, Period and Compare (TCAn.PER and TCAn.CMPn) registers, and their
corresponding buffer registers (TCAn.PERBUF and TCAn.CMPnBUF) are 16-bit registers. All buffer registers have a
Buffer Valid (BV) flag that indicates when the buffer contains a new value.
During normal operation, the counter value is continuously compared to zero and the period (PER) value to
determine whether the counter has reached TOP or BOTTOM. The counter value can also be compared to the
TCAn.CMPn registers.
The timer/counter can generate interrupt requests, events, or change the waveform output after being triggered by
the Counter (TCAn.CNT) register reaching TOP, BOTTOM, or CMPn. The interrupt requests, events, or waveform
output changes will occur on the next CLK_TCA cycle after the triggering.
CLK_TCA is either the prescaled peripheral clock or events from the Event System, as shown in the figure below.
Figure 21-3. Timer/Counter Clock Logic
CLK_TCA
CNT
‘‘Count
CLK_PER Prescaler
Enable’’
Event
CLKSEL
Logic ‘‘Count
Direction’’
Event
DIR
EVACT
CNTxEI
21.3.1 Definitions
The following definitions are used throughout the documentation:
Table 21-1. Timer/Counter Definitions
Name Description
BOTTOM The counter reaches BOTTOM when it becomes 0x0000
MAX The counter reaches MAXimum when it becomes all ones
TOP The counter reaches TOP when it becomes equal to the highest value in the count sequence
The update condition is met when the timer/counter reaches BOTTOM or TOP, depending on the
UPDATE Waveform Generator mode. Buffered registers with valid buffer values will be updated unless the Lock
Update (LUPD) bit in the TCAn.CTRLE register has been set.
CNT Counter register value
CMP Compare register value
PER Period register value
In general, the term timer is used when the timer/counter is counting periodic clock ticks. The term counter is used
when the input signal has sporadic or irregular ticks. The latter can be the case when counting events.
21.3.2 Initialization
To start using the timer/counter in a basic mode, follow these steps:
1. Write a TOP value to the Period (TCAn.PER) register.
2. Enable the peripheral by writing a ‘1’ to the Enable (ENABLE) bit in the Control A (TCAn.CTRLA) register.
The counter will start counting clock ticks according to the prescaler setting in the Clock Select (CLKSEL) bit
field in TCAn.CTRLA.
3. Optional: By writing a ‘1’ to the Enable Counter Event Input A (CNTAEI) bit in the Event Control
(TCAn.EVCTRL) register, events are counted instead of clock ticks.
4. The counter value can be read from the Counter (CNT) bit field in the Counter (TCAn.CNT) register.
21.3.3 Operation
MAX
‘‘update’’
TOP
CNT
BOTTOM
DIR
It is possible to change the counter value in the Counter (TCAn.CNT) register when the counter is running. The write
access to TCAn.CNT register has higher priority than count, clear or reload, and will be immediate. The direction
of the counter can also be changed during normal operation by writing to the Direction (DIR) bit in the Control E
(TCAn.CTRLE) register.
BV EN CMPnBUF
EN CMPn
UPDATE
CNT
‘‘match’’
=
Both the TCAn.CMPn and TCAn.CMPnBUF registers are available as I/O registers. This allows the initialization and
bypassing of the buffer register and the double-buffering function.
BOTTOM
New TOP written to New TOP written to
PER that is higher PER that is lower
than current CNT. than current CNT.
A counter wrap-around can occur in any mode of operation when counting up without buffering, as the TCAn.CNT
and TCAn.PER registers are continuously compared. If a new TOP value is written to TCAn.PER that is lower than
the current TCAn.CNT, the counter will wrap first, before a compare match occurs.
Figure 21-7. Unbuffered Dual-Slope Operation
Counter wrap-around
MAX
‘‘update’’
‘‘write’’
CNT
BOTTOM
With Buffering: When double-buffering is used, the buffer can be written at any time and still maintain the correct
operation. The TCAn.PER is always updated on the UPDATE condition, as shown for dual-slope operation in the
figure below. This prevents wrap-around and the generation of odd waveforms.
MAX
‘‘update’’
‘‘write’’
CNT
BOTTOM
New Period written to New Period written to
New PER is updated
PERB that is higher PERB that is lower
with PERB value.
than current CNT. than current CNT.
Note: Buffering is used in figures illustrating TCA operation if not otherwise specified.
CNT TOP
BOTTOM
Waveform Output
The following equation defines the waveform frequency (fFRQ):
f CLK_PER
fFRQ =
2N CMP0+1
where N represents the prescaler divider used (see the CLKSEL bit field in the TCAn.CTRLA register), and fCLK_PER
is the peripheral clock frequency.
The maximum frequency of the waveform generated is half of the peripheral clock frequency (fCLK_PER/2) when
TCAn.CMP0 is written to 0x0000 and no prescaling is used (N = 1, CLKSEL = 0x0 in TCAn.CTRLA).
Use the TCAn.CMP1 and TCAn.CMP2 registers to get additional waveform outputs WOn. The waveforms WOn can
either be identical or offset to WO0. The offset can be influenced by TCAn.CMPn, TCAn.CNT and the count direction.
The offset in seconds tOffset can be calculated using the equations in the table below. The equations are only valid
when CMPn<CMP0.
Table 21-2. Offset equation overview
The figure below shows leading and trailing offset for WOn, where both equations can be used. The correct equation
is determined by count direction, and the state of CMPn vs CNT when the timer is enabled or CMPn is changed.
Figure 21-10. Offset When Counting Up
CMPn changed
‘‘update’’
causing match to be
Period (T) ‘‘match’’
missed
MAX
TOP
CNT
CMPn
BOTTOM
TOP
CNT
CMPn
BOTTOM
CNT
CMPn
BOTTOM
Waveform Output
Notes:
1. The representation in the figure above is valid when CMPn is updated using CMPnBUF.
2. For single-slope Pulse-Width Modulation (PWM) generation, the counter counting from TOP to BOTTOM is not
supported.
The TCAn.PER register defines the PWM resolution. The minimum resolution is 2 bits (TCAn.PER = 0x0003), and
the maximum resolution is 16 bits (TCAn.PER = MAX).
The following equation calculates the exact resolution in bits for single-slope PWM (RPWM_SS):
log PER+1
RPWM_SS =
log 2
The single-slope PWM frequency (fPWM_SS) depends on the period setting (TCAn.PER), the peripheral clock
frequency fCLK_PER and the TCA prescaler (the CLKSEL bit field in the TCAn.CTRLA register). It is calculated by
the following equation where N represents the prescaler divider used:
fCLK_PER
fPWM_SS =
N PER+1
CMPn
CNT TOP
BOTTOM
Waveform Output
Note: The representation in the figure above is valid when CMPn is updated using CMPnBUF.
The Period (TCAn.PER) register defines the PWM resolution. The minimum resolution is 2 bits (TCAn.PER =
0x0003), and the maximum resolution is 16 bits (TCAn.PER = MAX).
The following equation calculates the exact resolution in bits for dual-slope PWM (RPWM_DS):
log PER+1
RPWM_DS =
log 2
The PWM frequency depends on the period setting in the TCAn.PER register, the peripheral clock frequency
(fCLK_PER), and the prescaler divider selected in the CLKSEL bit field in the TCAn.CTRLA register. It is calculated by
the following equation:
fCLK_PER
fPWM_DS =
2N ⋅ PER
N represents the prescaler divider used.
Using dual-slope PWM results in approximately half the maximum operation frequency compared to single-slope
PWM operation, due to twice the number of timer increments per period.
OUT
Waveform WOn
CMPnEN INVEN
CNT
CMPn
B OTTOM
Waveform Output
Note: The maximum duty-cycle of the waveform output is TOP/(TOP+1)
Activating Split mode results in changes to the functionality of some registers and register bits. The modifications are
described in a separate register map (see 21.6. Register Summary - Split Mode).
Block Diagram
Figure 21-16. Timer/Counter Block Diagram Split Mode
Base Counter
Clock Select
HPER LPER CTRLA
‘‘count high’’
Counter
‘‘load high’’ HUNF
‘‘count low’’ Control Logic (INT Req. and Event)
HCNT LCNT
‘‘load low’’
LUNF
(INT Req. and Event)
BOTTOML
=0
BOTTOMH
=0
Compare Unit n
LCMPn
Waveform WOn Out
Generation
‘‘match’’ LCMPn
=
(INT Req. and Event)
Compare Unit n
HCMPn
Waveform
Generation
WO[n+3] Out
‘‘match’’
=
21.3.4 Events
The TCA can generate the events described in the table below. All event generators except TCAn_HUNF are
shared between Normal mode and Split mode operation, and the generator name indicates what specific signal the
generator represents in each mode in the following way: OVF_LUNF corresponds to overflow in Normal mode and
Low byte timer underflow in Split mode. The same applies to CMPn_LCMPn.
Table 21-3. Event Generators in TCA
Note: The conditions for generating an event are identical to those that will raise the corresponding interrupt flag in
the TCAn.INTFLAGS register for both Normal mode and Split mode.
The TCA has two event users for detecting and acting upon input events. The table below describes the event users
and their associated functionality.
User Name
Description Input Detection Async/Sync
Peripheral Input
Count on a positive event edge Edge Sync
Count on any event edge Edge Sync
CNTA Count while the event signal is high Level Sync
The event level controls the count direction, up when low and
Level Sync
down when high
TCAn
The event level controls count direction, up when low and
Level Sync
down when high
The specific actions described in the table above are selected by writing to the Event Action (EVACTA, EVACTB) bits
in the Event Control (TCAn.EVCTRL) register. Input events are enabled by writing a ‘1’ to the Enable Counter Event
Input (CNTAEI and CNTBEI) bits in the TCAn.EVCTRL register.
If both EVACTA and EVACTB are configured to control the count direction, the event signals will be OR’ed to
determine the count direction. Both event inputs must then be low for the counter to count upwards.
Notes:
1. Event inputs are not used in Split mode.
2. Event actions with level input detection only work reliably if the event frequency is less than the timer’s
frequency.
Refer to the Event System (EVSYS) section for more details regarding event types and Event System configuration.
21.3.5 Interrupts
Table 21-5. Available Interrupt Vectors and Sources in Normal Mode
...........continued
Name Vector Description Conditions
Match between the counter value and the low byte of the Compare 2
LCMP2 Compare Channel 2 interrupt
register
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUNSTDBY CLKSEL[2:0] ENABLE
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 0 – ENABLE Enable
Value Description
0 The peripheral is disabled
1 The peripheral is enabled
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMP2EN CMP1EN CMP0EN ALUPD WGMODE[2:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Note:
1. When counting up.
Name: CTRLC
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMP2OV CMP1OV CMP0OV
Access R/W R/W R/W
Reset 0 0 0
Note: When the output is connected to the pad, overriding these bits will not work unless the CMPnEN bits in
the TCAn.CTRLB register have been set. If the output is connected to CCL, the CMPnEN bits in the TCAn.CTRLB
register are bypassed.
Name: CTRLD
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SPLITM
Access R/W
Reset 0
Name: CTRLECLR
Offset: 0x04
Reset: 0x00
Property: -
Use this register instead of a Read-Modify-Write (RMW) to clear individual bits by writing a ‘1’ to its bit location.
Bit 7 6 5 4 3 2 1 0
CMD[1:0] LUPD DIR
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: CTRLESET
Offset: 0x05
Reset: 0x00
Property: -
Use this register instead of a Read-Modify-Write (RMW) to set individual bits by writing a ‘1’ to its bit location.
Bit 7 6 5 4 3 2 1 0
CMD[1:0] LUPD DIR
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: CTRLFCLR
Offset: 0x06
Reset: 0x00
Property: -
Use this register instead of a Read-Modify-Write (RMW) to clear individual bits by writing a ‘1’ to its bit location.
Bit 7 6 5 4 3 2 1 0
CMP2BV CMP1BV CMP0BV PERBV
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: CTRLFSET
Offset: 0x07
Reset: 0x00
Property: -
Use this register instead of a Read-Modify-Write (RMW) to set individual bits by writing a ‘1’ to its bit location.
Bit 7 6 5 4 3 2 1 0
CMP2BV CMP1BV CMP0BV PERBV
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: EVCTRL
Offset: 0x09
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
EVACTB[2:0] CNTBEI EVACTA[2:0] CNTAEI
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTCTRL
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMP2 CMP1 CMP0 OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTFLAGS
Offset: 0x0B
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMP2 CMP1 CMP0 OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: DBGCTRL
Offset: 0x0E
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: TEMP
Offset: 0x0F
Reset: 0x00
Property: -
The Temporary register is used by the CPU for 16-bit single-cycle access to the 16-bit registers of this peripheral. The
register is common for all the 16-bit registers of this peripheral and can be read and written by software. For more
details on reading and writing 16-bit registers, refer to Accessing 16-Bit Registers in the AVR CPU section.
Bit 7 6 5 4 3 2 1 0
TEMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CNT
Offset: 0x20
Reset: 0x00
Property: -
The TCAn.CNTL and TCAn.CNTH register pair represents the 16-bit value, TCAn.CNT. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit 15 14 13 12 11 10 9 8
CNT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: PER
Offset: 0x26
Reset: 0xFFFF
Property: -
The TCAn.PER register contains the 16-bit TOP value in the timer/counter in all modes of operation, except
Frequency Waveform Generation (FRQ).
The TCAn.PERL and TCAn.PERH register pair represents the 16-bit value, TCAn.PER. The low byte [7:0] (suffix L)
is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit 15 14 13 12 11 10 9 8
PER[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
PER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Name: CMPn
Offset: 0x28 + n*0x02 [n=0..2]
Reset: 0x00
Property: -
This register is continuously compared to the counter value. Normally, the outputs from the comparators are used to
generate waveforms.
The TCAn.CMPn registers are updated with the buffer value from their corresponding TCAn.CMPnBUF register when
an UPDATE condition occurs.
The TCAn.CMPnL and TCAn.CMPnH register pair represents the 16-bit value, TCAn.CMPn. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit 15 14 13 12 11 10 9 8
CMP[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: PERBUF
Offset: 0x36
Reset: 0xFFFF
Property: -
This register serves as the buffer for the Period (TCAn.PER) register. Writing to this register from the CPU or UPDI
will set the Period Buffer Valid (PERBV) bit in the TCAn.CTRLF register.
The TCAn.PERBUFL and TCAn.PERBUFH register pair represents the 16-bit value, TCAn.PERBUF. The low byte
[7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit 15 14 13 12 11 10 9 8
PERBUF[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
PERBUF[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Name: CMPnBUF
Offset: 0x38 + n*0x02 [n=0..2]
Reset: 0x00
Property: -
This register serves as the buffer for the associated Compare n (TCAn.CMPn) register. Writing to this register from
the CPU or UPDI will set the Compare Buffer valid (CMPnBV) bit in the TCAn.CTRLF register.
The TCAn.CMPnBUFL and TCAn.CMPnBUFH register pair represents the 16-bit value, TCAn.CMPnBUF. The low
byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset +
0x01.
Bit 15 14 13 12 11 10 9 8
CMPBUF[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CMPBUF[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUNSTDBY CLKSEL[2:0] ENABLE
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 0 – ENABLE Enable
Value Description
0 The peripheral is disabled
1 The peripheral is enabled
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
HCMP2EN HCMP1EN HCMP0EN LCMP2EN LCMP1EN LCMP0EN
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: CTRLC
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
HCMP2OV HCMP1OV HCMP0OV LCMP2OV LCMP1OV LCMP0OV
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Note: When the output is connected to the pad, overriding these bits will not work unless the xCMPnEN bits in
the TCAn.CTRLB register have been set. If the output is connected to CCL, the xCMPnEN bits in the TCAn.CTRLB
register are bypassed.
Name: CTRLD
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SPLITM
Access R/W
Reset 0
Name: CTRLECLR
Offset: 0x04
Reset: 0x00
Property: -
Use this register instead of a Read-Modify-Write (RMW) to clear individual bits by writing a ‘1’ to its bit location.
Bit 7 6 5 4 3 2 1 0
CMD[1:0] CMDEN[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: CTRLESET
Offset: 0x05
Reset: 0x00
Property: -
Use this register instead of a Read-Modify-Write (RMW) to set individual bits by writing a ‘1’ to its bit location.
Bit 7 6 5 4 3 2 1 0
CMD[1:0] CMDEN[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTCTRL
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
LCMP2 LCMP1 LCMP0 HUNF LUNF
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: INTFLAGS
Offset: 0x0B
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
LCMP2 LCMP1 LCMP0 HUNF LUNF
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: DBGCTRL
Offset: 0x0E
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: LCNT
Offset: 0x20
Reset: 0x00
Property: -
The TCAn.LCNT register contains the counter value for the low byte timer. CPU and UPDI write access has priority
over count, clear or reload of the counter.
Bit 7 6 5 4 3 2 1 0
LCNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: HCNT
Offset: 0x21
Reset: 0x00
Property: -
The TCAn.HCNT register contains the counter value for the high byte timer. CPU and UPDI write access has priority
over count, clear or reload of the counter.
Bit 7 6 5 4 3 2 1 0
HCNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: LPER
Offset: 0x26
Reset: 0xFF
Property: -
The TCAn.LPER register contains the TOP value for the low byte timer.
Bit 7 6 5 4 3 2 1 0
LPER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Name: HPER
Offset: 0x27
Reset: 0xFF
Property: -
The TCAn.HPER register contains the TOP value for the high byte timer.
Bit 7 6 5 4 3 2 1 0
HPER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Name: LCMPn
Offset: 0x28 + n*0x02 [n=0..2]
Reset: 0x00
Property: -
The TCAn.LCMPn register represents the compare value of Compare Channel n for the low byte timer. This register
is continuously compared to the counter value of the low byte timer, TCAn.LCNT. Normally, the outputs from the
comparators are then used to generate waveforms.
Bit 7 6 5 4 3 2 1 0
LCMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: HCMPn
Offset: 0x29 + n*0x02 [n=0..2]
Reset: 0x00
Property: -
The TCAn.HCMPn register represents the compare value of Compare Channel n for the high byte timer. This register
is continuously compared to the counter value of the high byte timer, TCAn.HCNT. Normally, the outputs from the
comparators are then used to generate waveforms.
Bit 7 6 5 4 3 2 1 0
HCMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
22.1 Features
• 16-bit Counter Operation Modes:
– Periodic interrupt
– Time-out check
– Input capture
• On event
• Frequency measurement
• Pulse-width measurement
• Frequency and pulse-width measurement
• 32-bit capture
– Single-shot
– 8-bit Pulse-Width Modulation (PWM)
• Noise Canceler on Event Input
• Synchronize Operation with TCAn
22.2 Overview
The capabilities of the 16-bit Timer/Counter type B (TCB) include frequency and waveform generation and input
capture on event with time and frequency measurement of digital signals. The TCB consists of a base counter and
control logic that can be set in one of eight different modes, each mode providing unique functionality. The base
counter is clocked by the peripheral clock with optional prescaling.
Clock Select
CTRLA
Mode
CTRLB
Event Action
EVCTRL
Count Events
Counter
Control
Clear
CNT Logic CAPT
(Interrupt Request
Restart and Events)
OVF
= MAX (Interrupt Request
and Events)
BOTTOM
=0
CCMP
Waveform
Match WO
= Generation
The timer/counter can be clocked from the Peripheral Clock (CLK_PER), from a 16-bit Timer/Counter type A
(CLK_TCAn) or the Event System (EVSYS).
Figure 22-2. Timer/Counter Clock Logic
CTRLA
CLK_PER
DIV2 CLK_TCB
CLK_TCAn CNT
Events
Control
Logic
The Clock Select (CLKSEL) bit field in the Control A (TCBn.CTRLA) register selects one of the prescaler outputs
directly, or an event channel as the clock (CLK_TCB) input.
Setting the timer/counter to use the clock from a TCAn allows the timer/counter to run in sync with that TCAn.
By using the EVSYS, any event source, such as an external clock signal on any I/O pin, may be used as the counter
clock input or as a control logic input. When an event action controlled operation is used, the clock selection must be
set to use an event channel as the counter input.
22.3.1 Definitions
The following definitions are used throughout the documentation:
Table 22-1. Timer/Counter Definitions
Name Description
BOTTOM The counter reaches BOTTOM when it becomes 0x0000
MAX The counter reaches the maximum when it becomes 0xFFFF
TOP The counter reaches TOP when it becomes equal to the highest value in the count sequence
CNT Count (TCBn.CNT) register value
CCMP Capture/Compare (TCBn.CCMP) register value
Note: In general, the term ‘timer’ is used when the timer/counter is counting periodic clock ticks. The term ‘counter’
is used when the input signal has sporadic or irregular ticks.
22.3.2 Initialization
By default, the TCB is in Periodic Interrupt mode. Follow these steps to start using it:
1. Write a TOP value to the Compare/Capture (TCBn.CCMP) register.
2. Optional: Write the Compare/Capture Output Enable (CCMPEN) bit in the Control B (TCBn.CTRLB) register
to ‘1’. This will make the waveform output available on the corresponding pin, overriding the value in the
corresponding PORT output register.
3. Enable the counter by writing a ‘1’ to the ENABLE bit in the Control A (TCBn.CTRLA) register.
The counter will start counting clock ticks according to the prescaler setting in the Clock Select (CLKSEL) bit
field in the Control A (TCBn.CTRLA) register.
4. The counter value can be read from the Count (TCBn.CNT) register. The peripheral will generate a CAPT
interrupt and event when the CNT value reaches TOP.
a. If the Compare/Capture register is modified to a value lower than the current CNT, the peripheral will
count to MAX and wrap around.
b. At MAX, an OVF interrupt and event will be generated.
22.3.3 Operation
22.3.3.1 Modes
The timer can be configured to run in one of the eight different modes described in the sections below. The event
pulse needs to be longer than one system clock cycle to ensure edge detection.
MAX CAPT
(Interrupt Request
and Event)
OVF
(Interrupt Request
and Event)
TOP
CNT
BOTTOM
TOP changed to OVF set, and CNT set to
a value lower than CNT BOTTOM
CAPT
Event Input (Interrupt Request
and Event)
OVF
Event Detector (Interrupt Request
and Event)
MAX
TOP
CNT
BOTTOM
TOP changed to a value lower OVF set, and CNT
than CNT set to BOTTOM
CAPT
Event Input (Interrupt Request
and Event)
OVF
(Interrupt Request
and Event)
Event Detector
MAX
CNT
BOTTOM
Important: It is recommended to write 0x0000 to the Count (TCBn.CNT) register when entering this
mode from any other mode.
CAPT
(Interrupt Request
and Event)
Event Input
OVF
(Interrupt Request
and Event)
Event Detector
MAX
CNT
BOTTOM
Copy CNT to CCMP, OVF set, and CNT Copy CNT to CCMP,
CAPT and restart set to BOTTOM CAPT and restart
CAPT
(Interrupt Request
Event Input and Event)
OVF
(Interrupt Request
and Event)
Edge Detector
MAX
CNT
BOTTOM
The CAPT Interrupt flag is automatically cleared after the low byte of the Compare/Capture (TCBn.CCMP) register
has been read, and the timer/counter is ready for a new capture sequence. Therefore, the Count (TCBn.CNT)
register must be read before the Compare/Capture (TCBn.CCMP) register, since it is reset to BOTTOM at the next
positive edge of the event input signal. An OVF interrupt and event is generated when the CNT value is MAX.
Figure 22-8. Input Capture Frequency and Pulse-Width Measurement
CAPT
(Interrupt Request
Event Input and Event)
Event Detector
MAX
CNT
BOTTOM
Start Copy CNT to Stop counter and CPU reads the
counter CCMP CAPT CCMP register
Edge Detector
TOP
CNT
BOTTOM
Output
CCMPL
CNT
CCMPH
BOTTOM
Output
22.3.3.2 Output
Timer synchronization and output logic level are dependent on the selected Timer Mode (CNTMODE) bit field in
Control B (TCBn.CTRLB) register. In Single-Shot mode, the timer/counter can be configured so that the signal
generation happens asynchronously to an incoming event (ASYNC = 1 in TCBn.CTRLB). The output signal is then
set immediately at the incoming event instead of being synchronized to the TCB clock. Even though the output is set
immediately, it will take two to three CLK_TCB cycles before the counter starts counting.
Writing the Compare/Capture Output Enable (CCMPEN) bit in TCBn.CTRLB to ‘1’ enables the waveform output. This
will make the waveform output available on the corresponding pin, overriding the value in the corresponding PORT
output register.
The different configurations and their impact on the output are listed in the table below.
Table 22-2. Output Configuration
It is not recommended to change modes while the peripheral is enabled, as this can produce an unpredictable
output. There is a possibility that an interrupt flag is set during the timer configuration. It is recommended to clear the
Timer/Counter Interrupt Flags (TCBn.INTFLAGS) register after configuring the peripheral.
System Configuration
• Configure a source (TCA, events, CLK_PER) for the count input for the LSB TCB, according to the application
requirements
• Configure the event system to route the OVF events from the LSB TCB (event generator) to the MSB TCB
(event user)
• Configure the event system to route the same capture event (CAPT) generator to both TCBs
Capture request
TCB1.CCMP TCB0.CCMP
32-bit capture value: Byte 3 Byte 2 Byte 1 Byte 0
(MSB) (LSB)
22.3.4 Events
The TCB can generate the events described in the following table:
Generator Name
Description Event Type Generating Clock Domain Length of Event
Peripheral Event
CAPT CAPT flag set
TCBn Pulse CLK_PER One CLK_PER period
OVF OVF flag set
The conditions for generating the CAPT and OVF events are identical to those that will raise the corresponding
interrupt flags in the Timer/Counter Interrupt Flags (TCBn.INTFLAGS) register. Refer to the Event System section for
more details regarding event users and Event System configuration.
The TCB can receive the events described in the following table:
Table 22-4. Event Users and Available Event Actions in TCB
User Name
Description Input Detection Async/Sync
Peripheral Input
Time-Out Check Count mode
Input Capture on Event Count mode
Input Capture Frequency Measurement Count mode
Sync
CAPT Input Capture Pulse-Width Measurement Count mode
TCBn Edge
Input Capture Frequency and Pulse-Width Measurement
Count mode
Single-Shot Count mode Both
COUNT Event as clock source in combination with a count mode Sync
CAPT and COUNT are TCB event users that detect and act upon input events.
The COUNT event user is enabled on the peripheral by modifying the Clock Select (CLKSEL) bit field in the Control A
(TCBn.CTRLA) register to EVENT and setting up the Event System accordingly.
If the Capture Event Input Enable (CAPTEI) bit in the Event Control (TCBn.EVCTRL) register is written to
‘1’, incoming events will result in an event action as defined by the Event Edge (EDGE) bit in Event Control
(TCBn.EVCTRL) register and the Timer Mode (CNTMODE) bit field in Control B (TCBn.CTRLB) register. The event
needs to last for at least one CLK_PER cycle to be recognized.
If the Asynchronous mode is enabled for Single-Shot mode, the event is edge-triggered and will capture changes on
the event input shorter than one peripheral clock cycle.
22.3.5 Interrupts
Table 22-5. Available Interrupt Vectors and Sources
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
22.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUNSTDBY CASCADE SYNCUPD CLKSEL[2:0] ENABLE
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 0 – ENABLE Enable
Writing this bit to ‘1’ enables the Timer/Counter type B peripheral.
22.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ASYNC CCMPINIT CCMPEN CNTMODE[2:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: EVCTRL
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
FILTER EDGE CAPTEI
Access R/W R/W R/W
Reset 0 0 0
Name: INTCTRL
Offset: 0x05
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
OVF CAPT
Access R/W R/W
Reset 0 0
Name: INTFLAGS
Offset: 0x06
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
OVF CAPT
Access R/W R/W
Reset 0 0
TOP
Counter Mode Interrupt Set Condition CAPT
Value
Periodic Interrupt mode Set when the counter reaches TOP
Timeout Check mode Set when the counter reaches TOP CCMP CNT == TOP
Single-Shot mode Set when the counter reaches TOP
On Event, copy CNT
Set on edge when the Capture register is
Input Capture Frequency to CCMP, and restart
loaded and the counter restarts; the flag clears
Measurement mode counting (CNT ==
when the capture is read
BOTTOM)
Set when an event occurs and the Capture
Input Capture on Event
register is loaded; the flag clears when the
mode
capture is read --
Set on edge when the Capture register is On Event, copy CNT
Input Capture Pulse-Width
loaded; the previous edge initialized the count; to CCMP, and continue
Measurement mode
the flag clears when the capture is read counting
Input Capture Frequency Set on the second edge (positive or negative)
and Pulse-Width when the counter is stopped; the flag clears
Measurement mode when the capture is read
8-Bit PWM mode Set when the counter reaches CCMH CCML CNT == CCMH
22.5.6 Status
Name: STATUS
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUN
Access R
Reset 0
Bit 0 – RUN Run
When the counter is running, this bit is set to ‘1’. When the counter is stopped, this bit is cleared to ‘0’.
The bit is read-only and cannot be set by UPDI.
Name: DBGCTRL
Offset: 0x08
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: TEMP
Offset: 0x09
Reset: 0x00
Property: -
The Temporary register is used by the CPU for 16-bit single-cycle access to the 16-bit registers of this peripheral. The
register is common for all the 16-bit registers of this peripheral and can be read and written by software. For more
details on reading and writing 16-bit registers, refer to Accessing 16-Bit Registers in the AVR CPU section.
Bit 7 6 5 4 3 2 1 0
TEMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
22.5.9 Count
Name: CNT
Offset: 0x0A
Reset: 0x00
Property: -
The TCBn.CNTL and TCBn.CNTH register pair represents the 16-bit value TCBn.CNT. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
CPU and UPDI write access has priority over internal updates of the register.
Bit 15 14 13 12 11 10 9 8
CNT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
22.5.10 Capture/Compare
Name: CCMP
Offset: 0x0C
Reset: 0x00
Property: -
The TCBn.CCMPL and TCBn.CCMPH register pair represents the 16-bit value TCBn.CCMP. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
This register has different functions depending on the mode of operation:
• For Capture operation, these registers contain the captured value of the counter at the time the capture occurs
• In Periodic Interrupt/Time-Out and Single-Shot mode, this register acts as the TOP value
• In 8-bit PWM mode, TCBn.CCMPL and TCBn.CCMPH act as two independent registers: The period of the
waveform is controlled by CCMPL, while CCMPH controls the duty cycle.
Bit 15 14 13 12 11 10 9 8
CCMP[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CCMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
23.1 Features
• 16-Bit Resolution
• Selectable Clock Sources
• Programmable 15-Bit Clock Prescaling
• One Compare Register
• One Period Register
• Clear Timer on Period Overflow
• Optional Interrupt/Event on Overflow and Compare Match
• Periodic Interrupt and Event
• Crystal Error Correction
23.2 Overview
The RTC peripheral offers two timing functions: The Real-Time Counter (RTC) and a Periodic Interrupt Timer (PIT).
The PIT functionality can be enabled independently of the RTC functionality.
TOSC1
32.768 kHz Crystal Osc.
TOSC2
DIV32
PER
CLK_RTC = Overflow
Correction 15-bit
CNT
counter prescaler
= Compare
PIT CMP
RTC
Period
23.3 Clocks
The peripheral clock (CLK_PER) is required to be at least four times faster than the RTC clock (CLK_RTC) for
reading the counter value, regardless of the prescaler setting.
A 32.768 kHz crystal can be connected to the TOSC1 or TOSC2 pins, along with any required load capacitors.
Alternatively, an external digital clock can be connected to the TOSC1 pin.
23.4.1 Initialization
Before enabling the RTC peripheral and the desired actions (interrupt requests and output events), the source clock
for the RTC counter must be configured to operate the RTC.
The CLK_RTC clock configuration is used by both RTC and PIT functionalities.
23.5.1 Initialization
To operate the PIT, follow these steps:
1. Configure the RTC clock CLK_RTC as described in section 23.4.1.1. Configure the Clock CLK_RTC.
2. Enable the interrupt by writing a ‘1’ to the Periodic Interrupt (PI) bit in the PIT Interrupt Control
(RTC.PITINTCTRL) register.
3. Select the period for the interrupt by writing the desired value to the Period (PERIOD) bit field in the Periodic
Interrupt Timer Control A (RTC.PITCTRLA) register.
4. Enable the PIT by writing a ‘1’ to the Periodic Interrupt Timer Enable (PITEN) bit in the RTC.PITCTRLA
register.
Continuous Operation
After the first interrupt, the PIT will continue toggling every ½ PIT period resulting in a full PIT period signal.
CLK_RTC
Prescaler
..000000
..000001
..000010
..000100
..000101
..001000
..001001
..001010
..010000
..010001
..010010
..010100
..010101
..100000
..100001
..100010
..100100
..100101
..101000
..101001
..101010
..000011
..000110
..001011
..001100
..001101
..010011
..010110
..011000
..011001
..011010
..100011
..100110
..101011
..101100
..101101
..000111
..001110
..010111
..011011
..011100
..011101
..100111
..101110
..001111
..011110
..101111
..011111
counter
value (LSB)
Prescaler bit 3
(CYC16)
23.7 Events
The RTC can generate the events described in the following table:
The conditions for generating the OVF and CMP events are identical to those that will raise the corresponding
interrupt flags in the RTC.INTFLAGS register.
Refer to the EVSYS - Event System section for more details regarding event users and Event System configuration.
23.8 Interrupts
Table 23-1. Available Interrupt Vectors and Sources
PIT Periodic Interrupt Timer A time period has passed, as configured by the PERIOD bit field in
interrupt RTC.PITCTRLA
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
Note that:
• The RTC has two INTFLAGS registers: RTC.INTFLAGS and RTC.PITINTFLAGS.
• The RTC has two INTCTRL registers: RTC.INTCTRL and RTC.PITINTCTRL.
23.10 Synchronization
Both the RTC and the PIT are asynchronous, operating from a different clock source (CLK_RTC) independently of
the peripheral clock (CLK_PER). For Control and Count register updates, it will take some RTC and/or peripheral
clock cycles before an updated register value is available in a register or until a configuration change affects the RTC
or PIT, respectively. This synchronization time is described for each register in the Register Description section.
For some RTC registers, a Synchronization Busy (CMPBUSY, PERBUSY, CNTBUSY, CTRLABUSY) flag is available
in the Status (RTC.STATUS) register.
For the RTC.PITCTRLA register, a Synchronization Busy (CTRLBUSY) flag is available in the Periodic Interrupt
Timer Status (RTC.PITSTATUS) register.
Check these flags before writing to the mentioned registers.
23.13.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUNSTDBY PRESCALER[3:0] CORREN RTCEN
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
23.13.2 Status
Name: STATUS
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMPBUSY PERBUSY CNTBUSY CTRLABUSY
Access R R R R
Reset 0 0 0 0
Name: INTCTRL
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMP OVF
Access R/W R/W
Reset 0 0
Name: INTFLAGS
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMP OVF
Access R/W R/W
Reset 0 0
23.13.5 Temporary
Name: TEMP
Offset: 0x4
Reset: 0x00
Property: -
The Temporary register is used by the CPU for 16-bit single-cycle access to the 16-bit registers of this peripheral. The
register is common for all the 16-bit registers of this peripheral and can be read and written by software. For more
details on reading and writing 16-bit registers, refer to Accessing 16-Bit Registers in the AVR CPU section.
Bit 7 6 5 4 3 2 1 0
TEMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DBGCTRL
Offset: 0x05
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: CALIB
Offset: 0x06
Reset: 0x00
Property: -
This register stores the error value and the type of correction to be done. The register is written by software with an
error value based on external calibration and/or temperature correction/s.
Bit 7 6 5 4 3 2 1 0
SIGN ERROR[6:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Value Description
0x0 Positive correction causing the prescaler to count slower
0x1 Negative correction causing the prescaler to count faster. This requires that the
minimum prescaler configuration is DIV2
Name: CLKSEL
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CLKSEL[1:0]
Access R/W R/W
Reset 0 0
23.13.9 Count
Name: CNT
Offset: 0x08
Reset: 0x0000
Property: -
The RTC.CNTL and RTC.CNTH register pair represents the 16-bit value, RTC.CNT. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Due to the synchronization between the RTC clock and main clock domains, there is a latency of two RTC clock
cycles from updating the register until this has an effect. The application software needs to check that the CNTBUSY
flag in RTC.STATUS is cleared before writing to this register.
Bit 15 14 13 12 11 10 9 8
CNT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
23.13.10 Period
Name: PER
Offset: 0x0A
Reset: 0xFFFF
Property: -
The RTC.PERL and RTC.PERH register pair represents the 16-bit value, RTC.PER. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Due to the synchronization between the RTC clock and main clock domains, there is a latency of two RTC clock
cycles from updating the register until this has an effect. The application software needs to check that the PERBUSY
flag in RTC.STATUS is cleared before writing to this register.
Bit 15 14 13 12 11 10 9 8
PER[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
PER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
23.13.11 Compare
Name: CMP
Offset: 0x0C
Reset: 0x0000
Property: -
The RTC.CMPL and RTC.CMPH register pair represents the 16-bit value, RTC.CMP. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit 15 14 13 12 11 10 9 8
CMP[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: PITCTRLA
Offset: 0x10
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
PERIOD[3:0] PITEN
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: PITSTATUS
Offset: 0x11
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CTRLBUSY
Access R
Reset 0
Name: PITINTCTRL
Offset: 0x12
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
PI
Access R/W
Reset 0
Name: PITINTFLAGS
Offset: 0x13
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
PI
Access R/W
Reset 0
Name: PITDBGCTRL
Offset: 0x15
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
24.1 Features
• Full-Duplex Operation
• Half-Duplex Operation:
– One-Wire mode
– RS-485 mode
• Asynchronous or Synchronous Operation
• Supports Serial Frames with Five, Six, Seven, Eight or Nine Data Bits and One or Two Stop Bits
• Fractional Baud Rate Generator:
– Can generate the desired baud rate from any peripheral clock frequency
– No need for an external oscillator
• Built-In Error Detection and Correction Schemes:
– Odd or even parity generation and parity check
– Buffer overflow and frame error detection
– Noise filtering including false Start bit detection and digital low-pass filter
• Separate Interrupts for:
– Transmit complete
– Transmit Data register empty
– Receive complete
• Host SPI Mode
• Multiprocessor Communication Mode
• Start-of-Frame Detection
• IRCOM Module for IrDA® Compliant Pulse Modulation/Demodulation
• LIN Client Support
24.2 Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a fast and flexible serial
communication peripheral. The USART supports several different modes of operation that can accommodate multiple
types of applications and communication devices. For example, the One-Wire Half-Duplex mode is useful when low
pin count applications are desired. The communication is frame-based, and the frame format can be customized to
support a wide range of standards.
The USART is buffered in both directions, enabling continued data transmission without any delay between frames.
Separate interrupts for receive and transmit completion allow fully interrupt-driven communication.
The transmitter consists of a two-level write buffer, a shift register, and control logic for different frame formats. The
receiver consists of a two-level receive buffer and a shift register. The status information of the received data is
available for error checking. Data and clock recovery units ensure robust synchronization and noise filtering during
asynchronous data reception.
CLOCK GENERATOR
TRANSMITTER
XDIR
TX Buffer TX Shift Register
TXD
TXDATA
RECEIVER
24.3.1 Initialization
Full-Duplex Mode:
1. Set the baud rate (USARTn.BAUD).
2. Set the frame format and mode of operation (USARTn.CTRLC).
3. Configure the TXD pin as an output.
4. Enable the transmitter and the receiver (USARTn.CTRLB).
Notes:
• For interrupt-driven USART operation, global interrupts must be disabled during the initialization
• Before doing a reinitialization with a changed baud rate or frame format, be sure that there are no ongoing
transmissions while the registers are changed
One-Wire Half-Duplex Mode:
1. Internally connect the TXD to the USART receiver (the LBME bit in the USARTn.CTRLA register).
2. Enable internal pull-up for the RX/TX pin (the PULLUPEN bit in the PORTx.PINnCTRL register).
3. Enable Open-Drain mode (the ODME bit in the USARTn.CTRLB register).
4. Set the baud rate (USARTn.BAUD).
5. Set the frame format and mode of operation (USARTn.CTRLC).
6. Enable the transmitter and the receiver (USARTn.CTRLB).
Notes:
• When Open-Drain mode is enabled, the TXD pin is automatically set to output by hardware
• For interrupt-driven USART operation, global interrupts must be disabled during the initialization
• Before doing a reinitialization with a changed baud rate or frame format, be sure that there are no ongoing
transmissions while the registers are changed
24.3.2 Operation
FRAME
CLK_PER Edge
Detector
XCKO
Transmitter
TXCLK
Receiver
RXCLK
Operating Mode Conditions Baud Rate (Bits Per Seconds) USART.BAUD Register Value
Calculation
Asynchronous fCLK_PER 64 × fCLK_PER 64 × fCLK_PER
fBAUD ≤ fBAUD = BAUD =
S S × BAUD S × fBAUD
USART.BAUD ≥ 64
Synchronous Host fCLK_PER fCLK_PER fCLK_PER
fBAUD ≤ fBAUD = BAUD 15: 6 =
S S × BAUD 15: 6 S × fBAUD
USART.BAUD ≥ 64
• Parity Error detection - checks the validity of the incoming frame by calculating its parity and comparing it to the
Parity bit
Each error detection mechanism controls one error flag that can be read in the RXDATAH register:
• Frame Error (FERR)
• Buffer Overflow (BUFOVF)
• Parity Error (PERR)
The error flags are located in the RX buffer together with their corresponding frame. The RXDATAH register that
contains the error flags must be read before the RXDATAL register since reading the RXDATAL register will trigger
the RX buffer to shift out the RXDATA bytes.
Note: If the Character Size (CHSIZE) bit field in the Control C (USARTn.CTRLC) register is set to nine bits, low
byte first (9BITL), the RXDATAH register will, instead of the RXDATAL register, trigger the RX buffer to shift out the
RXDATA bytes. The RXDATAL register must, in that case, be read before the RXDATAH register.
XCK
INVEN = 0 Data transmit (TxD)
XCK
INVEN = 1 Data transmit (TxD)
Frame Formats
The serial frame for the USART in Host SPI mode always contains eight Data bits. The Data bits can be configured
to be transmitted with either the LSb or MSb first by writing to the Data Order (UDORD) bit in the Control C
(USARTn.CTRLC) register.
SPI does not use Start, Stop, or Parity bits, so the transmission frame can only consist of the Data bits.
Clock Generation
Being a host device in a synchronous communication interface, the USART in Host SPI mode must generate the
interface clock to be shared with the client devices. The interface clock is generated using the fractional Baud Rate
Generator, which is described in 24.3.2.2.1. The Fractional Baud Rate Generator.
Each Data bit is transmitted by pulling the data line high or low for one full clock period. The receiver will sample bits
in the middle of the transmitter hold period, as shown in the figure below. It also shows how the timing scheme can be
configured using the Inverted I/O Enable (INVEN) bit in the PORTx.PINnCTRL register and the USART Clock Phase
(UCPHA) bit in the USARTn.CTRLC register.
XCK XCK
Data transmit (TxD) Data transmit (TxD)
XCK XCK
Data transmit (TxD) Data transmit (TxD)
Note:
1. The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock
cycle.
Data Transmission
Data transmission in Host SPI mode is functionally identical to the general USART operation, as described in
the Operation section. The transmitter interrupt flags and corresponding USART interrupts are also identical. See
24.3.2.3. Data Transmission for further description.
Data Reception
Data reception in Host SPI mode is identical in function to general USART operation as described in the Operation
section. The receiver interrupt flags and the corresponding USART interrupts are also identical, except for the
receiver error flags that are not in use and always read as ‘0’. See 24.3.2.4. Data Reception for further description.
...........continued
USART SPI Comment
XCK SCK Functionally identical
- SS Not supported by USART in Host SPI mode(1)
Note:
1. For the stand-alone SPI peripheral, this pin is used with the Multi-Host function or as a dedicated Client Select
pin. The Multi-Host function is not available with the USART in Host SPI mode, and no dedicated Client Select
pin is available.
Sample
(RXMODE = 0x0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Sample
(RXMODE = 0x1) 0 1 2 3 4 5 6 7 8 1 2
When the clock recovery logic detects a falling edge from the Idle (high) state to the Start bit (low), the Start
bit detection sequence is initiated. In the figure above, sample 1 denotes the first sample reading ‘0’. The clock
recovery logic then uses three subsequent samples (samples 8, 9, and 10 in Normal mode, and samples 4, 5, 6
in Double-Speed mode) to decide if a valid Start bit is received. If two or three samples read ‘0’, the Start bit is
accepted. The clock recovery unit is synchronized, and the data recovery can begin. If less than two samples read
‘0’, the Start bit is rejected. This process is repeated for each Start bit.
RxD BIT n
Sample
(CLK2X = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
Sample
(CLK2X = 1) 1 2 3 4 5 6 7 8 1
A majority voting technique is, like with clock recovery, used on the three center samples for deciding the logic level
of the received bit. The process is repeated for each bit until a complete frame is received.
The data recovery unit will only receive the first Stop bit while ignoring the rest if there are more. If the sampled Stop
bit is read ‘0’, the Frame Error flag will be set. The figure below shows the sampling of a Stop bit. It also shows the
earliest possible beginning of the next frame’s Start bit.
Figure 24-8. Stop Bit and Next Start Bit Sampling
Sample
(CLK2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1
Sample
(CLK2X = 1) 1 2 3 4 5 6 0/1
A new high-to-low transition indicating the Start bit of a new frame can come right after the last of the bits used
for majority voting. For Normal-Speed mode, the first low-level sample can be at the point marked (A) in the figure
above. For Double-Speed mode, the first low level must be delayed to point (B), being the first sample after the
majority vote samples. Point (C) marks a Stop bit of full length at the nominal baud rate.
D Rslow [%] Rfast [%] Maximum Total Error [%] Recommended Max. Receiver Error [%]
5 93.20 106.67 -6.80/+6.67 ±3.0
6 94.12 105.79 -5.88/+5.79 ±2.5
7 94.81 105.11 -5.19/+5.11 ±2.0
8 95.36 104.58 -4.54/+4.58 ±2.0
9 95.81 104.14 -4.19/+4.14 ±1.5
10 96.17 103.78 -3.83/+3.78 ±1.5
Notes:
• D: The sum of character size and parity size (D = 5 to 10 bits)
• RSLOW: The ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
• RFAST: The ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
Table 24-5. Recommended Maximum Receiver Baud Rate Error for Double-Speed Mode
D Rslow [%] Rfast [%] Maximum Total Error [%] Recommended Max. Receiver Error [%]
5 94.12 105.66 -5.88/+5.66 ±2.5
6 94.92 104.92 -5.08/+4.92 ±2.0
7 95.52 104.35 -4.48/+4.35 ±1.5
8 96.00 103.90 -4.00/+3.90 ±1.5
9 96.39 103.53 -3.61/+3.53 ±1.5
10 96.70 103.23 -3.30/+3.23 ±1.0
Notes:
• D: The sum of character size and parity size (D = 5 to 10 bits)
• RSLOW: The ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
• RFAST: The ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
The recommendations of the maximum receiver baud rate error were made under the assumption that the receiver
and transmitter equally divide the maximum total error.
The following equations are used to calculate the maximum ratio of the incoming data rate and the internal receiver
baud rate.
S D+1 S D+2
RSLOW = RFAST =
S D + 1 + SF − 1 S D + 1 + SM
24.3.3.2.5 Auto-Baud
The auto-baud feature lets the USART configure its BAUD register based on input from a communication device,
which allows the device to communicate autonomously with multiple devices communicating with different baud
rates. The USART peripheral features two auto-baud modes: Generic Auto-Baud mode and LIN Constrained Auto-
Baud mode.
Both auto-baud modes must receive an auto-baud frame, as seen in the figure below.
Tbit
8 Tbit
The break field is detected when 12 or more consecutive low cycles are sampled and notifies the USART that it
is about to receive the synchronization field. After the break field, when the Start bit of the synchronization field is
detected, a counter running at the peripheral clock speed is started. The counter is then incremented for the next
eight Tbit of the synchronization field. When all eight bits are sampled, the counter is stopped. The resulting counter
value is in effect the new BAUD register value.
When the USART Receive mode is set to GENAUTO (the RXMODE bit field in the USARTn.CTRLB register), the
Generic Auto-Baud mode is enabled. In this mode, one can set the Wait For Break (WFB) bit in the USARTn.STATUS
register to enable detection of a break field of any length (that is, also shorter than 12 cycles). This makes it possible
to set an arbitrary new baud rate without knowing the current baud rate. If the measured sync field results in a valid
BAUD value (0x0064 - 0xFFFF), the BAUD register is updated.
When USART Receive mode is set to LINAUTO mode (the RXMODE bit field in the USARTn.CTRLB register),
it follows the LIN format. The WFB functionality of the Generic Auto-Baud mode is not compatible with the
LIN Constrained Auto-Baud mode, which means that the received signal must be low for 12 peripheral clock
cycles or more for a break field to be valid. When a break field has been detected, the USART expects the
following synchronization field character to be 0x55. If the received synchronization field character is not 0x55,
the Inconsistent Sync Field Error Flag (the ISFIF bit in the USARTn.STATUS register) is set, and the baud rate is
unchanged.
One-Wire Mode
One-Wire mode is enabled by setting the Loop-Back Mode Enable (LBME) bit in the USARTn.CTRLA register. This
will enable an internal connection between the TXD pin and the USART receiver, making the TXD pin a combined
TxD/RxD line. The RXD pin will be disconnected from the USART receiver and may be controlled by a different
peripheral.
In One-Wire mode, multiple devices can manipulate the TxD/RxD line at the same time. In the case where one
device drives the pin to a logical high level (VCC), and another device pulls the line low (GND), a short will occur. To
accommodate this, the USART features an Open-Drain mode (the ODME bit in the USARTn.CTRLB register), which
prevents the transmitter from driving a pin to a logical high level, thereby constraining it to only be able to pull it low.
Combining this function with the internal pull-up feature (the PULLUPEN bit in the PORTx.PINnCTRL register) will
let the line be held high through a pull-up resistor, allowing any device to pull it low. When the line is pulled low, the
current from VCC to GND will be limited by the pull-up resistor. The TXD pin is automatically set to output by hardware
when the Open-Drain mode is enabled.
When the USART is transmitting to the TxD/RxD line, it will also receive its transmission. This can be used to detect
overlapping transmissions by checking if the received data are the same as the transmitted data.
RS-485 Mode
RS-485 is a communication standard supported by the USART peripheral. It is a physical interface that defines the
setup of a communication circuit. Data are transmitted using differential signaling, making communication robust
against noise. RS-485 is enabled by writing the RS485 bit in the USARTn.CTRLA register to ‘1’.
The RS-485 mode supports external line driver devices that convert a single USART transmission into corresponding
differential pair signals. It implements automatic control of the XDIR pin that can be used to enable transmission
or reception for the line driver device. The USART automatically drives the XDIR pin high while the USART is
transmitting and pulls it low when the transmission is complete. An example of such a circuit is shown in the figure
below.
TX Driver
XDIR Differential Bus
USART +
-
RX Driver
RXD
The XDIR pin goes high one baud clock cycle in advance of data being shifted out to allow some guard time to
enable the external line driver. The XDIR pin will remain high for the complete frame, including Stop bit(s).
Figure 24-11. XDIR Drive Timing
TxD St 0 1 2 3 4 5 6 7 Sp1
XDIR
Guard
Stop
time
RS-485 mode is compatible with One-Wire mode. One-Wire mode enables an internal connection between the TXD
pin and the USART receiver, making the TXD pin a combined TxD/RxD line. The RXD pin will be disconnected from
the USART receiver and may be controlled by a different peripheral. An example of such a circuit is shown in the
figure below.
Figure 24-12. RS-485 with Loop-Back Mode Connection
TX Driver
XDIR Differential Bus
USART +
-
RX Driver
RXD
Encoded RxD
Pulse
Decoding
Decoded RxD
USART RXD
Decoded RxD TXD
Pulse
Encoding
Encoded RxD
The USART is set in IRCOM mode by writing 0x02 to the CMODE bit field in the USARTn.CTRLC register. The data
on the TXD/RXD pins are the inverted values of the transmitted/received infrared pulse. It is also possible to select an
event channel from the Event System as an input for the IRCOM receiver. This enables the IRCOM to receive input
from the I/O pins or sources other than the corresponding RXD pin, which will disable the RxD input from the USART
pin.
For transmission, three pulse modulation schemes are available:
• 3/16 of the baud rate period
• Fixed programmable pulse time based on the peripheral clock frequency
• Pulse modulation disabled
For the reception, a fixed programmable minimum high-level pulse-width for the pulse to be decoded as a logical ‘0’
is used. Shorter pulses will then be discarded, and the bit will be decoded to logical ‘1’ as if no pulse was received.
Double-Speed mode cannot be used for the USART when IRCOM mode is enabled.
24.3.4.1 Parity
Parity bits can be used by the USART to check the validity of a data frame. The Parity bit is set by the transmitter
based on the number of bits with the value of ‘1’ in a transmission and controlled by the receiver upon reception.
If the Parity bit is inconsistent with the transmission frame, the receiver may assume that the data frame has been
corrupted.
Even or odd parity can be selected for error checking by writing the Parity Mode (PMODE) bit field in the
USARTn.CTRLC register. If even parity is selected, the Parity bit is set to ‘1’ if the number of Data bits with value ‘1’
is odd (making the total number of bits with value ‘1’ even). If odd parity is selected, the Parity bit is set to ‘1’ if the
number of data bits with value ‘1’ is even (making the total number of bits with value ‘1’ odd).
When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result
with the Parity bit of the corresponding frame. If a parity error is detected, the Parity Error flag (the PERR bit in the
USARTn.RXDATAH register) is set.
If LIN Constrained Auto-Baud mode is enabled (RXMODE = 0x03 in the USARTn.CTRLB register), a parity check
is performed only on the protected identifier field. A parity error is detected if one of the equations below is not true,
which sets the Parity Error flag.
P0 = ID0 XOR ID1 XOR ID2 XOR ID4
P1 = NOT ID1 XOR ID3 XOR ID4 XOR ID5
Figure 24-14. Protected Identifier Field and Mapping of Identifier and Parity Bits
Protected identifier field
Note: The SLEEP instruction will not shut down the oscillator if there is ongoing communication.
4. The addressed MCU will disable MPCM and receive all data frames. The other client MCUs will ignore the
data frames.
5. When the addressed MCU has received the last data frame, it must enable MPCM again and wait for a new
address frame from the host.
The process then repeats from step 2.
24.3.5 Events
The USART can generate the events described in the table below.
Table 24-7. Event Generators in USART
The table below describes the event user and its associated functionality.
Table 24-8. Event Users in USART
User Name
Description Input Detection Async/Sync
Peripheral Input
USARTn IREI USARTn IrDA event input Pulse Sync
24.3.6 Interrupts
Table 24-9. Available Interrupt Vectors and Sources
DRE Data Register Empty The transmit buffer is empty/ready to receive new data (DREIE)
interrupt
TXC Transmit Complete The entire frame in the transmit shift register has been shifted out and there
interrupt are no new data in the transmit buffer (TXCIE)
When an interrupt condition occurs, the corresponding interrupt flag is set in the STATUS (USARTn.STATUS)
register.
An interrupt source is enabled or disabled by writing to the corresponding bit in the Control A (USARTn.CTRLA)
register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the Interrupt flag is set.
The interrupt request remains active until the Interrupt flag is cleared. See the USARTn.STATUS register for details
on how to clear Interrupt flags.
Name: RXDATAL
Offset: 0x00
Reset: 0x00
Property: -
This register contains the eight LSbs of the data received by the USART receiver. The USART receiver is double-
buffered, and this register always represents the data for the oldest received frame. If the data for only one frame is
present in the receive buffer, this register contains that data.
The buffer shifts out the data either when RXDATAL or RXDATAH is read, depending on the configuration. The
register, which does not lead to data being shifted, must be read first to be able to read both bytes before shifting.
When the Character Size (CHSIZE) bit field in the Control C (USARTn.CTRLC) register is configured to 9-bit (low
byte first), a read of RXDATAH shifts the receive buffer, or else, RXDATAL shifts the buffer.
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: RXDATAH
Offset: 0x01
Reset: 0x00
Property: -
This register contains the MSb of the data received by the USART receiver, as well as status bits reflecting the status
of the received data frame. The USART receiver is double-buffered, and this register always represents the data and
status bits for the oldest received frame. If the data and status bits for only one frame is present in the receive buffer,
this register contains that data.
The buffer shifts out the data either when RXDATAL or RXDATAH is read, depending on the configuration. The
register, which does not lead to data being shifted, must be read first to be able to read both bytes before shifting.
When the Character Size (CHSIZE) bits in the Control C (USARTn.CTRLC) register is configured to 9-bit (low byte
first), a read of RXDATAH shifts the receive buffer, or else, RXDATAL shifts the buffer.
Bit 7 6 5 4 3 2 1 0
RXCIF BUFOVF FERR PERR DATA[8]
Access R R R R R
Reset 0 0 0 0 0
Name: TXDATAL
Offset: 0x02
Reset: 0x00
Property: -
The data written to this register is automatically loaded into the TX Buffer and through to the dedicated shift register.
The shift register outputs each of the bits serially to the TXD pin.
When using a 9-bit frame size, the ninth bit (MSb) must be written to the Transmit Data Register High Byte
(USARTn.TXDATAH). In that case, the buffer shifts data either when the Transmit Data Register Low Byte
(USARTn.TXDATAL) or the Transmit Data Register High Byte (USARTn.TXDATAH) is written, depending on the
configuration. The register, which does not lead to data being shifted, must be written first to be able to write both
registers before shifting.
When the Character Size (CHSIZE) bit field in the Control C (USARTn.CTRLC) register is configured to 9-bit (low
byte first), a write of the Transmit Data Register High Byte shifts the transmit buffer. Otherwise, the Transmit Data
Register Low Byte shifts the buffer.
This register may only be written when the Data Register Empty Interrupt Flag (DREIF) in the Status
(USARTn.STATUS) register is set.
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: TXDATAH
Offset: 0x03
Reset: 0x00
Property: -
The data written to this register is automatically loaded into the TX Buffer and through to the dedicated shift register.
The shift register outputs each of the bits serially to the TXD pin.
When using a 9-bit frame size, the ninth bit (MSb) must be written to the Transmit Data Register High Byte
(USARTn.TXDATAH). In that case, the buffer shifts data either when the Transmit Data Register Low Byte
(USARTn.TXDATAL) or the Transmit Data Register High Byte (USARTn.TXDATAH) is written, depending on the
configuration. The register, which does not lead to data being shifted, must be written first to be able to write both
registers before shifting.
When the Character Size (CHSIZE) bit field in the Control C (USARTn.CTRLC) register is configured to 9-bit (low
byte first), a write of the Transmit Data Register High Byte shifts the transmit buffer. Otherwise, the Transmit Data
Register Low Byte shifts the buffer.
This register may only be written when the Data Register Empty Interrupt Flag (DREIF) in the Status
(USARTn.STATUS) register is set.
Bit 7 6 5 4 3 2 1 0
DATA[8]
Access R/W
Reset 0
Name: STATUS
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RXCIF TXCIF DREIF RXSIF ISFIF BDF WFB
Access R R/W R R/W R/W R/W W
Reset 0 0 1 0 0 0 0
24.5.6 Control A
Name: CTRLA
Offset: 0x05
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RXCIE TXCIE DREIE RXSIE LBME ABEIE RS485
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Value Description
0 RS-485 mode is disabled
1 RS-485 mode is enabled
24.5.7 Control B
Name: CTRLB
Offset: 0x06
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RXEN TXEN SFDEN ODME RXMODE[1:0] MPCM
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Name: CTRLC
Offset: 0x07
Reset: 0x03
Property: -
This register description is valid for all modes except the Host SPI mode. When the USART Communication Mode
(CMODE) bit field in this register is written to ‘MSPI’, see CTRLC - Host SPI mode for the correct description.
Bit 7 6 5 4 3 2 1 0
CMODE[1:0] PMODE[1:0] SBMODE CHSIZE[2:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 1 1
Name: CTRLC
Offset: 0x07
Reset: 0x00
Property: -
This register description is valid only when the USART is in Host SPI mode (CMODE written to MSPI). For other
CMODE values, see CTRLC - Normal Mode.
See 24.3.3.1.3. USART in Host SPI Mode for a full description of the Host SPI mode operation.
Bit 7 6 5 4 3 2 1 0
CMODE[1:0] UDORD UCPHA
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: BAUD
Offset: 0x08
Reset: 0x00
Property: -
The USARTn.BAUDL and USARTn.BAUDH register pair represents the 16-bit value, USARTn.BAUD. The low byte
[7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Ongoing transmissions of the transmitter and receiver will be corrupted if the baud rate is changed. Writing to this
register will trigger an immediate update of the baud rate prescaler. For more information on how to set the baud rate,
see Table 24-1.
Bit 15 14 13 12 11 10 9 8
BAUD[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
BAUD[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
24.5.11 Control D
Name: CTRLD
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ABW[1:0]
Access R/W R/W
Reset 0 0
Name: DBGCTRL
Offset: 0x0B
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: EVCTRL
Offset: 0x0C
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
IREI
Access R/W
Reset 0
Name: TXPLCTRL
Offset: 0x0D
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
TXPL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: RXPLCTRL
Offset: 0x0E
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RXPL[6:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
25.1 Features
• Full Duplex, Three-Wire Synchronous Data Transfer
• Host or Client Operation
• LSb First or MSb First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double-Speed (CK/2) Host SPI Mode
25.2 Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four
pins. It allows full-duplex communication between an AVR® device and peripheral devices or between several
microcontrollers. The SPI peripheral can be configured as either host or client. The host initiates and controls all data
transactions.
The interconnection between host and client devices with SPI is shown in the block diagram. The system consists of
two shift registers and a server clock generator. The SPI host initiates the communication cycle by pulling the desired
client’s Client Select (SS) signal low. The host and client prepare the data to be sent to their respective shift registers,
and the host generates the required clock pulses on the SCK line to exchange data. Data are always shifted from
host to client on the host output, client input (MOSI) line, and from client to host on the host input, client output
(MISO) line.
DATA DATA
Buffer Buffer
mode mode
Buffer Buffer
mode mode
DATA DATA
The SPI is built around an 8-bit shift register that will shift data out and in at the same time. The Transmit Data
register and the Receive Data register are not physical registers but are mapped to other registers when written or
read: Writing the Transmit Data (SPIn.DATA) register will write the shift register in Normal mode and the Transmit
Buffer register in Buffer mode. Reading the Receive Data (SPIn.DATA) register will read the Receive Data register in
Normal mode and the Receive Data Buffer in Buffer mode.
In Host mode, the SPI has a clock generator to generate the SCK clock. In Client mode, the received SCK clock is
synchronized and sampled to trigger the shifting of data in the shift register.
Pin Configuration
Signal Description
Host Mode Client Mode
MOSI Host Out Client In User defined(1) Input
MISO Host In Client Out Input User defined(1,2)
SCK Serial Clock User defined(1) Input
SS Client Select User defined(1) Input
Notes:
1. If the pin data direction is configured as output, the pin level is controlled by the SPI.
2. If the SPI is in Client mode and the MISO pin data direction is configured as output, the SS pin controls the
MISO pin output in the following way:
– If the SS pin is driven low, the MISO pin is controlled by the SPI
– If the SS pin is driven high, the MISO pin is tri-stated
When the SPI module is enabled, the pin data direction for the signals marked with “Input” in Table 25-1 is
overridden.
25.3.1 Initialization
Initialize the SPI to a basic functional state by following these steps:
1. Configure the SS pin in the port peripheral.
2. Select the SPI host/client operation by writing the Host/Client Select (MASTER) bit in the Control A
(SPIn.CTRLA) register.
3. In Host mode, select the clock speed by writing the Prescaler (PRESC) bits and the Clock Double (CLK2X) bit
in SPIn.CTRLA.
4. Optional: Select the Data Transfer mode by writing to the MODE bits in the Control B (SPIn.CTRLB) register.
5. Optional: Write the Data Order (DORD) bit in SPIn.CTRLA.
6. Optional: Set up the Buffer mode by writing the BUFEN and BUFWR bits in the Control B (SPIn.CTRLB)
register.
7. Optional: To disable the multi-host support in Host mode, write ‘1’ to the Client Select Disable (SSD) bit in
SPIn.CTRLB.
8. Enable the SPI by writing a ‘1’ to the ENABLE bit in SPIn.CTRLA.
25.3.2 Operation
25.3.2.1 Host Mode Operation
When the SPI is configured in Host mode, a write to the SPIn.DATA register will start a new transfer. The SPI host
can operate in two modes, Normal and Buffer, as explained below.
25.3.2.1.1 Normal Mode
In Normal mode, the system is single-buffered in the transmit direction and double-buffered in the receive direction.
This influences the data handling in the following ways:
1. New bytes to be sent cannot be written to the DATA (SPIn.DATA) register before the entire transfer has been
completed. A premature write will cause corruption of the transmitted data, and the Write Collision (WRCOL)
flag in SPIn.INTFLAGS will be set.
2. Received bytes are written to the Receive Data Buffer register immediately after the transmission is
completed.
3. The Receive Data Buffer register has to be read before the next transmission is completed, or the data will be
lost. This register is read by reading SPIn.DATA.
4. The Transmit Data Buffer and Receive Data Buffer registers are not used in Normal mode.
After a transfer has been completed, the Interrupt Flag (IF) will be set in the Interrupt Flags (SPIn.INTFLAGS)
register. This will cause the corresponding interrupt to be executed if this interrupt and the global interrupts are
enabled. Setting the Interrupt Enable (IE) bit in the Interrupt Control (SPIn.INTCTRL) register will enable the interrupt.
Note: If the device is in Host mode and it cannot be ensured that the SS pin will stay high between two
transmissions, the status of the Host (MASTER) bit in SPIn.CTRLA has to be checked before a new byte is written.
After the Host bit has been cleared by a low level on the SS line, it must be set by the application to re-enable the SPI
Host mode.
SCK
Write DATA
WRCOL
IF
Client Buffer Mode with Wait for Receive Bit Written to ‘0’
In Client mode, if the Buffer mode Wait for Receive (BUFWR) bit in SPIn.CTRLB is written to ‘0’, a dummy byte
will be sent before the transmission of user data starts. Figure 25-3 shows a transmission sequence with this
configuration. Notice how the value 0x45 is written to the Data (SPIn.DATA) register but never transmitted.
Figure 25-3. SPI Timing Diagram in Buffer Mode with BUFWR in SPIn.CTRLB Written to ‘0’
SS
SCK
Write DATA
DREIF
TXCIF
RXCIF
Client Buffer Mode with Wait for Receive Bit Written to ‘1’
In Client mode, if the Buffer mode Wait for Receive (BUFWR) bit in SPIn.CRTLB is written to ‘1’, the transmission
of user data starts as soon as the SS pin is driven low. Figure 25-4 shows a transmission sequence with this
configuration. Notice how the value 0x45 is written to the Data (SPIn.DATA) register but never transmitted.
Figure 25-4. SPI Timing Diagram in Buffer Mode with CTRLB.BUFWR Written to ‘1’
SS
SCK
Write DATA
DREIF
TXCIF
RXCIF
Note: In Client mode, the SPI state machine will be reset when the SS pin is driven high. If the SS pin is driven
high during a transmission, the SPI will stop sending and receiving data immediately and both data received and data
sent must be considered lost. As the SS pin is used to signal the start and end of a transfer, it is useful for achieving
packet/byte synchronization and keeping the Client bit counter synchronized with the host clock generator.
The SPI data transfer formats are shown below. Data bits are shifted out and latched in on opposite edges of the
SCK signal, ensuring sufficient time for data signals to stabilize.
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle.
Figure 25-5. SPI Data Transfer Modes
Cycle # 1 2 3 4 5 6 7 8
SPI Mode 0
SS
SCK
Sampling
MISO 1 2 3 4 5 6 7 8
MOSI 1 2 3 4 5 6 7 8
Cycle # 1 2 3 4 5 6 7 8
SPI Mode 1
SS
SCK
Sampling
MISO 1 2 3 4 5 6 7 8
MOSI 1 2 3 4 5 6 7 8
Cycle # 1 2 3 4 5 6 7 8
SPI Mode 2
SS
SCK
Sampling
MISO 1 2 3 4 5 6 7 8
MOSI 1 2 3 4 5 6 7 8
Cycle # 1 2 3 4 5 6 7 8
SPI Mode 3
SS
SCK
Sampling
MISO 1 2 3 4 5 6 7 8
MOSI 1 2 3 4 5 6 7 8
25.3.2.4 Events
The SPI can generate the following events:
25.3.2.5 Interrupts
Table 25-5. Available Interrupt Vectors and Sources
Conditions
Name Vector Description
Normal Mode Buffer Mode
• SSI: Client Select Trigger Interrupt
• IF: Interrupt Flag interrupt • DRE: Data Register Empty interrupt
SPIn SPI interrupt
• WRCOL: Write Collision interrupt • TXC: Transfer Complete interrupt
• RXC: Receive Complete interrupt
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
25.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DORD MASTER CLK2X PRESC[1:0] ENABLE
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
25.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
BUFEN BUFWR SSD MODE[1:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: INTCTRL
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RXCIE TXCIE DREIE SSIE IE
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: INTFLAGS
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
IF WRCOL
Access R/W R/W
Reset 0 0
Name: INTFLAGS
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RXCIF TXCIF DREIF SSIF BUFOVF
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
25.5.6 Data
Name: DATA
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
26.1 Features
• Bidirectional, Two-Wire Communication Interface
• Philips I2C Compatible1
– Standard mode
– Fast mode
– Fast mode plus
• System Management Bus (SMBus) 2.0 Compatible
– Support arbitration between Start/repeated Start and data bit
– Client arbitration allows support for the Address Resolution Protocol (ARP)
– Configurable SMBus Layer 1 time-outs in hardware
• Independent Host and Client Operation
– Single or multi-host bus operation with full arbitration support
• Flexible Client Address Match Hardware Operating in All Sleep Modes, Including Power-Down
– 7-bit and general call address recognition
– 10-bit addressing support in collaboration with software
– Support for address range masking or secondary address match
– Optional software address recognition (permissive mode) for an unlimited number of addresses
• Input Filter for Bus Noise Suppression
• Smart Mode Support
26.2 Overview
The Two-Wire Interface (TWI) is a bidirectional, two-wire communication interface (bus) with a Serial Data Line (SDA)
and a Serial Clock Line (SCL).
The TWI bus connects one or several client devices to one or several host devices. Any device connected to the
bus can act as a host, a client, or both. The host generates the SCL by using a Baud Rate Generator (BRG) and
initiates data transactions by addressing one client and telling whether it wants to transmit or receive data. The BRG
is capable of generating the Standard mode (Sm) and Fast mode (Fm, Fm+) bus frequencies from 100 kHz up to 1
MHz.
The TWI will detect Start and Stop conditions, bus collisions, and bus errors. Arbitration lost, errors, collision, and
clock hold are also detected and indicated in separate status flags available in both Host and Client modes.
The TWI supports multi-host bus operation and arbitration. An arbitration scheme handles the case where more
than one host tries to transmit data at the same time. The TWI also supports Smart mode, which can auto-trigger
operations and thus reduce software complexity. The TWI supports Quick Command mode, where the host can
address a client without exchanging data.
1 The I2C standard uses the terminology "host" and "client". The equivalent Microchip terminology used in this
document is "host" and "client" respectively.
RxDATA RxDATA ==
Figure 26-2. Basic TWI Transaction Diagram Topology for a 7-Bit Address Bus
SDA
Direction
Transaction
Bus Driver Special Bus Conditions
'1' '0'
'0' '1'
26.3.2.1 Initialization
If used, the following bits must be configured before enabling the TWI device:
• The SDA Hold Time (SDAHOLD) bit field from the Control A (TWIn.CTRLA) register
• The FM Plus Enable (FMPEN) bit from the Control A (TWIn.CTRLA) register
tHIGH tLOW
tOF tSP tR
SCL
tHD;STA tSU;DAT tHD;DAT tSU;STO tBUF
tSU;STA
SDA
S P S
1
fSCL = t [Hz]
LOW + tHIGH + tOF + tR
The SCL clock is designed to have a 50/50 duty cycle, where the low period of the duty cycle comprises of tOF and
tLOW. tHIGH will not start until a high state of SCL has been detected. The BAUD bit field in the TWIn.MBAUD register
and the SCL frequency are related by the following formula:
Equation 26-2. SCL Frequency
fCLK_PER
fSCL =
10 + 2 × BAUD + fCLK_PER × tR
Equation 26-3. BAUD
fCLK_PER fCLK_PER × tR
BAUD = − 5+
2 × fSCL 2
RESET
UNKNOWN
(0b00)
Stop Condition
1. Unknown: The bus state machine is active when the TWI host is enabled. After the TWI host has been
enabled, the bus state is Unknown. The bus state will also be set to Unknown after a system Reset is
performed or after the TWI host is disabled.
2. Idle: The bus state machine can be forced to enter the Idle state by writing 0x1 to the Bus State (BUSSTATE)
bit field. The bus state logic cannot be forced into any other state. If no state is set by the application
software, the bus state will become Idle when the first Stop condition is detected. If the Inactive Bus Time-Out
(TIMEOUT) bit field from the Host Control A (TWIn.MCTRLA) register is configured to a nonzero value, the
bus state will change to Idle on the occurrence of a time-out. When the bus is Idle, it is ready for a new
transaction.
3. Busy: If a Start condition, generated externally, is detected when the bus is Idle, the bus state becomes Busy.
The bus state changes back to Idle when a Stop condition is detected or when a time-out, if configured, is set.
4. Owner: If a Start condition is generated internally when the bus is Idle, the bus state becomes Owner. If the
complete transaction is performed without interference, the host issues a Stop condition, and the bus state
changes back to Idle. If a collision is detected, the arbitration is lost, and the bus state becomes Busy until a
Stop condition is detected.
P P
Sr A M3 Sr A Sr
M4 BUSY
M4 BUSY
P P
IF Interrupt flag raised
Mn Diagram cases
Case M1: Address Packet Transmit Complete - Direction Bit Set to ‘0’
If a client device responds to the address packet with an ACK, the Write Interrupt Flag (WIF) is set to ‘1’, the
Received Acknowledge (RXACK) flag is set to ‘0’, and the Clock Hold (CLKHOLD) flag is set to ‘1’. The WIF, RXACK
and CLKHOLD flags are located in the Host Status (TWIn.MSTATUS) register.
The clock hold is active at this point, forcing the SCL low. This will stretch the low period of the clock to slow down the
overall clock frequency, forcing delays required to process the data and preventing further activity on the bus.
The software can prepare to:
• Transmit data packets to the client
Case M2: Address Packet Transmit Complete - Direction Bit Set to ‘1’
If a client device responds to the address packet with an ACK, the RXACK flag is set to ‘0’, and the client can start
sending data to the host without any delays because the client owns the bus at this moment. The clock hold is active
at this point, forcing the SCL low.
The software can prepare to:
P S3 P S3 P S3
S4 A Sr S4 A Sr S4
S3 S ADDRESS R IF A IF S2 DATA A
P S3 P S3 P S3
Sn Diagram cases
26.3.3.1 SMBus
If the TWI is used in an SMBus environment, the Inactive Bus Time-Out (TIMEOUT) bit field from the Host Control
A (TWIn.MCTRLA) register must be configured. It is recommended to write to the Host Baud Rate (TWIn.MBAUD)
register before setting the time-out because it is dependent on the baud rate setting.
A frequency of 100 kHz can be used for the SMBus environment. For the Standard mode (Sm) and Fast mode (Fm),
the operating frequency has slew rate limited output, while for the Fast mode Plus (Fm+), it has x10 output drive
strength.
The TWI also allows for an SMBus compatible SDA hold time configured in the SDA Hold Time (SDAHOLD) bit field
from the Control A (TWIn.CTRLA) register.
26.3.3.2 Multi-Host
A host can start a bus transaction only if it has detected that the bus is in the Idle state. As the TWI bus is a multi-host
bus, more devices may try to initiate a transaction at the same time. This results in multiple hosts owning the bus
simultaneously. The TWI solves this problem by using an arbitration scheme where the host loses control of the bus
if it is not able to transmit a high-level data bit on the SDA and the Bus State (BUSSTATE) bit field from the Host
Status (TWIn.MSTATUS) register will be changed to Busy. The hosts that lose the arbitration must wait until the bus
becomes Idle before attempting to reacquire the bus ownership.
Both devices can issue a Start condition, but DEVICE1 loses arbitration when attempting to transmit a high-level (bit
5) while DEVICE2 is transmitting a low-level.
Figure 26-7. TWI Arbitration
DEVICE1 Loses arbitration
DEVICE1_SDA
DEVICE2_SDA
SDA
bit 7 bit 6 bit 5 bit 4
(wired-AND)
SCL
S
BUSY
SW Software interaction
26.3.4 Interrupts
Table 26-1. Available Interrupt Vectors and Sources
Host TWI Host interrupt • RIF: Read Interrupt Flag in TWIn.MSTATUS is set to ‘1’
• WIF: Write Interrupt Flag in TWIn.MSTATUS is set to ‘1’
When an interrupt condition occurs, the corresponding interrupt flag is set in the Host Status (TWIn.MSTATUS)
register or the Client Status (TWIn.SSTATUS) register.
When several interrupt request conditions are supported by an interrupt vector, the interrupt requests are ORed
together into one combined interrupt request to the interrupt controller. The user must read the interrupt flags from the
TWIn.MSTATUS register or the TWIn.SSTATUS register to determine which of the interrupt conditions are present.
26.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SDASETUP SDAHOLD[1:0] FMPEN
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: DBGCTRL
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: MCTRLA
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RIEN WIEN QCEN TIMEOUT[1:0] SMEN ENABLE
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Name: MCTRLB
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
FLUSH ACKACT MCMD[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 3 – FLUSH Flush
This bit clears the internal state of the host and the bus states changes to Idle. The TWI will transmit invalid data
if the Host Data (TWIn.MDATA) register is written before the Host Address (TWIn.MADDR) register. Writing to Host
Address (TWIn.MADDR) and Host Data (TWIn.MDATA) after a Flush will cause a transaction to start as soon as
hardware detects SCL bus free.
Writing a ‘1’ to this bit generates a strobe for one clock cycle, disabling the host and then re-enabling the host. Writing
a ‘0’ to this bit has no effect.
Notes:
1. The ACKACT bit and the MCMD bit field can be written at the same time.
2. For a host write operation, the TWI will wait for new data to be written to the Host Data (TWIn.MDATA) register.
Name: MSTATUS
Offset: 0x05
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RIF WIF CLKHOLD RXACK ARBLOST BUSERR BUSSTATE[1:0]
Access R/W R/W R/W R R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: MBAUD
Offset: 0x06
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
BAUD[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: MADDR
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: MDATA
Offset: 0x08
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: SCTRLA
Offset: 0x09
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DIEN APIEN PIEN PMEN SMEN ENABLE
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: SCTRLB
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ACKACT SCMD[1:0]
Access R/W R/W R/W
Reset 0 0 0
Note: 1. The ACKACT bit and the SCMD bit field can be written at the same time. The ACKACT will be updated
before the command is triggered.
Name: SSTATUS
Offset: 0x0B
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DIF APIF CLKHOLD RXACK COLL BUSERR DIR AP
Access R/W R/W R R R/W R/W R R
Reset 0 0 0 0 0 0 0 0
Bit 3 – COLL Collision
When this bit is read as ‘1’, it indicates that the client has not been able to do one of the following:
1. Transmit high bits on the SDA. The Data Interrupt Flag (DIF) will be set to ‘1’ at the end as a result of the
internal completion of an unsuccessful transaction.
2. Transmit the NACK bit. The collision occurs because the client address match already took place, and the
APIF flag is set to ‘1’ as a result.
Writing a ‘1’ to this bit will clear the COLL flag. The flag is automatically cleared if any Start condition (S/Sr) is
detected.
Note: The APIF and DIF flags can only generate interrupts whose handlers can be used to check for the collision.
The TWI bus error detector is part of the TWI Host circuitry. For the bus errors to be detected by the client, the TWI
Host must be enabled, and the main clock frequency must be at least four times the SCL frequency. The TWI Host
can be enabled by writing ‘1’ to the ENABLE bit in the TWIn.MCTRLA register.
Name: SADDR
Offset: 0x0C
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: SDATA
Offset: 0x0D
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: SADDRMASK
Offset: 0x0E
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ADDRMASK[6:0] ADDREN
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
27.1 Features
• CRC-16-CCITT
• Check of the Entire Flash Section, Application Code, and/or Boot Section
• Selectable NMI Trigger on Failure
• User-Configurable Check During Internal Reset Initialization
27.2 Overview
A Cyclic Redundancy Check (CRC) takes a data stream of bytes from the NVM (either the entire Flash, only the Boot
section, or both the Boot section and the application code section) and generates a checksum. The CRC peripheral
(CRCSCAN) can be used to detect errors in the program memory.
The last location in the section to check has to contain the correct pre-calculated 16-bit checksum for comparison.
If the checksum calculated by the CRCSCAN and the pre-calculated checksums match, a status bit is set. If they
do not match, the Status register (CRCSCAN.STATUS) will indicate that it failed. The user can choose to let the
CRCSCAN generate a Non-Maskable Interrupt (NMI) if the checksums do not match.
An n-bit CRC applied to a data block of arbitrary length will detect any single alteration (error burst) up to n bits in
length. For longer error bursts a fraction 1-2-n will be detected.
The CRC generator supports CRC-16-CCITT.
Polynomial:
• CRC-16-CCITT: x16 + x12 + x5 + 1
The CRC reads byte-by-byte the content of the section(s) it is set up to check, starting with byte 0, and generates a
new checksum per byte. The byte is sent through a shift register as depicted below, starting with the Most Significant
bit. If the last bytes in the section contain the correct checksum, the CRC will pass. See 27.3.2.1. Checksum for how
to place the checksum. The initial value of the Checksum register is 0xFFFF.
Figure 27-1. CRC Implementation Description
data
15
x x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0
Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D
Source
CTRLB
CRC BUSY
CTRLA
Enable, calculation
Reset STATUS
CRC OK
CHECKSUM
NMI Req
27.3.1 Initialization
To enable a CRC in software (or via the debugger):
1. Write the Source (SRC) bit field of the Control B register (CRCSCAN.CTRLB) to select the desired mode and
source settings.
2. Enable the CRCSCAN by writing a ‘1’ to the ENABLE bit in the Control A register (CRCSCAN.CTRLA).
3. The CRC will start after three cycles. The CPU will continue executing during these three cycles.
The CRCSCAN can be configured to perform a code memory scan before the device leaves Reset. If this check fails,
the CPU is not allowed to start normal code execution. This feature is enabled and controlled by the CRCSRC field in
FUSE.SYSCFG0, see the Fuses chapter for more information.
If this feature is enabled, a successful CRC check will have the following outcome:
• Normal code execution starts
• The ENABLE bit in CRCSCAN.CTRLA will be ‘1’
• The SRC bit field in CRCSCAN.CTRLB will reflect the checked section(s)
• The OK flag in CRCSCAN.STATUS will be ‘1’
If this feature is enabled, a non-successful CRC check will have the following outcome:
• Normal code execution does not start, the CPU will hang executing no code
• The ENABLE bit in CRCSCAN.CTRLA will be ‘1’
• The SRC bit field in CRCSCAN.CTRLB will reflect the checked section(s)
• The OK flag in CRCSCAN.STATUS will be ‘0’
• This condition may be observed using the debug interface
27.3.2 Operation
When the CRC is operating in Priority mode, the CRC peripheral has priority access to the Flash and will stall the
CPU until completed.
In Priority mode the CRC fetches a new word (16-bit) on every third main clock cycle, or when the CRC peripheral is
configured to do a scan from start-up.
27.3.2.1 Checksum
The pre-calculated checksum must be present in the last location of the section to be checked. If the BOOT section
is to be checked, the checksum must be saved in the last bytes of the BOOT section, and similarly for APPLICATION
and the entire Flash. Table 27-1 shows explicitly how the checksum must be stored for the different sections. Also,
see the CRCSCAN.CTRLB register description for how to configure which section to check and the device fuse
description for how to configure the BOOTEND and APPEND fuses.
Table 27-1. Placement of the Pre-Calculated Checksum in Flash
27.3.3 Interrupts
Table 27-2. Available Interrupt Vectors and Sources
When the interrupt condition occurs the OK flag in the Status (CRCSCAN.STATUS) register is cleared to ‘0’.
A Non-Maskable Interrupt (NMI) is enabled by writing a ‘1’ to the respective Enable (NMIEN) bit in the Control A
(CRCSCAN.CTRLA) register, but can only be disabled with a System Reset. An NMI is generated when the OK
flag in the CRCSCAN.STATUS register is cleared, and the NMIEN bit is ‘1’. The NMI request remains active until a
System Reset and cannot be disabled.
An NMI can be triggered even if interrupts are not globally enabled.
– Writing the OK bit to ‘0’ can trigger a Non-Maskable Interrupt (NMI) if the NMIEN bit in CRCSCAN.CTRLA
is ‘1’. If an NMI has been triggered, no writes to the CRCSCAN are allowed.
– Writing the OK bit to ‘1’ will make the OK bit read as ‘1’ when the BUSY bit in CRCSCAN.STATUS is ‘0’.
Writes to CRCSCAN.CTRLA and CRCSCAN.CTRLB from the debugger are treated in the same way as writes from
the CPU.
27.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RESET NMIEN ENABLE
Access R/W R/W R/W
Reset 0 0 0
27.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
The CRCSCAN.CTRLB register contains the mode and source settings for the CRC. It is not writable when the CRC
is busy, or when an NMI has been triggered.
Bit 7 6 5 4 3 2 1 0
MODE[1:0] SRC[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
27.5.3 Status
Name: STATUS
Offset: 0x02
Reset: 0x02
Property: -
Bit 7 6 5 4 3 2 1 0
OK BUSY
Access R R
Reset 1 0
Bit 1 – OK CRC OK
When this bit is read as ‘1’, the previous CRC completed successfully. The bit is set to ‘1’ by default before a CRC
scan is run. The bit is not valid unless BUSY is ‘0’.
28.1 Features
• Glue Logic for General Purpose PCB Design
• Four Programmable Look-Up Tables (LUTs)
• Combinatorial Logic Functions: Any Logic Expression Which Is a Function of up to Three Inputs.
• Sequencer Logic Functions:
– Gated D flip-flop
– JK flip-flop
– Gated D latch
– RS latch
• Flexible LUT Input Selection:
– I/Os
– Events
– Subsequent LUT output
– Internal peripherals such as:
• Analog comparator
• Timers/Counters
• USART
• SPI
• Clocked by a System Clock or Other Peripherals
• Output Can Be Connected to I/O Pins or an Event System
• Optional Synchronizer, Filter, or Edge Detector Available on Each LUT Output
• Optional Interrupt Generation from Each LUT Output:
– Rising edge
– Falling edge
– Both edges
28.2 Overview
The Configurable Custom Logic (CCL) is a programmable logic peripheral which can be connected to the device
pins, to events, or to other internal peripherals. The CCL can serve as ‘glue logic’ between the device peripherals
and external devices. The CCL can eliminate the need for external logic components, and can also help the designer
to overcome real-time constraints by combining Core Independent Peripherals (CIPs) to handle the most time-critical
parts of the application independent of the CPU.
The CCL peripheral provides a number of Look-up Tables (LUTs). Each LUT consists of three inputs, a truth table, a
synchronizer/filter, and an edge detector. Each LUT can generate an output as a user programmable logic expression
with three inputs. The output is generated from the inputs using the combinatorial logic and can be filtered to remove
spikes. The CCL can be configured to generate an interrupt request on changes in the LUT outputs.
Neighboring LUTs can be combined to perform specific operations. A sequencer can be used for generating complex
waveforms.
Internal SEQSEL
LUTn-TRUTHSEL[2:0] FILTSEL EDGEDET
Events
I/O
Peripherals
CLKSRC TRUTH Filter/ Edge
LUTn-OUT
Synch Detector
Clock Sources CLK_LUTn
Sequencer
LUTn-TRUTHSEL[2]
Internal
LUTn+1-TRUTHSEL[2:0] FILTSEL EDGEDET
Events
I/O
Peripherals
CLKSRC TRUTH Filter/ Edge LUTn+1-OUT
Synch Detector
Clock Sources CLK_LUTn+1
LUTn+1-TRUTHSEL[2]
Refer to the I/O Multiplexing and Considerations section for details on the pin mapping for this peripheral. One signal
can be mapped to several pins.
...........continued
Value Input Source INSEL0[3:0] INSEL1[3:0] INSEL2[3:0]
0x08(1) USARTn USART0 TXD USART1 TXD -
0x09(2) SPI SPI0 MOSI SPI0 MOSI SPI0 SCK
0x0A TCA0 WO0 WO1 WO2
0x0B - -
0x0C TCB TCB0 WO TCB1 WO -
Notes:
1. USART connections to the CCL work only in asynchronous/synchronous USART host mode.
2. SPI connections to the CCL work only in host SPI mode.
28.3.1 Operation
28.3.1.1 Enable-Protected Configuration
The configuration of the LUTs and sequencers is enable-protected, meaning that they can only be configured when
the corresponding even LUT is disabled (ENABLE = ‘0’ in the LUT n Control A (CCL.LUTnCTRLA) register). This is a
mechanism to suppress the undesired output from the CCL under (re-)configuration.
The following bits and registers are enable-protected:
• Sequencer Selection (SEQSEL) in the Sequencer Control n (CCL.SEQCTRLn) registers
• LUT n Control x (CCL.LUTnCTRLx) registers, except the ENABLE bit in the CCL.LUTnCTRLA register
• TRUTHn (CCL.TRUTHn) registers
The enable-protected bits in the CCL.LUTnCTRLx registers can be written at the same time as ENABLE in
CCL.LUTnCTRLA is written to ‘1’, but not at the same time as ENABLE is written to ‘0’.
The enable protection is denoted by the enable-protected property in the register description.
TRUTHn[0]
TRUTHn[1]
TRUTHn[2]
TRUTHn[3]
OUT
TRUTHn[4]
TRUTHn[5]
TRUTHn[6]
TRUTHn[7]
LUTn-TRUTHSEL[2:0]
Configure the truth table inputs (LUTn-TRUTHSEL[2:0]) by writing the Input Source Selection bit fields in the LUT
Control registers:
• INSEL0 in CCL.LUTnCTRLB
• INSEL1 in CCL.LUTnCTRLB
• INSEL2 in CCL.LUTnCTRLC
Each combination of the input bits (LUTn-TRUTHSEL[2:0]) corresponds to one bit in the CCL.TRUTHn register, as
shown in the table below:
Table 28-3. Truth Table of an LUT
Important: Consider the unused inputs turned off (tied low) when logic functions are created.
Input Overview
The inputs can be individually:
• OFF
• Driven by peripherals
• Driven by internal events from the Event System
• Driven by I/O pin inputs
• Driven by other LUTs
Even LUT
Sequencer
Odd LUT
When selected (INSELy = FEEDBACK in LUTnCTRLx), the sequencer (SEQ) output is used as input for the
corresponding LUTs.
LUT0 SEQ0
LUT1
LUT2 SEQ1
LUT3
Peripherals
The different peripherals on the three input lines of each LUT are selected by writing to the Input Select (INSEL) bits
in the LUT Control (LUTnCTRLB and LUTnCTRLC) registers.
28.3.1.5 Filter
By default, the LUT output is a combinational function of the LUT inputs. This may cause some short glitches when
the inputs change the value. These glitches can be removed by clocking through filters if demanded by application
needs.
The Filter Selection (FILTSEL) bits in the LUT n Control A (CCL.LUTnCTRLA) registers define the digital filter
options.
When FILTSEL = SYNCH, the output is synchronized with CLK_LUTn. The output will be delayed by two positive
CLK_LUTn edges.
When FILTSEL = FILTER, only the input that is persistent for more than two positive CLK_LUTn edges will pass
through the gated flip-flop to the output. The output will be delayed by four positive CLK_LUTn edges.
One clock cycle later, after the corresponding LUT is disabled, all internal filter logic is cleared.
Figure 28-5. Filter
FILTSEL
DISABLE
Input
SYNCH
OUT
EN FILTER
D Q D Q D Q D Q
R R R R
CLK_LUTn
CLR
EDGEDET
CLK_LUTn
Odd LUT
R G D OUT
1 X X Clear
0 1 1 Set
0 1 0 Clear
0 0 X Hold state (no change)
JK Flip-Flop (JK)
The J input is driven by the even LUT output, and the K input is driven by the odd LUT output.
Figure 28-8. JK Flip-Flop
Even LUT
CLK_LUTn
Odd LUT
R J K OUT
1 X X Clear
0 0 0 Hold state (no change)
0 0 1 Clear
0 1 0 Set
0 1 1 Toggle
Odd LUT G
G D OUT
0 X Hold state (no change)
1 0 Clear
1 1 Set
RS Latch (RS)
The S input is driven by the even LUT output, and the R input is driven by the odd LUT output.
Figure 28-10. RS Latch
Odd LUT R
S R OUT
0 0 Hold state (no change)
0 1 Clear
1 0 Set
1 1 Forbidden state
Edge Filter
Detector
IN[2]
OSCULP1K
OSCULP32K CLK_MUX_OUT
OSC20M
CLK_PER
CLKSRC
even LUT
Sequencer
Edge Filter
Detector
IN[2]
OSCULP1K
OSCULP32K CLK_MUX_OUT
OSC20M
CLK_PER
CLKSRC
odd LUT
When the Clock Source (CLKSRC) bit is written to 0x1, LUTn-TRUTHSEL[2] is used to clock the corresponding filter
and edge detector (CLK_LUTn). The sequencer is clocked by the CLK_LUTn of the even LUT in the pair. When
CLKSRC is written to 0x1, LUTn-TRUTHSEL[2] is treated as OFF (low) in the TRUTH table.
The CCL peripheral must be disabled while changing the clock source to avoid undefined outputs from the peripheral.
28.3.2 Interrupts
Table 28-8. Available Interrupt Vectors and Sources
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
When several interrupt request conditions are supported by an interrupt vector, the interrupt requests are ORed
together into one combined interrupt request to the interrupt controller. The user must read the peripheral’s
INTFLAGS register to determine which of the interrupt conditions are present.
28.3.3 Events
The CCL can generate the events shown in the table below.
Table 28-9. Event Generators in the CCL
Generator Name Description Event Type Generating Clock Domain Length of Event
Peripheral Event
CCL LUTn LUT output level Level Asynchronous Depends on the CCL
configuration
The CCL has the event users below for detecting and acting upon input events.
Table 28-10. Event Users in the CCL
The event signals are passed directly to the LUTs without synchronization or input detection logic.
Two event users are available for each LUT. They can be selected as LUTn inputs by writing to the INSELn bit groups
in the LUT n Control B and Control C (CCL.LUTnCTRLB or LUTnCTRLC) registers.
Refer to the EVSYS - Event System section for more details regarding the event types and the EVSYS configuration.
28.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUNSTDBY ENABLE
Access R/W R/W
Reset 0 0
Bit 0 – ENABLE Enable
Value Description
0 The peripheral is disabled
1 The peripheral is enabled
Name: SEQCTRL0
Offset: 0x01
Reset: 0x00
Property: Enable-Protected
Bit 7 6 5 4 3 2 1 0
SEQSEL0[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: SEQCTRL1
Offset: 0x02
Reset: 0x00
Property: Enable-Protected
Bit 7 6 5 4 3 2 1 0
SEQSEL1[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTCTRL0
Offset: 0x05
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
INTMODE3[1:0] INTMODE2[1:0] INTMODE1[1:0] INTMODE0[1:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTFLAGS
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
INT3 INT2 INT1 INT0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: LUTnCTRLA
Offset: 0x08 + n*0x04 [n=0..3]
Reset: 0x00
Property: Enable-Protected
Bit 7 6 5 4 3 2 1 0
EDGEDET OUTEN FILTSEL[1:0] CLKSRC[2:0] ENABLE
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: LUTnCTRLB
Offset: 0x09 + n*0x04 [n=0..3]
Reset: 0x00
Property: Enable-Protected
Notes:
1. SPI connections to the CCL work in Host SPI mode only.
2. USART connections to the CCL work only when the USART is in one of the following modes:
– Asynchronous USART
– Synchronous USART host
Bit 7 6 5 4 3 2 1 0
INSEL1[3:0] INSEL0[3:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: LUTnCTRLC
Offset: 0x0A + n*0x04 [n=0..3]
Reset: 0x00
Property: Enable-Protected
Bit 7 6 5 4 3 2 1 0
INSEL2[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
28.5.9 TRUTHn
Name: TRUTHn
Offset: 0x0B + n*0x04 [n=0..3]
Reset: 0x00
Property: Enable-Protected
Bit 7 6 5 4 3 2 1 0
TRUTHn[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
29.1 Features
• Selectable Response Time
• Selectable Hysteresis
• Analog Comparator Output Available on Pin
• Comparator Output Inversion Available
• Flexible Input Selection:
– Up to four Positive pins
– Up to three Negative pins
– Internal reference voltage generator (DACREF)
• Interrupt Generation on:
– Rising edge
– Falling edge
– Both edges
• Event Generation:
– Comparator output
29.2 Overview
The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on
this comparison. The AC can be configured to generate interrupt requests and/or events upon several different
combinations of input change.
The dynamic behavior of the AC can be adjusted by a hysteresis feature. The hysteresis can be customized to
optimize the operation for each application.
The input selection includes analog port pins and internally generated inputs. The analog comparator output state
can also be the output on a pin for use by external devices.
An AC has one positive input and one negative input. The digital output from the comparator is '1' when the
difference between the positive and the negative input voltage is positive, and '0' otherwise.
AINP0
.
.
. +
AINPn CMP
AC Controller
logic
(Int. Req)
AINN0 . OUT
..
AINNn -
Hysteresis
Event out
Enable
Invert
Voltage
VREF
divider
CTRLA
DACREF MUXCTRLA
29.3.1 Initialization
For a basic operation, follow these steps:
• Configure the desired input pins in the port peripheral.
• Select the positive and negative input sources by writing the Positive and Negative Input MUX Selection bit
fields (MUXPOS and MUXNEG) in the MUX Control A register (ACn.MUXCTRLA).
• Optional: Enable the output to pin by writing a '1' to the Output Pad Enable bit (OUTEN) in the Control A register
(ACn.CTRLA).
• Enable the AC by writing a '1' to the ENABLE bit in ACn.CTRLA.
During the start-up time after enabling the AC, the output of the AC may be invalid.
The start-up time of the AC by itself is at most 2.5 µs. If an internal reference is used, the reference start-up time is
normally longer than the AC start-up time.
To avoid the pin being tri-stated when the AC is disabled, the OUT pin must be configured as output in PORTx.DIR.
29.3.2 Operation
29.3.3 Events
The AC can generate the events described in the table below.
Table 29-1. Event Generators in AC
Generator Name
Description Event Type Generating Clock Domain Length of Event
Peripheral Event
ACn OUT Comparator output level. Level Asynchronous Given by AC output level
29.3.4 Interrupts
Table 29-2. Available Interrupt Vectors and Sources
When an interrupt condition occurs, the corresponding Interrupt flag is set in the Status register (ACn.STATUS).
An interrupt source is enabled or disabled by writing to the corresponding bit in the peripheral's Interrupt Control
register (ACn.INTCTRL).
An interrupt request is generated when the corresponding interrupt source is enabled and the Interrupt flag is set.
The interrupt request remains active until the Interrupt flag is cleared. See the ACn.STATUS register description for
details on how to clear the Interrupt flags.
29.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUNSTDBY OUTEN INTMODE[1:0] LPMODE HYSMODE[1:0] ENABLE
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 0 – ENABLE Enable AC
Writing this bit to '1' enables the AC.
Name: MUXCTRLA
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
INVERT MUXPOS[1:0] MUXNEG[1:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: DACREF
Offset: 0x04
Reset: 0xFF
Property: R/W
Bit 7 6 5 4 3 2 1 0
DACREF[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Name: INTCTRL
Offset: 0x06
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CMP
Access R/W
Reset 0
29.5.5 Status
Name: STATUS
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
STATE CMP
Access R R/W
Reset 0 0
30.1 Features
• 12-Bit Resolution
– Up to 17 bits with oversampling
• Conversion Rate Up to 375 ksps at 12-bit Resolution
• Up to 15 Inputs
• Differential and Single-Ended Conversion
• Programmable Gain Amplifier (PGA) from 1x to 16x
• Input Voltage Range from -100 mV to VDD+100 mV
• Multiple Internal ADC Reference Voltages
– VDD
– 1.024V
– 2.048V
– 2.500V
– 4.096V
• External Reference Input
• Single and Free-Running Conversions
• Series and Burst Accumulation Modes
• Accumulation of Up to 1024 Conversions
• Left or Right Adjusted Result
• Interrupts on Conversion Complete
• Optional Event Triggered Conversion
• Configurable Window Comparator
30.2 Overview
The Analog-to-Digital Converter (ADC) peripheral is a 12-bit differential and single-ended ADC, with a Programmable
Gain Amplifier (PGA), and a conversion rate up to 375 ksps at 12-bit resolution. The ADC is connected to an analog
input multiplexer for selection between multiple single-ended or differential inputs. In single-ended conversions, the
ADC measures the voltage between the selected input and 0V (GND). In differential conversions, the ADC measures
the voltage between two selected inputs. The ADC inputs can be either internal (for example, a voltage reference) or
external analog input pins.
An ADC conversion can be started by software, or by using the Event System (EVSYS) to route an event from
other peripherals. This makes it possible to sample input signals periodically, trigger an ADC conversion on a special
condition, and also trigger ADC conversions in Standby sleep mode. A digital window compare feature is available for
monitoring the input signal and can be configured to trigger an interrupt if the sample is under or over a user-defined
threshold, or inside or outside a user-defined window, with minimum software intervention required.
The ADC input signal is fed through a sample-and-hold circuit that ensures the input voltage to the ADC is held at a
constant level during the conversion.
The ADC supports sampling in bursts where a configurable number of samples are accumulated into a single ADC
result (Sample Accumulation).
The ADC reference voltage can be either internal or supplied from the external analog reference pin (VREFA).
SAMPRDY
SAMPLE (Int. Req.)
WINLT WCMP
AIN0
(Int. Req.)
AIN1 WINHT
.. VINP
.
AINn >
<
Internal Sources
PGA ADC RESRDY
ACC RESULT (Int. Req.)
AIN0
AIN1
Convert
.
Enable
.. VINN Diff
AINn
Gain Accumulate
Internal Sources RESOVR
Enable (Int. Req.)
SAMPOVR
MUXNEG Control Logic (Int. Req.)
TRIGOVR
(Int. Req.)
30.3.1 Definitions
• Conversion: The operation where analog values on the selected ADC inputs are transformed into a digital
representation.
• Sample: The value placed in the Sample (ADCn.SAMPLE) register, that is, the outcome of a conversion
operation.
• Result: The value placed in the Result (ADCn.RESULT) register. Depending on the ADC configuration, this
value is a single sample or the sum of multiple accumulated samples.
5. Optional: Configure the number of samples to be accumulated by writing the Sample Accumulation Number
Select (SAMPNUM) bit field in the Control F (ADCn.CTRLF) register.
6. Optional: Enable the Free-Running mode by writing a ‘1’ to the Free-Running (FREERUN) bit in the Control F
register.
7. Configure a positive input by writing to the MUXPOS bit field in the Positive Input Multiplexer
(ADCn.MUXPOS) register.
8. Optional: Configure a negative input by writing to the MUXNEG bit field in the Negative Input Multiplexer
(ADCn.MUXNEG) register.
9. Optional: Select Differential ADC conversion by writing a ‘1’ to the Differential (DIFF) bit in the Command
(ADCn.COMMAND) register.
10. Configure the mode of operation for the ADC by writing to the MODE bit field in the Command register.
11. Configure how an ADC conversion will start by writing to the START bit field in the Command register. If the
IMMEDIATE command is written, a conversion will start immediately.
12. Wait until the Result Ready (RESRDY) bit in the Interrupt Flags (ADCn.INTFLAGS) register is ‘1’ before
reading the updated Result (ADCn.RESULT) register.
30.3.3 Operation
Conversions Per
Operation Mode COMMAND Mode Accumulation Type RESULT Update
Trigger
Single 8-bit 0
1 N/A Every conversion
Single 12-bit 1
Series Accumulation 2 Full After SAMPNUM
1
Series Accumulation with Scaling 3 Scaled conversions
An ongoing conversion can be aborted by writing the STOP value to the START bit field in the Command register,
and a new conversion can be started immediately. Triggering a new conversion before the ongoing conversion has
finished will set the Trigger Overrun Interrupt (TRIGOVR) flag in the Interrupt Flags (ADCn.INTFLAGS) register, and
the trigger will be ignored.
The Result Ready and Sample Ready (RESRDY and SAMPRDY) interrupt flags in the Interrupt Flags register show
if a conversion or accumulation has finished. These flags also trigger the corresponding interrupts if enabled in the
Interrupt Control (ADCn.INTCTRL) register.
VINP × Gain
Single‐Ended 8‐bit conversion = × 256 ∈ 0, 255
VREF
Where VINP and VINN are the positive and negative inputs to the ADC, and VREF is the selected voltage reference.
The gain is between 1x and 16x as configured in the PGA, and 1x if the PGA is not in use.
The ADC has two output registers, the Sample (ADCn.SAMPLE) and Result (ADCn.RESULT) registers. The 16-bit
Sample register will always be updated with the latest ADC conversion output (one sample). All accumulation modes
will accumulate samples in an internal sample accumulator, configured by the Sample Accumulation Number Select
(SAMPNUM) bit field in the Control F (ADCn.CTRLF) register. The sample accumulator is sufficiently wide to avoid
overflow for all supported accumulation configurations, and the accumulated result is automatically transferred to the
32-bit Result register at the end of a Burst or Series mode accumulation. In single conversion modes, the Result
register will be updated with the latest sample, identical to the Sample register.
Operating modes with scaling can be selected to limit the accumulated result to 16 bits of resolution if more than 16
samples are accumulated. Scaling is always applied after accumulating the last sample in Burst or Series modes and
is carried out by right shifting the accumulated result by SAMPNUM-4 bits.
The Left Adjust (LEFTADJ) bit in the Control F register enables left shift of the output data in the modes where this is
supported. If enabled, this will left shift the output from both the Result and the Sample registers.
The data format for a sample in Single-Ended mode is an unsigned number, where 0x0000 represents zero, and
0x0FFF represents the largest number (full scale). If the analog input is higher than the reference level of the ADC,
the 12-bit ADC output will be equal the maximum value of 0x0FFF. Likewise, if the input is below 0V, the ADC output
will be 0x0000. For Differential mode, the data format is two's complement, with sign extension.
The following tables show the Result register output formats for single-ended and differential conversions, by mode of
operation and left adjustment.
Table 30-2. RESULT Register - Single-Ended Mode
Notes:
1. Left adjust is not available in 8-bit mode or accumulation modes without scaling.
2. If SAMPNUM < 4, the result is left-shifted 4-SAMPNUM bits such that bit 15 is the MSb.
Table 30-3. RESULT Register - Differential Mode
Notes:
1. Left adjust is not available in 8-bit mode or accumulation modes without scaling.
2. If SAMPNUM < 4, the result is left-shifted 4-SAMPNUM bits such that bit 15 is the MSb.
The following table shows the Sample register output formats by mode of operation, left adjustment, and Differential
or Single-Ended conversions.
Table 30-4. SAMPLE Register
#include <math.h>
#define CLK_PER 3333333ul // 20 MHz/6 = 3.333333 MHz
#define TIMEBASE_VALUE ((uint8_t) ceil(CLK_PER*0.000001))
The reference voltage for the ADC (VREF) controls the conversion range of the ADC. VREF can be selected by writing
the Reference Selection (REFSEL) bit field in the Control C (ADCn.CTRLC) register. Except for VDD, the internal
reference voltages are generated from an internal band gap reference. VDD must be at least 0.5V higher than the
selected internal reference voltage.
The input and reference selections are not buffered. Changing any of these while a conversion is ongoing will corrupt
the output. To safely change input or reference when using Free-Running mode, disable Free-Running mode, and
wait for the conversion to complete before making any changes. Enable Free-Running mode again before starting the
next conversion.
After switching input or reference, the ADC requires time to settle. Refer to the Electrical Characteristics section for
further details.
IIH
AINn
RIN
CIN
IIL
VDD/2
If a source with high impedance is used, the sampling time can be increased. The required sample time will depend
on how long the source needs to charge the CIN capacitor and can be configured using the Sample Duration
(SAMPDUR) bit field in the Control E (ADCn.CTRLE) register.
Note:
1. If CLK_PER < 2 MHz, the ADC initialization time is 20 CLK_PER cycles.
Example: Selecting Tempsense as input and using VDD as the reference will give a 35 µs initialization time. Using the
Tempsense with the 1.024V internal reference will result in a 60 µs initialization time.
The ADC can be put in Low-Latency mode by writing a ‘1’ to the LOWLAT bit in the Control A (ADCn.CTRLA)
register. This will keep the configured modules continuously enabled, effectively removing all initialization time at
the start of a conversion. The initialization time is still needed when enabling the ADC for the first time, and if
reconfiguring the ADC to use an input or reference that requires initialization, as shown in the table above. The ADC
Busy (ADCBUSY) bit in the Status (ADCn.STATUS) register can be used to check if initialization is ongoing.
The sampling period of the input to the ADC is configured through the Sample Duration (SAMPDUR) bit field in the
Control E (ADCn.CTRLE) register as (SAMPDUR + ½) CLK_ADC cycles. The input signal characteristics affect how
long the sampling period has to be.
When the PGA is used, it is sampling continuously and will only be in the Hold state when the ADC is sampling the
PGA. This ADC PGA Sample Duration (ADCPGASAMPDUR) depends on fCLK_ADC and is configured in the PGA
Control (ADCn.PGACTRL) register. SAMPDUR will still configure the minimum sampling period of the input to the
PGA as (SAMPDUR + 1) CLK_ADC cycles. In Burst mode, SAMPDUR must be ≥12, limited by the length of the
Conversion state.
The Series and Burst Accumulation modes can be used for oversampling to achieve up to 5 bit higher resolution,
given suitable input signal and sampling frequency. Increasing the resolution by n bits can be achieved by
accumulating 4n samples and dividing the accumulated result by 2n. The Sample Accumulation Number (SAMPNUM)
bit field in the Control F (ADCn.CTRLF) register can be configured for up to 45 = 1024 samples, resulting in up to
17-bit resolution.
The two tables below show the calculated conversion rates (fconv) for a subset of the possible combinations of
fCLK_ADC and sample durations. For more details, see the relevant timing diagrams on the following pages.
Table 30-6. Example Conversion Rates (fconv) for fCLK_ADC = 5 MHz and ADCPGASAMPDUR = 20
SAMPDUR PGA fconv(1) Single 8-bit fconv(1) Single 12-bit fconv Burst
[sps] [sps] Accumulation [sps]
2 OFF 384615 294118 312500
12 OFF 217391 185185 192308
48 OFF 84746 79365 80645
255 OFF 18797 18519 18587
2 ON 149254 133333 N/A
12 ON 114943 105263 147059
48 ON 62893 59880 71429
255 ON 17452 17212 18051
Table 30-7. Example Conversion Rates (fconv) for fCLK_ADC = 333 kHz and ADCPGASAMPDUR = 6
SAMPDUR PGA fconv(1) Single 8-bit fconv(1) Single 12-bit fconv Burst
[sps] [sps] Accumulation [sps]
2 OFF 25641 19608 20833
12 OFF 14493 12346 12821
48 OFF 5650 5291 5376
255 OFF 1253 1235 1239
2 ON 17094 14184 N/A
12 ON 11299 9950 16667
48 ON 5089 4796 5952
255 ON 1223 1206 1267
Note:
1. Conversion rates with the Free-Running (FREERUN) bit set to ‘1’ in the Control F (ADCn.CTRLF) register; a
new conversion will be started immediately after the results are available in the ADC.
1 ... 13
CLK_ADC
Enable
Trigger
Initialization SAMPDUR
(0–60 μs) (0–255 CLK_ADC cycles)
Notes:
1. In Single 8-bit mode, the length of the Conversion state is nine CLK_ADC cycles. In all other modes, it is
thirteen cycles.
2. If the Low Latency (LOWLAT) bit is set to ‘1’ in the Control A (ADCn.CTRLA) register, the analog modules in
the ADC will not turn OFF at the end of the conversion, eliminating the initialization time when triggering the
following conversion.
3. The time from the conversion has finished to the outputs are available in the registers is 0.5 CLK_ADC cycles
followed by 1 CLK_MAIN cycle. With minimum prescaling, this sums up to 1 CLK_ADC cycle.
The total conversion time (tconv) for a single result, in μs, is calculated by:
A new conversion starts immediately after a result is available in the Result (ADCn.RESULT) register if the Free-
Running (FREERUN) bit is set to ‘1’ in the Control F (ADCn.CTRLF) register. The Free-Running conversion rate
(fconv) is calculated by:
fCLK_ADC
fconv (12‐bit) =
SAMPDUR+15
fCLK_ADC
fconv (8‐bit) =
SAMPDUR+11
1 ... 13 1 ... 13
CLK_ADC
Enable
Trigger
ADC State Off Input 1 Sampling Conversion 1 Off (1) Input Sampling n Conversion n Off (1)
Notes:
1. If the Low Latency (LOWLAT) bit is set to ‘1’ in the Control A (ADCn.CTRLA) register, the analog modules in
the ADC will not turn OFF at the end of the conversion, eliminating the initialization time when triggering the
following conversion.
2. The time from the conversion has finished to the outputs are available in the registers is 0.5 CLK_ADC cycles
followed by 1 CLK_MAIN cycle. The last conversion and accumulation require an additional CLK_MAIN cycle.
With minimum prescaling, this sums up to 1.5 CLK_ADC cycles before the final outputs are available.
The number of samples to accumulate is set by the Sample Number (SAMPNUM) bit field in the Control F
(ADCn.CTRLF) register.
The total conversion (tsamp) time for each separate sample, in μs, is calculated by:
1 ... 13 1 ... 13
CLK_ADC
Enable
Trigger
ADC State Off Input Sampling 1 Conversion 1 Input Sampling 2 Input Sampling n Conversion n Off (1)
ADCn.SAMPLE Conversion 1 value (2) Conversion n-1 value Conversion n value (2)
Notes:
1. If the Low Latency (LOWLAT) bit is set to ‘1’ in the Control A (ADCn.CTRLA) register, the analog modules in
the ADC will not turn OFF at the end of the conversion, eliminating the initialization time when triggering the
following conversion.
2. The time from the conversion has finished to the outputs are available in the registers is 0.5 CLK_ADC cycles
followed by 1 CLK_MAIN cycle. The last conversion and accumulation require an additional CLK_MAIN cycle.
With minimum prescaling, this sums up to 1.5 CLK_ADC cycles before the final outputs are available.
The number of samples to accumulate is set by the Sample Number (SAMPNUM) bit field in the Control F
(ADCn.CTRLF) register.
The total conversion time (tconv) for a Burst Accumulation, in μs, is calculated by:
1 ... 13
CLK_ADC
Enable
Trigger
ADC State Off Idle (1) PGA Sampling Conversion (2) Off (3)
PGA State Off Input Sampling (1) Hold Sample Off (3)
Notes:
1. The PGA will start sampling the input once the PGA initialization is done, even if the ADC initialization is still
ongoing. In this case, the first sampling period will be longer than configured by SAMPDUR.
2. In Single 8-bit mode, the length of the Conversion state is nine CLK_ADC cycles. In all other modes, it is
thirteen cycles.
3. If the Low Latency (LOWLAT) bit is set to ‘1’ in the Control A (ADCn.CTRLA) register, the PGA and the analog
modules in the ADC will not turn OFF at the end of the conversion, eliminating the initialization time when
triggering the following conversion. The PGA will stay in the Input Sampling state until a new PGA sampling
occurs.
4. The time from the conversion has finished to the outputs are available in the registers is 0.5 CLK_ADC cycles
followed by 1 CLK_MAIN cycle. With minimum prescaling, this sums up to 1 CLK_ADC cycle.
The total conversion time (tconv) for a single result, in μs, is calculated by:
A new conversion starts immediately after a result is available in the Result (ADCn.RESULT) register if the Free-
Running (FREERUN) bit is set to ‘1’ in the Control F (ADCn.CTRLF) register. The Free-Running conversion rate
(fconv) is calculated by:
fCLK_ADC
fconv (12‐bit) =
SAMPDUR+ADCPGASAMPDUR + 15.5
fCLK_ADC
fconv (8‐bit) =
SAMPDUR+ADCPGASAMPDUR + 11.5
CLK_ADC
Enable
Trigger
ADC State Off Idle (1) PGA Sampling 1 Conversion 1 Off (2) Idle (1) PGA Sampling n Conversion n Off (2)
PGA State Off Input Sampling 1 (1) Hold Sample 1 Off (2) Input Sampling n (1) Hold Sample n Off (2)
Notes:
1. The PGA will start sampling the input once the PGA initialization is done, even if the ADC initialization is still
ongoing. In this case, the first sampling period will be longer than configured by SAMPDUR.
2. If the Low Latency (LOWLAT) bit is set to ‘1’ in the Control A (ADCn.CTRLA) register, the PGA and the analog
modules in the ADC will not turn OFF at the end of the conversion, eliminating the initialization time when
triggering the following conversion. The PGA will stay in the Input Sampling state until a new PGA sampling
occurs.
3. The time from the conversion has finished to the outputs are available in the registers is 0.5 CLK_ADC cycles
followed by 1 CLK_MAIN cycle. The last conversion and accumulation require an additional CLK_MAIN cycle.
With minimum prescaling, this sums up to 1.5 CLK_ADC cycles before the final outputs are available.
The number of samples to accumulate is set by the Sample Number (SAMPNUM) bit field in the Control F
(ADCn.CTRLF) register.
The total conversion time (tsamp) for each separate sample, in μs, is calculated by:
CLK_ADC
Enable
Trigger
ADC State Off Idle (1) PGA Sampling 1 Conversion 1 Idle Idle PGA Sampling n Conversion n Off (2)
PGA State Off Input Sampling 1 (1) Hold Sample 1 Input Sampling 2 Input Sampling n Hold Sample n Off (2)
ADCn.SAMPLE Conversion 1 value (3) Conversion n-1 value Conversion n value (3)
Notes:
1. The PGA will start sampling the input once the PGA initialization is done, even if the ADC initialization is still
ongoing. In this case, the first sampling period will be longer than configured by SAMPDUR.
2. If the Low Latency (LOWLAT) bit is set to ‘1’ in the Control A (ADCn.CTRLA) register, the PGA and the analog
modules in the ADC will not turn OFF at the end of the conversion, eliminating the initialization time when
triggering the following conversion. The PGA will stay in the Input Sampling state until a new PGA sampling
occurs.
3. The time from the conversion has finished to the outputs are available in the registers is 0.5 CLK_ADC cycles
followed by 1 CLK_MAIN cycle. The last conversion and accumulation require an additional CLK_MAIN cycle.
With minimum prescaling, this sums up to 1.5 CLK_ADC cycles before the final outputs are available.
The number of samples to accumulate is set by the Sample Number (SAMPNUM) bit field in the Control F
(ADCn.CTRLF) register.
For a Burst Accumulation with the PGA, SAMPDUR must be ≥ 11. The total conversion time (tconv), in μs, is
calculated by:
SAMPDUR+ADCPGASAMPDUR + 2 × SAMPNUM + 14
tconv = tinitialization +
fCLK_ADC
The Window Mode Source (WINSRC) bit in the Control D (ADCn.CTRLD) register selects if the comparison is done
on the 16 LSb of the Result (ADCn.RESULT) register or the Sample (ADCn.SAMPLE) register. If an interrupt request
is enabled for the WCMP flag, WINSRC selects which interrupt vector to request, RESRDY or SAMPRDY.
When accumulating multiple samples, if the Window Comparator source is the Result register, the comparison
between the result and the threshold(s) will happen after the last conversion is complete. If the source is the Sample
register, the comparison will happen after every conversion.
Assuming the ADC is already configured to run, follow these steps to use the Window Comparator mode:
1. Set the required threshold(s) by writing to the Window Comparator Low and High Threshold (ADCn.WINLT
and ADCn.WINHT) registers.
2. Optional: Enable the interrupt request by writing a ‘1’ to the Window Comparator Interrupt Enable (WCMP) bit
in the Interrupt Control (ADCn.INTCTRL) register.
3. Enable the Window Comparator by writing the WINSRC bit field and a non-zero value to the WINCM bit field in
the Control D (ADCn.CTRLD) register.
30.3.4 Events
The ADC can generate the following events:
Table 30-8. ADC Event Generators
The conditions for generating an event are identical to those that will raise the corresponding flag in the Interrupt
Flags (ADCn.INTFLAGS) register.
The ADC has one event user for detecting and acting upon input events. The table below describes the event user
and the associated functionality.
Table 30-9. ADC Event Users and Available Event Actions
User Name
Description Input Detection Async/Sync
Peripheral Event
ADCn START ADC start on event Edge Async
The START event action can be triggered if the EVENT_TRIGGER setting is written to the START bit field in the
Command (ADCn.COMMAND) register.
30.3.5 Interrupts
Table 30-10. Available Interrupt Vectors and Sources
...........continued
Name Vector Description Interrupt Flag Conditions
SAMPRDY The sample is available in ADCn.SAMPLE
SAMPRDY Sample Ready interrupt
WCMP As defined by WINSRC and WINCM in ADCn.CTRLD
RESRDY The result is available in ADCn.RESULT
RESRDY Result Ready interrupt
WCMP As defined by WINSRC and WINCM in ADCn.CTRLD
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
30.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RUNSTDBY LOWLAT ENABLE
Access R/W R/W R/W
Reset 0 0 0
30.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
PRESC[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
30.5.3 Control C
Name: CTRLC
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
TIMEBASE[4:0] REFSEL[2:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Note: The internal references can only be used if lower than VDD - 0.5V.
30.5.4 Control D
Name: CTRLD
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
WINSRC WINCM[2:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTCTRL
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
TRIGOVR SAMPOVR RESOVR WCMP SAMPRDY RESRDY
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: INTFLAGS
Offset: 0x05
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
TRIGOVR SAMPOVR RESOVR WCMP SAMPRDY RESRDY
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
30.5.7 Status
Name: STATUS
Offset: 0x06
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ADCBUSY
Access R
Reset 0
Name: DBGCTRL
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
30.5.9 Control E
Name: CTRLE
Offset: 0x08
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SAMPDUR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
30.5.10 Control F
Name: CTRLF
Offset: 0x09
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
FREERUN LEFTADJ SAMPNUM[3:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 5 – FREERUN Free-Running
This bit controls whether the ADC Free-Running mode is enabled or not.
Value Description
0 The ADC Free-Running mode is disabled
1 The ADC Free-Running mode is enabled. A new conversion is started as soon as the previous
conversion or accumulation has completed.
30.5.11 Command
Name: COMMAND
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DIFF MODE[2:0] START[2:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 – DIFF Differential
This bit controls whether the ADC conversion is Single-Ended or Differential.
Value Description
0x0 Unsigned Single-Ended conversion. Only the ADCn.MUXPOS register is used.
0x1 Signed Differential conversion. Both the ADCn.MUXPOS and ADCn.MUXNEG registers are used.
Note: If the ENABLE bit in ADCn.CTRLA is ‘0’ when writing the START bit field to IMMEDIATE, it will automatically
be set to STOP.
Name: PGACTRL
Offset: 0x0B
Reset: 0x04
Property: -
Bit 7 6 5 4 3 2 1 0
GAIN[2:0] PGABIASSEL[1:0] ADCPGASAMPDUR[1:0] PGAEN
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 1 0 0
Note: If both PGAEN and the Low Latency (LOWLAT) bit in the Control A (ADCn.CTRLA) register are ‘1’, the
PGA will be ON continuously, even when not selected by the VIA bit field. This eliminates the initialization time if
reconfiguring the ADC to use the PGA.
Name: MUXPOS
Offset: 0x0C
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
VIA[1:0] MUXPOS[5:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Note: The VIA bits in MUXPOS and MUXNEG are shared, so a value written to the VIA bit field in one of the two
registers is updated in both. It is, therefore, not possible to have one input using the PGA and the other not using the
PGA.
Name: MUXNEG
Offset: 0x0D
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
VIA[1:0] MUXNEG[5:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Note: The VIA bits in MUXPOS and MUXNEG are shared, so a value written to the VIA bit field in one of the two
registers is updated in both. It is, therefore, not possible to have one input using the PGA and the other not using the
PGA.
30.5.15 Result
Name: RESULT
Offset: 0x10
Reset: 0x00
Property: -
The ADCn.RESULT0 to ADCn.RESULT3 registers represent the 32-bit value, ADCn.RESULT. The low byte [7:0]
(suffix 0) is accessible at the original offset. The n higher bytes [31:8] can be accessed at offset + n.
Refer to the Output Formats section for details on the output from this register.
Bit 31 30 29 28 27 26 25 24
RESULT[31:24]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
RESULT[23:16]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
RESULT[15:8]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RESULT[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
30.5.16 Sample
Name: SAMPLE
Offset: 0x14
Reset: 0x00
Property: -
The ADCn.SAMPLEL and ADCn.SAMPLEH register pair represents the 16-bit value, ADCn.SAMPLE. The low byte
[7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Refer to the Output Formats section for details on the output from this register.
Bit 15 14 13 12 11 10 9 8
SAMPLE[15:8]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SAMPLE[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
30.5.17 Temporary n
Name: TEMPn
Offset: 0x18 + n*0x01 [n=0..2]
Reset: 0x00
Property: -
The Temporary registers are used by the CPU for single-cycle access to the 16- and 32-bit registers of this
peripheral. The registers are common for all the 16- and 32-bit registers of this peripheral and can be read and
written by software. For more details on reading and writing 16- and 32-bit registers, refer to Accessing 16-Bit
Registers and Accessing 32-Bit Registers in the AVR CPU section.
Bit 7 6 5 4 3 2 1 0
TEMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: WINLT
Offset: 0x1C
Reset: 0x00
Property: -
This register is the 16-bit Low Threshold for the digital comparator monitoring the ADC Result or Sample
(ADCn.RESULT or ADCn.SAMPLE) registers. The data format must be according to Conversion mode and left
adjustment setting.
The ADCn.WINLTH and ADCn.WINLTL register pair represents the 16-bit value, ADCn.WINLT. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
When monitoring the ADC Result register, in an accumulation mode, the window comparator thresholds are applied
to the result after all accumulation and, optionally, scaling is done.
Bit 15 14 13 12 11 10 9 8
WINLT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WINLT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: WINHT
Offset: 0x1E
Reset: 0x00
Property: -
This register is the 16-bit High Threshold for the digital comparator monitoring the ADC Result or Sample
(ADCn.RESULT or ADCn.SAMPLE) registers. The data format must be according to Conversion mode and left
adjustment setting.
The ADCn.WINHTH and ADCn.WINHTL register pair represents the 16-bit value, ADCn.WINHT. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
When monitoring the ADC Result register, in an accumulation mode, the window comparator thresholds are applied
to the result after all accumulation and, optionally, scaling is done.
Bit 15 14 13 12 11 10 9 8
WINHT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WINHT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
31.1 Features
• UPDI One-Wire Interface for External Programming and On-Chip-Debugging (OCD)
– Enable programming by high-voltage or fuse
– Uses the RESET pin of the device for programming
– No GPIO pins occupied during the operation
– Asynchronous half-duplex UART protocol towards the programmer
• Programming:
– Built-in error detection and error signature generation
– Override of response generation for faster programming
• Debugging:
– Memory-mapped access to device address space (NVM, RAM, I/O)
– No limitation on the device clock frequency
– Unlimited number of user program breakpoints
– Two hardware breakpoints
– Support for advanced OCD features
• Run-time readout of the CPU Program Counter (PC), Stack Pointer (SP) and Status Register (SREG)
for code profiling
• Detection and signalization of the Break/Stop condition in the CPU
• Program flow control for Run, Stop and Reset debug instructions
– Nonintrusive run-time chip monitoring without accessing the system registers
– Interface for reading the result of the CRC check of the Flash on a locked device
31.2 Overview
The Unified Program and Debug Interface (UPDI) is a proprietary interface for external programming and OCD of a
device.
The UPDI supports programming of Nonvolatile Memory (NVM) space, Flash, EEPROM, fuses, lock bits, and the
user row. Some memory-mapped registers are accessible only with the correct access privilege enabled (key, lock
bits) and only in the OCD Stopped mode or certain Programming modes. These modes are unlocked by sending the
correct key to the UPDI. See the NVMCTRL - Nonvolatile Memory Controller section for programming via the NVM
controller and executing NVM controller commands.
The UPDI is partitioned into three separate protocol layers: the UPDI Physical (PHY) Layer, the UPDI Data Link (DL)
Layer and the UPDI Access (ACC) Layer. The default PHY layer handles bidirectional UART communication over
the UPDI pin line towards a connected programmer/debugger and provides data recovery and clock recovery on
an incoming data frame in the One-Wire Communication mode. Received instructions and corresponding data are
handled by the DL layer, which sets up the communication with the ACC layer based on the decoded instruction.
Access to the system bus and memory-mapped registers is granted through the ACC layer.
Programming and debugging are done through the PHY layer, which is a one-wire UART based on a half-duplex
interface using the RESET pin for data reception and transmission. The clocking of the PHY layer is done by a
dedicated internal oscillator.
The ACC layer is the interface between the UPDI and the connected bus matrix. This layer grants access via the
UPDI interface to the bus matrix with memory-mapped access to system blocks such as memories, NVM, and
peripherals.
The Asynchronous System Interface (ASI) provides direct interface access to select features in the OCD, NVM, and
System Management systems. This gives the debugger direct access to system information without requesting bus
access.
Bus Matrix
NVM
UPDI Pin
(RX/TX Data) UPDI UPDI
Physical Access
layer layer Peripherals
ASI Access
Controller
System
OCD
NVM
31.2.2 Clocks
The PHY layer and the ACC layer can operate on different clock domains. The PHY layer clock is derived from the
dedicated internal oscillator, and the ACC layer clock is the same as the peripheral clock. There is a synchronization
boundary between the PHY and the ACC layer, which ensures correct operation between the clock domains. The
UPDI clock output frequency is selected through the ASI, and the default UPDI clock start-up frequency is 4 MHz
after enabling or resetting the UPDI. The UPDI clock frequency can be changed by writing to the UPDI Clock Divider
Select (UPDICLKSEL) bit field in the ASI Control A (UPDI.ASI_CTRLA) register.
UPDI Controller
SYNCH
UPDI UPDI
Physical Access
layer layer
Clock Clock
Controller Controller
CLK_UPDI
CLK_UPDI
CLK_PER
source
CLK_PER
~ UPDICLKSEL ~
St 0 1 2 3 4 5 6 7 P S1 S2
IDLE
BREAK
SYNCH (0x55)
St P S1 S2
Synch Part
End_synch
ACK (0x40)
St P S1 S2
Frame Description
DATA A DATA frame consists of one Start (St) bit, which is always low, eight Data bits, one Parity (P) bit for
even parity, and two Stop (S1 and S2) bits, which are always high. If the Parity bit or Stop bits have an
incorrect value, an error will be detected and signalized by the UPDI. The parity bit-check in the UPDI can
be disabled by writing to the Parity Disable (PARD) bit in the Control A (UPDI.CTRLA) register, in which
case the parity generation from the debugger is ignored.
IDLE This is a special frame that consists of at least 12 high bits. This is the same as keeping the transmission
line in an Idle state.
BREAK This is a special frame that consists of at least 12 low bits. It is used to reset the UPDI back to its default
state and is typically used for error recovery.
SYNCH The SYNCH frame is used by the Baud Rate Generator to set the baud rate for the coming transmission.
A SYNCH character is always expected by the UPDI in front of every new instruction, and after a
successful BREAK has been transmitted.
ACK The ACK frame is transmitted from the UPDI whenever an ST or an STS instruction has successfully
crossed the synchronization boundary and gained bus access. When an ACK is received by the
debugger, the next transmission can start.
The transmission baud rate of the PHY layer is related to the selected UPDI clock, which can be adjusted by writing
to the UPDI Clock Divider Select (UPDICLKSEL) bit field in the ASI Control A (UPDI.ASI_CTRLA) register. The
receive and transmit baud rates are always the same within the accuracy of the auto-baud.
Table 31-1. Recommended UART Baud Rate Based on UPDICLKSEL Setting
The UPDI Baud Rate Generator utilizes fractional baud counting to minimize the transmission error. With the fixed
frame format used by the UPDI, the maximum and recommended receiver transmission error limits can be seen in
Table 31-2.
Table 31-2. Receiver Baud Rate Error
Data + Parity Bits Rslow Rfast Max. Total Error [%] Recommended Max. RX Error [%]
9 96.39 104.76 +4.76/-3.61 +1.5/-1.5
2. It is used by the Baud Rate Generator to set the baud rate for the subsequent transmission. If an invalid
SYNCH character is sent, the next transmission will not be sampled correctly.
31.3.2 Operation
The UPDI must be enabled before the UART communication can start.
Figure 31-4. UPDI Enable Sequence with UPDI PAD Enabled By Fuse
1 Fuse read in. Pull-up enabled. Ready to receive init.
2 Drive low from the debugger to request the UPDI clock.
3 UPDI clock ready; Communication channel ready.
1
2
RESET Hi-Z St D0 D1 D2 D3 D4 D5 D6 D7 Sp
Handshake / BREAK
t RES SYNC (0x55)
(Auto-baud)
UPDI.rxd (Ignore)
3
UPDI.txd Hi-Z Hi-Z
UPDI.txd = 0
t UPDI
debugger.
Hi-Z Hi-Z
UPDI.txd
Debugger.txd = 0 Debugger.txd = z
t Deb0 t DebZ
When the negative edge is detected, the UPDI clock starts. The UPDI will continue to drive the line low until the clock
is stable and ready for the UPDI to use. The duration of tUPDI will vary, depending on the status of the oscillator when
the UPDI is enabled. After this duration, the data line will be released by the UPDI and pulled high.
When the debugger detects that the line is high, the initial SYNCH character 0x55 must be transmitted to
synchronize the UPDI communication data rate. If the Start bit of the SYNCH character is not sent within maximum
tDebZ, the UPDI will disable itself, and the UPDI enabling sequence must be reinitiated. If the timing is violated, the
UPDI is disabled to avoid unintentional enabling of the UPDI.
After a successful SYNCH character transmission, the first instruction frame can be transmitted.
(Ignore)
Hi-Z St D0 D1 D2 D3 D4 D5 D6 D7 Sp
UPDIPAD
HV ramp Debugger.txd = z Handshake/BREAK
t HV_ramp t DebZ t RES SYNC (0x55)
Min. is 10 ns Min. is 1 μs (Auto-baud)
Max. is 10 μs Min. is 10 μs
Max. is 4 ms
Max. is 200 μs
(Ignore)
UPDI.rxd
Hi-Z 2 Hi-Z
UPDI.txd
UPDI.txd = 0
t UPDI
Min. is 10 μs
Max. is 200 μs
Debugger.txd = 0 Debugger.txd = z
t Deb0 t DebZ
HV Min. is 200 ns Min. is 200 μs
debugger Max. is 1 μs Max. is 14 ms
UPDI HV Vdd
When enabled by an HV pulse, only a POR will disable the UPDI configuration on the RESET pin and restore the
default setting. If issuing a UPDI Disable command through the UPDIDIS bit in UPDI.CTRLB, the UPDI will be reset,
and the clock request will be canceled, but the RESET pin will remain in UPDI configuration.
Notes:
1. If insufficient external protection is added to the UPDI pin, an ESD pulse can be interpreted by the device as a
high-voltage override and enable the UPDI.
2. The actual threshold voltage for the UPDI HV activation depends on VDD. See the Electrical Characteristics
section for more details.
Output Enable Timer Protection for GPIO Configuration
When the RESET Pin Configuration (RSTPINCFG) bit in FUSE.SYSCFG0 is ‘0x0’, the RESET pin is configured as
GPIO. To avoid a potential conflict between the GPIO actively driving the output and a UPDI high-voltage (HV) enable
sequence initiation, the GPIO output driver is disabled for a minimum of 8.8 ms after a System Reset.
It is always recommended to issue a Power-On Reset (POR) before entering the HV programming sequence.
The UPDI guard time is the minimum Idle time that the connected debugger will experience when waiting for data
from the UPDI. The maximum Idle time is the same as time-out. The Idle time before a transmission will be more than
the expected guard time when the synchronization time plus the data bus accessing time is longer than the guard
time.
It is recommended to always use the insertion of minimum two Guard Time bits on the UPDI side, and one guard time
cycle insertion from the debugger side.
LD 0 0 1 0
Size A - Address Size
0 0 Byte - can address 0-255 B
0 1 Word (2 Bytes) - for memories up to 64 KB in size
ST 0 1 1 0
1 0 3 Bytes - for memories above 64 KB in size
1 1 Reserved
CS Address
Ptr - Pointer Access
0 0 * (ptr)
LDCS 1 0 0 0
0 1 * (ptr++)
1 0 ptr
1 1 Reserved
STCS 1 1 0 0
31.3.3.1 LDS - Load Data from Data Space Using Direct Addressing
The LDS instruction is used to load data from the system bus into the PHY layer shift register for serial readout. The
LDS instruction is based on direct addressing, and the address must be given as an operand to the instruction for the
data transfer to start. The maximum supported size for the address and data is 32 bits. The LDS instruction supports
repeated memory access when combined with the REPEAT instruction.
After issuing the LDS instruction, the number of desired address bytes, as indicated by the Size A field followed
by the output data size, which is selected by the Size B field, must be transmitted. The output data is issued after
the specified Guard Time (GT). When combined with the REPEAT instruction, the address must be sent in for each
iteration of the repeat, meaning after each time the output data sampling is done. There is no automatic address
increment when using REPEAT with LDS, as it uses a direct addressing protocol.
Figure 31-8. LDS Instruction Operation
ADDRESS_SIZE
Synch RX
LDS Adr_0 Adr_n
(0x55)
Data_0 Data_n TX
ΔGT
When the instruction is decoded, and the address byte(s) are received as dictated by the decoded instruction, the DL
layer will synchronize all required information to the ACC layer, which will handle the bus request and synchronize
data buffered from the bus back again to the DL layer. This will create a synchronization delay that must be taken into
consideration upon receiving the data from the UPDI.
ADDRESS_SIZE DATA_SIZE
Synch RX
STS Adr_0 Adr_n Data_0 Data_n
(0x55)
ACK ACK TX
ΔGT ΔGT
The transfer protocol for an STS instruction is depicted in Figure 31-9, following this sequence:
1. The address is sent.
2. An Acknowledge (ACK) is sent back from the UPDI if the transfer was successful.
3. The number of bytes, as specified in the STS instruction, is sent.
4. A new ACK is received after the data have been successfully transferred.
Synch
LD
(0x55) DATA_SIZE RX
Data_0 Data_n
TX
ΔGT
The figure above shows an example of a typical LD sequence, where the data are received after the Guard Time
(GT) period. Loading data from the UPDI Pointer register follows the same transmission protocol.
For the LD instruction from the data space, the pointer register must be set up by using an ST instruction to the
UPDI Pointer register. After the ACK has been received on a successful Pointer register write, the LD instruction must
be set up with the desired DATA SIZE operands. An LD to the UPDI Pointer register is done directly with the LD
instruction.
31.3.3.4 ST - Store Data from UPDI to Data Space Using Indirect Addressing
The ST instruction is used to store data from the UPDI PHY shift register to the data space. The ST instruction is
used to store data that are shifted serially into the PHY layer. The ST instruction is based on indirect addressing,
which means that the Address Pointer in the UPDI needs to be written before the data space. The automatic pointer
post-increment operation is supported and is useful when the ST instruction is utilized with the REPEAT instruction.
The ST instruction is also used to store the UPDI Address Pointer into the Pointer register. The maximum supported
size for storing address and data is 32 bits.
ADDRESS_SIZE
Synch
ST ADR_0 ADR_n RX
(0x55)
ACK TX
ΔGT
BLOCK_SIZE
Synch RX
ST Data_0 Data_n
(0x55)
ACK TX
ΔGT
The figure above gives an example of an ST instruction to the UPDI Pointer register and the storage of regular data.
A SYNCH character is sent before each instruction. In both cases, an Acknowledge (ACK) is sent back by the UPDI if
the ST instruction was successful.
To write the UPDI Pointer register, the following procedure has to be followed:
1. Set the PTR field in the ST instruction to signature 0x2.
2. Set the address size (Size A) field to the desired address size.
3. After issuing the ST instruction, send Size A bytes of address data.
4. Wait for the ACK character, which signifies a successful write to the Address register.
After the Address register is written, sending data is done in a similarly:
1. Set the PTR field in the ST instruction to signature 0x0 to write to the address specified by the UPDI Pointer
register. If the PTR field is set to 0x1, the UPDI pointer is automatically updated to the next address according
to the data size Size B field of the instruction after the write is executed.
2. Set the Size B field in the instruction to the desired data size.
3. After sending the ST instruction, send Size B bytes of data.
4. Wait for the ACK character, which signifies a successful write to the bus matrix.
When used with the REPEAT instruction, it is recommended to set up the Address register with the start address
for the block to be written and use the Pointer Post Increment register to automatically increase the address for
each repeat cycle. When using the REPEAT instruction, the data frame of Size B data bytes can be sent after each
received ACK.
31.3.3.5 LDCS - Load Data from Control and Status Register Space
The LDCS instruction is used to load serial readout data from the UPDI Control and the Status register space located
in the DL layer into the PHY layer shift register. The LDCS instruction is based on direct addressing, where the
address is part of the instruction operands. The LDCS instruction can access only the UPDI CS register space. This
instruction supports only byte access, and the data size is not configurable.
Figure 31-12. LDCS Instruction Operation
OPCODE CS Address
Synch
LDCS
(0x55) RX
Data TX
Δgt
Figure 31-12 shows a typical example of LDCS data transmission. A data byte from the LDCS is transmitted from the
UPDI after the guard time is completed.
OPCODE CS Address
Synch
STCS Data
(0x55) RX
TX
Figure 31-13 shows the data frame transmitted after the SYNCH character and the instruction frames. The STCS
instruction byte can be immediately followed by the data byte. There is no response generated from the STCS
instruction, as is the case for the ST and STS instructions.
OPCODE Size B
Size B - Data Size
0 0 1 Byte
REPEAT 1 0 1 0 0 0
0 1 Word (2 Bytes)
1 0 Reserved
1 1 Reserved
REPEAT_SIZE
Synch
REPEAT RPT_0
(0x55) Repeat Number of Blocks of DATA_SIZE
Synch ST RX
Data_0 Data_n DataB_1 DataB_n
(0x55) (ptr++)
ACK ACK TX
Δd Δd Δd Δd Δd
Figure 31-14 gives an example of a repeat operation with an ST instruction using pointer post-increment operation.
After the REPEAT instruction is sent with RPT_0 = n, the first ST instruction is issued with SYNCH and instruction
frame, while the next n ST instructions are executed by only sending data bytes according to the ST operand
DATA_SIZE, and maintaining the Acknowledge (ACK) handshake protocol.
Synch
REPEAT RPT_0 RPT_1
(0x55)
Synch LD
(0x55) (ptr++) RX
DATA_SIZE TX
DATA_SIZE
DataB_1 DataB_n
ΔGT
For LD, data will come out continuously after the LD instruction. Note the guard time on the first data block.
If using indirect addressing instructions (LD/ST), it is recommended to always use the pointer post-increment option
when combined with REPEAT. The ST/LD instruction is necessary only before the first data block (number of data
bytes determined by DATA_SIZE). Otherwise, the same address will be accessed in all repeated access operations.
For direct addressing instructions (LDS/STS), the address must always be transmitted as specified in the instruction
protocol, before data can be received (LDS) or sent (STS).
SIB Size C
Size C - Key Size
0 0 64 bits (8 Bytes)
KEY 1 1 1 0 0
0 1 128 bits (16 Bytes) (SIB only)
1 0 Reserved
1 1 Reserved
KEY_SIZE
Synch
KEY KEY_0 KEY_n RX
(0x55)
TX
Synch RX
KEY
(0x55)
TX
SIB_0 SIB_n
Δgt
SIB_SIZE
Figure 31-16 shows the transmission of a key and the reception of a SIB. In both cases, the Size C (SIZE_C) field
in the operand determines the number of frames being sent or received. There is no response after sending a KEY
to the UPDI. When requesting the SIB, data will be transmitted from the UPDI according to the current guard time
setting.
must be ignored. The second captured value based on the input event must be used for the measurement. See
Figure 31-17 for an example using 10 kbps UPDI SYNCH character pulses, giving a capture window of 200 µs
for the timer.
• It is possible to read out the captured value directly after the SYNCH character by reading the TCBn.CCMP
register, or the value can be written to memory by the CPU once the capture is done. For more details, refer to
the TCB - 16-bit Timer/Counter Type B section.
Figure 31-17. UPDI System Clock Measurement Events
UPDI_Input
RX
Debugger
Data
RPT CNT LD*(ptr) GT D0 SB D1 SB D2 SB D3 SB D4 SB D5 SB
TX
Debugger D1 lost D3 lost
D0 D2 D4
Processing
RX
Debugger
RPT CNT LD*(ptr) GT D0 SB IB D1 SB IB D2 SB IB D3 SB
Data
TX
Debugger
D0 D1 D2 D3
Processing
Notes:
1. GT denotes the guard time insertion.
2. SB is for Stop bit.
3. IB is the inserted inter-byte delay.
4. The rest of the frames are data and instructions.
Table 31-5 gives an overview of the available key signatures that must be shifted in to activate the interfaces.
Table 31-5. Key Activation Signatures
2. Optional: Read the Chip Erase (CHIPERASE) bit in the ASI Key Status (UPDI.ASI_KEY_STATUS) register to
see that the key is successfully activated.
3. Write the signature to the Reset Request (RSTREQ) bit in the ASI Reset Request (UPDI.ASI_RESET_REQ)
register. This will issue a System Reset.
4. Write 0x00 to the ASI Reset Request (UPDI.ASI_RESET_REQ) register to clear the System Reset.
5. Read the NVM Lock Status (LOCKSTATUS) bit from the ASI System Status (UPDI.ASI_SYS_STATUS)
register.
6. The chip erase is done when LOCKSTATUS bit is ‘0’. If the LOCKSTATUS bit is ‘1’, return to step 5.
After a successful Chip Erase, the Lockbits will be cleared, and the UPDI will have full access to the system. Until
Lockbits are cleared, the UPDI cannot access the system bus, and only CS-space operations can be performed.
During chip erase, the BOD is forced in ON state by writing to the Active (ACTIVE) bit field from the
CAUTION
Control A (BOD.CTRLA) register and uses the BOD Level (LVL) bit field from the BOD Configuration
(FUSE.BODCFG) fuse and the BOD Level (LVL) bit field from the Control B (BOD.CTRLB) register. If
the supply voltage VDD is below that threshold level, the device is unavailable until VDD is increased
adequately. See the BOD section for more details.
7. The data to be written to the User Row must first be written to a buffer in the RAM. The writable area in the
RAM has a size of 32 bytes, and it is only possible to write user row data to the first 32 byte addresses of the
RAM. Addressing outside this memory range will result in a nonexecuted write. The data will map 1:1 with the
user row space when the data is copied into the user row upon completion of the Programming sequence.
8. When all user row data has been written to the RAM, write the User Row Programming Done (UROWDONE)
bit in the ASI System Control A (UPDI.ASI_SYS_CTRLA) register.
9. Read the Start User Row Programming (UROWPROG) bit from the ASI System Status
(UPDI.ASI_SYS_STATUS) register.
10. The User Row Programming is completed when UROWPROG bit is ‘0’. If UROWPROG bit is ‘1’, return to step
9.
11. Write to the User Row Write Key Status (UROWWRITE) bit in the ASI Key Status (UPDI.ASI_KEY_STATUS)
register.
12. Write the signature to the Reset Request (RSTREQ) bit in the ASI Reset Request (UPDI.ASI_RESET_REQ)
register. This will issue a System Reset.
13. Write 0x00 to the ASI Reset Request (UPDI.ASI_RESET_REQ) register to clear the System Reset.
14. The User Row Programming is complete.
It is not possible to read back data from the RAM in this mode. Only writes to the first 32 bytes of the RAM are
allowed.
31.3.9 Events
The UPDI can generate the following events:
Table 31-6. Event Generators in UPDI
This event is set on the UPDI clock for each detected positive edge in the SYNCH character, and it is not possible to
disable this event from the UPDI.
The UPDI has no event users.
Refer to the Event System section for more details regarding event types and Event System configuration.
31.5.1 Status A
Name: STATUSA
Offset: 0x00
Reset: 0x40
Property: -
Bit 7 6 5 4 3 2 1 0
UPDIREV[3:0]
Access R R R R
Reset 0 1 0 0
31.5.2 Status B
Name: STATUSB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
PESIG[2:0]
Access R R R
Reset 0 0 0
31.5.3 Control A
Name: CTRLA
Offset: 0x02
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
IBDLY PARD DTD RSD GTVAL[2:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
31.5.4 Control B
Name: CTRLB
Offset: 0x03
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
NACKDIS CCDETDIS UPDIDIS
Access R/W R/W R/W
Reset 0 0 0
Name: ASI_KEY_STATUS
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
UROWWRITE NVMPROG CHIPERASE
Access R/W R R
Reset 0 0 0
Name: ASI_RESET_REQ
Offset: 0x08
Reset: 0x00
Property: -
A Reset is signalized to the System when writing the Reset signature to this register.
Bit 7 6 5 4 3 2 1 0
RSTREQ[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: ASI_CTRLA
Offset: 0x09
Reset: 0x03
Property: -
Bit 7 6 5 4 3 2 1 0
UPDICLKSEL[1:0]
Access R/W R/W
Reset 1 1
Name: ASI_SYS_CTRLA
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
UROWWRITE_ CLKREQ
FINAL
Access R R R R R R R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: ASI_SYS_STATUS
Offset: 0x0B
Reset: 0x01
Property: -
Bit 7 6 5 4 3 2 1 0
RSTSYS INSLEEP NVMPROG UROWPROG LOCKSTATUS
Access R R R R R
Reset 0 0 0 0 1
Name: ASI_CRC_STATUS
Offset: 0x0C
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
CRC_STATUS[2:0]
Access R R R
Reset 0 0 0
33.1 Disclaimer
All typical values are measured at T = 25°C and VDD = 3V unless otherwise specified. All minimum and maximum
values are valid across operating temperature and voltage unless otherwise specified.
Typical values given should be considered for design guidance only, and actual part variation around these values is
expected.
Note:
1. If the VPIN is lower than GND – 0.6V, then a current limiting resistor is required. The negative DC injection
current limiting resistor is calculated as R = (GND – 0.6V – VPIN)/ICn.
If the VPIN is greater than VDD+0.6V, then a current limiting resistor is required. The positive DC injection
current limiting resistor is calculated as R = (VPIN – (VDD + 0.6))/ICn.
VRSTMAX = 13V
CAUTION
Care should be taken to avoid overshoot (overvoltage) when connecting the RESET pin to a 12V source.
Exposing the pin to a voltage above the rated absolute maximum can activate the pin’s ESD protection
circuitry, which will remain activated until the voltage has been brought below approximately 10V. A 12V
driver can keep the ESD protection in an activated state (if activated by an overvoltage condition) while
driving currents through it, potentially causing permanent damage to the part.
Notes:
1. Operation is ensured down to 1.8V or BOD triggering level VBOD when BOD is active.
2. During Chip Erase, the BOD is forced ON. If the supply voltage VDD is below the configured VBOD, the erase
attempt will fail.
3. Operation is ensured down to 2.7V or BOD triggering level VBOD when BOD is active.
Table 33-3. Operating Voltage and Frequency
Notes:
1. Operation is ensured down to BOD triggering level, VBOD with BODLEVEL0.
2. Operation is ensured down to BOD triggering level, VBOD with BODLEVEL2.
3. Operation is ensured down to BOD triggering level, VBOD with BODLEVEL7.
4. These specifications do not apply to automotive range parts (-VAO).
The maximum CPU clock frequency depends on VDD. As shown in the figure below, the Maximum Frequency vs. VDD
is linear between 1.8V < VDD < 2.7V and 2.7V < VDD < 4.5V.
20 MHz
10 MHz
Safe Operating Area
5 MHz
16 MHz
8 MHz
Where Cload = pin load capacitance and fsw = average switching frequency of I/O pin.
Table 33-4. Power Dissipation and Junction Temperature vs. Temperature
...........continued
Mode Description Condition Min. Typ. Max. Unit
Standby Standby power RTC running at - 0.7 - µA
consumption 1.024 kHz from
external XOSC32K
(CL = 7.5 pF)
RTC running at T = 25°C - 0.7 2.0 µA
1.024 kHz from
T = 85°C - - 6.0(1) µA
internal OSCULP32K
T = 125°C - - 8.0 µA
Power Power-down/ All peripherals T = 25°C - 0.1 1.5 µA
Down/ Standby power stopped
T = 85°C - - 4.0(1) µA
Standby consumption are
the same when T = 125°C - - 7.0 µA
all peripherals
are stopped
Reset Reset power Reset line pulled low - 100 - µA
consumption
Note:
1. These values are based on characterization and not covered by production test limits.
Symbol Description Clock PDIV fCLK_CPU VDD Min. Typ. Max. Unit
Source Division
tstartup The start-up time from the release Any Any Any Any - 200 - µs
of any Reset source. Execution
of first instruction. (Excluding
CRCSCAN)
twakeup(1) Wake-up from Idle OSC20M 1 20 MHz 5V - 1 -
FREQSEL =
0x2 2 10 MHz 3V - 2 -
4 5 MHz 2V - 4 -
OSC20M 1 16 MHz 5V - 1.2 -
FREQSEL =
0x1 2 8 MHz 3V - 2.4 -
Note:
1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on the
clock output (CLKOUT) pin. All peripherals and modules start execution from the first clock cycle, except the
CPU that is halted for four clock cycles before program execution starts.
Figure 33-3. Wake-Up Time Definition
Wake-Up Time
Wake-Up Request
CLKOUT
• OSC20M at 1 MHz used as the system clock source, unless otherwise specified
• In Idle sleep mode, unless otherwise specified
Table 33-7. Peripherals Power Consumption
Notes:
1. Current consumption of the module only. To calculate the total internal power consumption of the
microcontroller, power consumption values of all the peripherals and the clock sources used must be added to
the base power consumption given in the Power Consumption section in electrical characteristics.
2. CPU in Standby mode.
3. Average power consumption with ADC active in Free-Running mode.
Notes:
1. For design guidance only and not tested in production.
2. A slope faster than the maximum rating can trigger a Reset of the device if changing the voltage level after an
initial power-up.
Note:
1. For design guidance only. Not tested in production.
Table 33-10. Brown-out Detector (BOD) Characteristics
Note:
1. These parameters are for design guidance only and are not production tested.
FREQSEL = 0x02 - 20 -
ETOTAL Total error with 16 MHz and 20 From target TA = 25°C, 3.0V -1.5 - 1.5 %
MHz frequency selection frequency
TA = [0, 70]°C, VDD = -2.0(1) - 2.0(1) %
[1.8, 3.6]V
Full operation range -3.5 - 3.5
ΔfOSC20M Calibration step size - 0.75 - %
DOSC20M Duty cycle - 50 - %
tstartup Start-up time Within 2% accuracy - 12 - µs
Note:
1. These values are based on characterization and are not covered by production test limits.
Table 33-13. 32.768 kHz Internal Oscillator (OSCULP32K) Characteristics
Note:
1. These values are based on characterization and are not covered by production test limits.
Table 33-14. 32.768 kHz External Crystal Oscillator (XOSC32K) Characteristics
Note:
1. This parameter is for design guidance only. Not production tested.
ATtiny424/426/427
ATtiny824/826/827
Electrical Characteristics
V IH1
V IL1
Symbol Description Condition VDD=[1.8, 5.5]V VDD=[2.7, 5.5]V VDD=[4.5, 5.5]V Unit
Min. Max. Min. Max. Min. Max.
fCLCL Frequency 0 5.0 0.0 10.0 0.0 20.0 MHz
tCLCL Clock Period 200 - 100 - 50 - ns
tCHCX(1) High Time 80 - 40 - 20 - ns
tCLCX(1) Low Time 80 - 40 - 20 - ns
tCLCH(1) Rise Time (for maximum - 40 - 20 - 10 ns
frequency)
tCHCL(1) Fall Time (for maximum - 40 - 20 - 10 ns
frequency)
ΔtCLCL(1) Change in period from one clock - 20 - 20 - 20 %
cycle to the next
Note:
1. This parameter is for design guidance only. Not production tested.
VIL Input low-voltage, except RESET pin as I/O -0.2 - 0.3 × VDD V
VIH Input high-voltage, except RESET pin as I/O 0.7 × VDD - VDD + 0.2V V
IIH / IIL I/O pin Input leakage current, except RESET pin as I/O VDD = 5.5V, Pin high - < 0.05 - µA
VOL I/O pin drive strength VDD = 1.8V, IOL = 1.5 mA - - 0.36 V
VOH I/O pin drive strength VDD = 1.8V, IOH = 1.5 mA 1.44 - - V
...........continued
Symbol Description Condition Min. Typ. Max. Unit
Itotal Maximum combined I/O sink current per pin group(1) - - 100 mA
VIH2 Input high-voltage on RESET pin as I/O 0.7 × VDD - VDD + 0.2V V
VOL2 I/O pin drive strength on RESET pin as I/O VDD = 1.8V, IOL = 0.1 mA - - 0.36 V
VOH2 I/O pin drive strength on RESET pin as I/O VDD = 1.8V, IOH = 0.1 mA 1.44 - - V
other AC pins - 4 -
RP Pull-up resistor 20 35 50 kΩ
Notes:
1. Pin group x (Px[7:0]). The combined continuous sink/source current for all I/O ports should not exceed the
limits.
2. This capacitance is valid for pins with this functionality, even when that functionality is not used.
33.12 USART
Figure 33-5. USART in SPI Mode - Timing Requirements in Host Mode
SS
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS tMIH tSCK
MISO
MSb LSb
(Data Input)
tMOH tMOH
MOSI
(Data Output) MSb LSb
Note:
1. These parameters are for design guidance only and are not production tested.
33.13 SPI
Figure 33-6. SPI - Timing Requirements in Host Mode
SS
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS tMIH tSCK
MISO
MSb LSb
(Data Input)
tMOH tMOH
MOSI
(Data Output) MSb LSb
SS
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS tSIH tSSCK
MOSI
MSb LSb
(Data Input)
MISO
(Data Output) MSb LSb
...........continued
Symbol Description Condition Min. Typ. Max. Unit
tSSCK Client SCK period Client 4 × t CLK_PER - - ns
tSSCKW SCK high/low width Client 2 × t CLK_PER - - ns
tSSCKR SCK rise time Client - - 1600 ns
tSSCKF SCK fall time Client - - 1600 ns
tSIS MOSI setup to SCK Client 3.0 - - ns
tSIH MOSI hold after SCK Client t CLK_PER - - ns
tSSS SS setup to SCK Client 21 - - ns
tSSH SS hold after SCK Client 20 - - ns
tSOS MISO setup to SCK Client - 8.0 - ns
tSOH MISO hold after SCK Client - 13 - ns
tSOSS MISO setup after SS low Client - 11 - ns
tSOSH MISO hold after SS low Client - 8.0 - ns
Note:
1. These parameters are for design guidance only and are not production tested.
33.14 TWI
Figure 33-8. TWI - Timing Requirements
tHIGH tLOW
tOF tSP tR
SCL tSU;STA tHD ;STA tSU ;DAT tHD ;DAT tSU ;STO tBUF
SDA
S P S
...........continued
Symbol Description Condition Min. Typ. Max. Unit
VOL Output low voltage Iload = 20 mA, Fast mode+ - - 0.2 × VDD V
Iload = 3 mA, Normal mode, VDD > - - 0.4V
2V
Iload = 3 mA, Normal mode, VDD ≤ - - 0.2 × VDD
2V
IOL Low-level output fSCL ≤ 400 kHz, VOL = 0.4V 3 - - mA
current
fSCL ≤ 1 MHz, VOL = 0.4V 20 - -
CB Capacitive load for fSCL ≤ 100 kHz - - 400 pF
each bus line
fSCL ≤ 400 kHz - - 400
fSCL ≤ 1 MHz - - 550
tR Rise time for both fSCL ≤ 100 kHz - - 1000 ns
SDA and SCL
fSCL ≤ 400 kHz 20 - 300
fSCL ≤ 1 MHz - - 120
tOF Output fall time from 10 pF < capacitance fSCL ≤ 100 - 250 ns
VIHmin to VILmax of bus line < 400 pF kHz
fSCL ≤ 400 20 × (VDD/ - 250
kHz 5.5V)
fSCL ≤ 1 20 × (VDD/ - 120
MHz 5.5V)
tSP Spikes suppressed by 0 - 50 ns
the input filter
IL Input current for each 0.1×VDD < VI < 0.9×VDD - - 1 µA
I/O pin
CI Capacitance for each - - 10 pF
I/O pin
RP_TWI Value of external pull- fSCL ≤ 100 kHz (VDD - - 1000 ns/ Ω
up resistor VOL(max)) /IO (0.8473 × CB)
L
...........continued
Symbol Description Condition Min. Typ. Max. Unit
tLOW Low period of SCL fSCL ≤ 100 kHz 4.7 - - µs
Clock
fSCL ≤ 400 kHz 1.3 - -
fSCL ≤ 1 MHz 0.5 - -
tHIGH High period of SCL fSCL ≤ 100 kHz 4.0 - - µs
Clock
fSCL ≤ 400 kHz 0.6 - -
fSCL ≤ 1 MHz 0.26 - -
tSU;STA Setup time for fSCL ≤ 100 kHz 4.7 - - µs
a repeated Start
fSCL ≤ 400 kHz 0.6 - -
condition
fSCL ≤ 1 MHz 0.26 - -
- 3 - TSCL
tHD;DAT Data hold time fSCL ≤ 100 kHz 0 - 3.45 µs
fSCL ≤ 400 kHz 0 - 0.9
fSCL ≤ 1 MHz 0 - 0.45
tSU;DAT Data setup time fSCL ≤ 100 kHz 250 - - ns
fSCL ≤ 400 kHz 100 - -
fSCL ≤ 1 MHz 50 - -
tSU;STO Setup time for Stop fSCL ≤ 100 kHz 4 - - µs
condition
fSCL ≤ 400 kHz 0.6 - -
fSCL ≤ 1 MHz 0.26 - -
- 2 - TSCL
tBUF Bus free time fSCL ≤ 100 kHz 4.7 - - µs
between a Stop and
fSCL ≤ 400 kHz 1.3 - -
Start condition
fSCL ≤ 1 MHz 0.5 - -
- 2 - TSCL
Note:
1. These parameters are for design guidance only and are not production tested.
tHD;DAT Data hold time Client(4) All Frequencies SDAHOLD = 0x00 90 150 220 ns
Notes:
1. These parameters are for design guidance only and are not covered by production test limits.
2. SDAHOLD is the data hold time after the SCL signal is detected as being low. The actual hold time is,
therefore, higher than the configured hold time.
3. For Host mode, the data hold time is whatever is largest of the following:
– 4×tCLK_PER + 50 ns (typical)
– SDAHOLD configuration + SCL filter delay
4. For Client mode, the hold time is given by:
– SDAHOLD configuration + SCL filter delay
33.15 VREF
Table 33-21. Internal Voltage Reference Characteristics(1)
Note:
1. These parameters are for design guidance only and are not production tested.
Notes:
1. These values are based on characterization and not covered by production test limits.
2. The symbols xVxxx refer to the respective values of the REFSEL bit field in the ADC0.CTRLC register.
Table 33-23. AC Internal Voltage Reference Characteristics(1)
Notes:
1. These values are based on characterization and not covered by production test limits.
2. The symbols xVxxx refer to the respective values of the AC0REFSEL bit field in the VREF.CTRLA register.
33.16 ADC
Operating conditions:
• TA = [-40, 125]°C
• Sample rate defined for SAMPDUR = 0x02 with ADC in Free-Running mode
• Applies for all allowed combinations of VREF selections and sample rates, unless otherwise specified
• Characteristics are identical with and without PGA enabled, unless otherwise specified
Table 33-24. Power Supply, Reference and Input Range
Note:
1. These values are based on characterization and are not covered by production test limits.
Table 33-27. Accuracy Characteristics Internal Reference(1)
Note:
1. These values are based on characterization and are not covered by production test limits.
Note:
1. These values are based on characterization and are not covered by production test limits.
33.17 TEMPSENSE
Operating Conditions:
• VDD = 3V
• TA = 25°C, unless otherwise specified
Table 33-29. Temperature Sensor, Accuracy Characteristics
Notes:
1. These values are based on characterization and not covered by production test limits.
2. Characteristics over temperature can be found in the Typical Characteristics section.
33.18 AC
Table 33-30. Analog Comparator Characteristics, Low-Power Mode Disabled
...........continued
Symbol Description Condition Min. Typ. Max. Unit
VHYS Hysteresis HYSMODE = 0x0 - 0 - mV
HYSMODE = 0x1 - 10 -
HYSMODE = 0x2 - 30 -
HYSMODE = 0x3 - 55 -
HYSMODE = 0x1 - 10 -
HYSMODE = 0x2 - 40 -
HYSMODE = 0x3 - 80 -
33.19 UPDI
Figure 33-9. UPDI Enable Sequence (1)
1 Drive low from debugger to request UPDI clock
2 UPDI clock ready; Communication channel ready.
UPDIPAD St D0 D1 D2 D3 D4 D5 D6 D7 Sp
UPDI.rxd (Ignore)
2
UPDI.txd Hi-Z Hi-Z
UPDI.txd = 0
t UPDI
debugger.
Hi-Z Hi-Z
UPDI.txd
Debugger.txd = 0 Debugger.txd = z.
t Deb0 t DebZ
Note:
1. These parameters are for design guidance only and are not covered by production test limits.
Table 33-33. UPDI Max. Bit Rates vs. VDD(1)
Note:
1. These parameters are for design guidance only and are not covered by production test limits.
Notes:
1. This is the typical chip erase time for devices with 8 KB of Flash.
2. This is the typical chip erase time for devices with 4 KB of Flash.
12.0 V DD [V]
1.8
11.0
2.2
10.0 2.7
3
9.0
3.6
8.0 4.2
7.0 5
I DD [mA]
5.5
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0 2 4 6 8 10 12 14 16 18 20
Frequency [MHz]
Figure 34-2. Active Supply Current vs. Frequency (0.1-1.0 MHz) at T = 25°C (EXTCLK)
600 V DD [V]
1.8
2.2
500 2.7
3
3.6
400 4.2
5
I DD [µA]
5.5
300
200
100
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency [MHz]
12.0 V DD [V]
4.5
11.0
5
10.0 5.5
9.0
8.0
7.0
I DD [mA]
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-4. Active Supply Current vs. Temperature (f = 16 MHz OSC20M)
10.0 V DD [V]
4
9.0 4.5
5
8.0
5.5
7.0
6.0
I DD [mA]
5.0
4.0
3.0
2.0
1.0
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-5. Active Supply Current vs. VDD (f = [1.25, 20] MHz OSC20M) at T = 25°C
6.0
5.0
4.0
3.0
2.0
1.0
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD [V]
Figure 34-6. Active Supply Current vs. VDD (f = [1, 16] MHz OSC20M) at T = 25 °C
6.0
5.0
4.0
3.0
2.0
1.0
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD [V]
40 Temperature [°C]
-40
36 25
85
32
125
28
24
I DD [µA]
20
16
12
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD [V]
3.0 V DD [V]
1.8
2.2
2.5 2.7
3
3.6
2.0 4.2
5
I DD [mA]
5.5
1.5
1.0
0.5
0.0
0 2 4 6 8 10 12 14 16 18 20
Frequency [MHz]
Figure 34-9. Idle Supply Current vs. Frequency [0.1, 1.0] MHz at T = 25°C (EXTCLK)
150 V DD [V]
1.8
2.2
125 2.7
3
3.6
100 4.2
5
I DD [µA]
5.5
75
50
25
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency [MHz]
Figure 34-10. Idle Supply Current vs. Temperature (f = 20 MHz OSC20M)
3.0 V DD [V]
4.5
5
2.5 5.5
2.0
I DD [mA]
1.5
1.0
0.5
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
3.0 V DD [V]
4
4.5
2.5 5
5.5
2.0
I DD [mA]
1.5
1.0
0.5
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-12. Idle Supply Current vs. VDD (f = [1.25, 20] MHz OSC20M) at T = 25°C
1.5
1.0
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD [V]
Figure 34-13. Idle Supply Current vs. VDD (f = [1, 16] MHz OSC20M) at T = 25 °C
1.5
1.0
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD [V]
Figure 34-14. Idle Supply Current vs. VDD (f = 32 kHz OSCULP32K)
14 Temperature [°C]
-40
25
12
85
125
10
8
I DD [µA]
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD [V]
6.0
I DD [µA]
5.0
4.0
3.0
2.0
1.0
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD [V]
Figure 34-16. Standby Supply Current vs. VDD (RTC Running with Internal OSCULP32K)
6.0
I DD [µA]
5.0
4.0
3.0
2.0
1.0
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD [V]
Figure 34-17. Standby Supply Current vs. VDD (Sampled BOD Running at 1 kHz)
6.0
I DD [µA]
5.0
4.0
3.0
2.0
1.0
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD [V]
Figure 34-18. Standby Supply Current vs. VDD (Sampled BOD Running at 125 Hz)
6.0
I DD [µA]
5.0
4.0
3.0
2.0
1.0
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD [V]
5.0 V DD [V]
1.8
4.5 2.2
2.7
4.0
3
3.5 3.6
4.2
3.0 5
I DD [µA]
5.5
2.5
2.0
1.5
1.0
0.5
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-20. Power Down Supply Current vs. VDD (All Functions Disabled)
3.0
I DD [µA]
2.5
2.0
1.5
1.0
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD [V]
0.5
0.4
0.3
0.2
0.1
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VDD [V]
34.2 GPIO
1.0
0.8
0.6
0.4
0.2
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 34-23. I/O Pin Input Threshold Voltage vs. VDD (T = 25°C)
75 Treshold
VIH
70 VIL
65
60
55
Threshold [%]
50
45
40
35
30
25
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 34-24. I/O Pin Input Threshold Voltage vs. VDD (VIH)
75 Temperature [°C]
-40
70 0
25
65 70
85
60
105
55 125
Threshold [%]
50
45
40
35
30
25
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 34-25. I/O Pin Input Threshold Voltage vs. VDD (VIL)
75 Temperature [°C]
-40
70 0
25
65 70
85
60
105
55 125
Threshold [%]
50
45
40
35
30
25
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
0.25
0.20
0.15
0.10
0.05
0.00
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Sink current [mA]
Figure 34-27. I/O Pin Output Voltage vs. Sink Current (VDD = 3.0V)
0.30 125
0.25
0.20
0.15
0.10
0.05
0.00
0 1 2 3 4 5 6 7 8 9 10
Sink current [mA]
Figure 34-28. I/O Pin Output Voltage vs. Sink Current (VDD = 5.0V)
0.5
0.4
0.3
0.2
0.1
0.0
0 2 4 6 8 10 12 14 16 18 20
Sink current [mA]
Figure 34-29. I/O Pin Output Voltage vs. Sink Current (T = 25°C)
0.5
0.4
0.3
0.2
0.1
0.0
0 2 4 6 8 10 12 14 16 18 20
Sink current [mA]
Figure 34-30. I/O Pin Output Voltage vs. Source Current (VDD = 1.8V)
1.55
1.50
1.45
1.40
1.35
1.30
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Source current [mA]
Figure 34-31. I/O Pin Output Voltage vs. Source Current (VDD = 3.0V)
2.5
2.4
2.3
2.2
2.1
2.0
0 1 2 3 4 5 6 7 8 9 10
Source current [mA]
Figure 34-32. I/O Pin Output Voltage vs. Source Current (VDD = 5.0V)
4.5
4.4
4.3
4.2
4.1
4.0
0 2 4 6 8 10 12 14 16 18 20
Source current [mA]
Figure 34-33. I/O Pin Output Voltage vs. Source Current (T = 25°C)
2.5
2.0
1.5
1.0
0.5
0.0
0 2 4 6 8 10 12 14 16 18 20
Source current [mA]
1.0
0.8
0.5
0.3
0.0
0 5 10 15 20 25 30 35 40 45 50
Pull-up resistor current [µA]
Figure 34-35. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VDD = 3.0V)
2.0
1.8
1.5
1.3
1.0
0 5 10 15 20 25 30 35 40 45 50
Pull-up resistor current [µA]
Figure 34-36. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VDD = 5.0V)
4.0
3.8
3.5
3.3
3.0
0 5 10 15 20 25 30 35 40 45 50
Pull-up resistor current [µA]
3.0
VREF
1.024
2.5
2.048
2.0 4.096
1.5
1.0
VREF Error [%]
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-38. VREF Accuracy vs. VDD at T = 25°C, Internal References
3.0
VREF
1.024
2.5
2.048
2.0 4.096
1.5
1.0
VREF Error [%]
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
50 Temperature [°C]
-40
45 0
25
40 70
85
35
105
30 125
IDD [µA]
25
20
15
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Figure 34-40. BOD Current vs. VDD (Sampled BOD at 125 Hz)
2.5
2.0
1.5
1.0
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
2.5
2.0
1.5
1.0
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
1.90
Falling VDD
1.88 Rising VDD
1.86
1.84
1.82
BOD level [V]
1.80
1.78
1.76
1.74
1.72
1.70
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
2.70
2.68
BOD level [V]
2.66
2.64
2.62
2.60
2.58
2.56
4.30
4.28
BOD level [V]
4.26
4.24
4.22
4.20
4.18
4.16
15.0
VREF
14.0 1.024
2.048
13.0
12.0
Absolute Accuracy [LSb]
11.0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-46. Absolute Accuracy vs. Temperature (VDD = 5.0V, fADC = 145 ksps), Differential, REFSEL =
Internal Reference
30
VREF
28 1.024
2.048
26
4.096
24 VDD
22
Absolute Accuracy [LSb]
20
18
16
14
12
10
8
6
4
2
0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-47. Absolute Accuracy vs. VDD (fADC = 145 ksps) at T = 25°C, Differential, REFSEL = External
Reference
15.0
VREF
14.0 1.024
2.048
13.0
12.0
11.0
Absolute Accuracy [LSb]
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
Figure 34-48. Absolute Accuracy vs. VDD (fADC = 145 ksps) at T = 25°C, Differential, REFSEL = Internal
Reference
30
VREF
28 1.024
2.048
26
4.096
24 VDD
22
Absolute Accuracy [LSb]
20
18
16
14
12
10
8
6
4
2
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
34.5.2 DNL
Figure 34-49. DNL vs. Code (VDD = 5.0V, T = 25°C, fADC = 145 ksps), Differential, External 2.048V Reference
2.0
VREF
1.8 2.048
1.5
1.3
1.0
0.8
0.5
DNL [LSb]
0.3
0.0
-0.3
-0.5
-0.8
-1.0
-1.3
-1.5
-1.8
-2.0
-2048 -1536 -1024 -512 0 512 1024 1536
Code
Figure 34-50. DNL vs. Temperature (VDD = 5.0V, fADC = 145 ksps), Differential, REFSEL = External Reference
2.0
VREF
1.024
1.8 2.048
1.5
1.3
DNL [LSb]
1.0
0.8
0.5
0.3
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-51. DNL vs. Temperature (VDD = 5.0V, fADC = 145 ksps), Differential, REFSEL = Internal Reference
2.0
VREF
1.024
1.8 2.048
4.096
VDD
1.5
1.3
DNL [LSb]
1.0
0.8
0.5
0.3
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-52. DNL vs. VDD (fADC = 145 ksps) at T = 25°C, Differential, REFSEL = External Reference
2.0
VREF
1.024
1.8 2.048
1.5
1.3
DNL [LSb]
1.0
0.8
0.5
0.3
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
Figure 34-53. DNL vs. VDD (fADC = 145 ksps) at T = 25°C, Differential, REFSEL = Internal Reference
2.0
VREF
1.024
1.8 2.048
4.096
VDD
1.5
1.3
DNL [LSb]
1.0
0.8
0.5
0.3
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
5.0
VREF
4.5 1.024
4.0 2.048
3.5
3.0
2.5
2.0
1.5
Gain Error [LSb]
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-55. Gain Error vs. Temperature (VDD = 5.0V, fADC = 145 ksps), Differential, REFSEL = Internal
Reference
30
VREF
1.024
25
2.048
20 4.096
VDD
15
10
Gain Error [LSb]
0
-5
-10
-15
-20
-25
-30
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-56. Gain Error vs. VDD (fADC = 145 ksps) at T = 25°C, Differential, REFSEL = External Reference
5.0
VREF
4.5 1.024
4.0 2.048
3.5
3.0
2.5
2.0
1.5
Gain Error [LSb]
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
Figure 34-57. Gain Error vs. VDD (fADC = 145 ksps) at T = 25°C, Differential, REFSEL = Internal Reference
30
VREF
1.024
25
2.048
20 4.096
VDD
15
10
Gain Error [LSb]
0
-5
-10
-15
-20
-25
-30
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
34.5.4 INL
Figure 34-58. INL vs. Code (VDD = 5.0V, T = 25°C, fADC = 145 ksps), Differential, External 2.048V Reference
2.0
VREF
1.8 2.048
1.5
1.3
1.0
0.8
0.5
INL [LSb]
0.3
0.0
-0.3
-0.5
-0.8
-1.0
-1.3
-1.5
-1.8
-2.0
-2048 -1536 -1024 -512 0 512 1024 1536
Code
Figure 34-59. INL vs. Temperature (VDD = 5.0V, fADC = 145 ksps), Differential, REFSEL = External Reference
2.0
VREF
1.024
1.8 2.048
1.5
1.3
INL [LSb]
1.0
0.8
0.5
0.3
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-60. INL vs. Temperature (VDD = 5.0V, fADC = 145 ksps), Differential, REFSEL = Internal Reference
2.0
VREF
1.024
1.8 2.048
4.096
VDD
1.5
1.3
INL [LSb]
1.0
0.8
0.5
0.3
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-61. INL vs. VDD (fADC = 145 ksps) at T = 25°C, Differential, REFSEL = External Reference
2.0
VREF
1.024
1.8 2.048
1.5
1.3
INL [LSb]
1.0
0.8
0.5
0.3
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
Figure 34-62. INL vs. VDD (fADC = 145 ksps) at T = 25°C, Differential, REFSEL = Internal Reference
2.0
VREF
1.024
1.8 2.048
4.096
VDD
1.5
1.3
INL [LSb]
1.0
0.8
0.5
0.3
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
5.0
VREF
1.024
4.5 2.048
4.0
3.5
Offset Error [LSb]
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-64. Offset Error vs. Temperature (VDD = 5.0V, fADC = 145 ksps), Differential, REFSEL = Internal
Reference
5.0
VREF
1.024
4.5 2.048
4.096
4.0 VDD
3.5
Offset Error [LSb]
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-65. Offset Error vs. VDD (fADC = 145 ksps) at T = 25°C, Differential, REFSEL = External Reference
5.0
VREF
1.024
4.5 2.048
4.0
3.5
Offset Error [LSb]
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
Figure 34-66. Offset Error vs. VDD (fADC = 145 ksps) at T = 25°C, Differential, REFSEL = Internal Reference
5.0
VREF
1.024
4.5 2.048
4.096
4.0 VDD
3.5
Offset Error [LSb]
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
0.6
GAIN
1X_Gain
0.4
2X_Gain
0.2 4X_Gain
8X_Gain
0.0
16X_Gain
-0.2
Gain Error [%]
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-68. Gain Error vs. VDD at T = 25°C, VCM=min
0.6
GAIN
1X_Gain
0.4
2X_Gain
0.2 4X_Gain
8X_Gain
0.0
16X_Gain
-0.2
Gain Error [%]
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
20
GAIN
18 1X_Gain
16 2X_Gain
14 4X_Gain
12 8X_Gain
10
8
16X_Gain
Midcode Offset [LSb]
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
Figure 34-70. Offset Error vs. VDD at T = 25°C, VCM=min
20
GAIN
18 1X_Gain
16 2X_Gain
14 4X_Gain
12 8X_Gain
10
8
16X_Gain
Midcode Offset [LSb]
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
12 Legend
-3σ
+3σ
10 Mean
Temperature Sensor Error [°C]
34.7 AC Characteristics
80
70
60
50
40
30
20
10
0
-10
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vcommon mode [V]
Figure 34-73. Hysteresis over CM voltage and HYSMODE at VDD = 5V and Temperature 25C in Low Power
Mode Enabled
80
70
60
50
40
30
20
10
0
-10
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vcommon mode [V]
30 Temperature [°C]
-40
-20
25 0
25
55
20 85
Hysteresis [mV]
105
125
15
10
0
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vcommon mode [V]
Figure 34-75. Hysteresis over CM Voltage and Temperature at VDD = 5V and HYSMODE = 0x1 in Low Power
Mode Enabled
30 Temperature [°C]
-40
-20
25 0
25
55
20 85
Hysteresis [mV]
105
125
15
10
0
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vcommon mode [V]
Figure 34-76. Hysteresis over CM Voltage and Temperature at VDD = 5V and HYSMODE = 0x2 in Low Power
Mode Disabled
70 Temperature [°C]
-40
65
-20
60 0
25
55
55
50 85
Hysteresis [mV]
45 105
125
40
35
30
25
20
15
10
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vcommon mode [V]
Figure 34-77. Hysteresis over CM Voltage and Temperature at VDD = 5V and HYSMODE = 0x2 in Low Power
Mode Enabled
70 Temperature [°C]
-40
65
-20
60 0
25
55
55
50 85
Hysteresis [mV]
45 105
125
40
35
30
25
20
15
10
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vcommon mode [V]
Figure 34-78. Hysteresis over CM Voltage and Temperature at VDD = 5V and HYSMODE = 0x3 in Low Power
Mode Disabled
90 105
125
80
70
60
50
40
30
20
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vcommon mode [V]
Figure 34-79. Hysteresis over CM Voltage and Temperature at VDD = 5V and HYSMODE = 0x3 in Low Power
Mode Enabled
90 105
125
80
70
60
50
40
30
20
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vcommon mode [V]
3.0
Offset [mV]
2.5
2.0
1.5
1.0
0.5
0.0
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vcommon mode [V]
Figure 34-81. Offset over CM Voltage and HYSMODE at VDD = 5V and Temperature 25°C in Low Power Mode
Enabled
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vcommon mode [V]
Figure 34-82. Offset over CM Voltage and Temperature at VDD = 5V and HYSMODE = 0x1 in Low Power Mode
Disabled
125
2.5
2.0
1.5
1.0
0.5
0.0
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vcommon mode [V]
Figure 34-83. Offset over CM Voltage and Temperature at VDD = 5V and HYSMODE = 0x1 in Low Power Mode
Enabled
125
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vcommon mode [V]
105
125
0.8
0.6
0.4
0.2
0.0
0 16 32 48 64 80 96 112 128
OSCCAL [x1]
Figure 34-85. OSC20M Internal Oscillator: Frequency vs. Calibration Value (VDD = 3V)
32 Temperature [°C]
-40
30 -20
0
28 25
70
26
85
24 105
125
22
20
18
16
14
12
10
0 16 32 48 64 80 96 112 128
OSCCAL [x1]
20.0
19.9
19.8
19.7
19.6
19.5
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
20.0
19.9
19.8
19.7
19.6
19.5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
36.0 5.5
35.0
34.0
33.0
32.0
31.0
30.0
-40 -20 0 20 40 60 80 100 120
Temperature [°C]
36.0
125
35.0
34.0
33.0
32.0
31.0
30.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
Ordering Code(1) Flash/SRAM Pin Count Package Type(2) Supply Voltage Temperature Range Carrier Type
ATTINY824-SSF 8 KB/1 KB 14 SOIC 1.8V-5.5V -40°C to +125°C Tube
ATTINY824-SSFR 8 KB/1 KB 14 SOIC 1.8V-5.5V -40°C to +125°C Tape & Reel
ATTINY824-SSU 8 KB/1 KB 14 SOIC 1.8V-5.5V -40°C to +85°C Tube
ATTINY824-SSUR 8 KB/1 KB 14 SOIC 1.8V-5.5V -40°C to +85°C Tape & Reel
ATTINY824-XF 8 KB/1 KB 14 TSSOP 1.8V-5.5V -40°C to +125°C Tube
ATTINY824-XFR 8 KB/1 KB 14 TSSOP 1.8V-5.5V -40°C to +125°C Tape & Reel
...........continued
Ordering Code(1) Flash/SRAM Pin Count Package Type(2) Supply Voltage Temperature Range Carrier Type
ATTINY824-XU 8 KB/1 KB 14 TSSOP 1.8V-5.5V -40°C to +85°C Tube
ATTINY824-XUR 8 KB/1 KB 14 TSSOP 1.8V-5.5V -40°C to +85°C Tape & Reel
ATTINY826-MF 8 KB/1 KB 20 VQFN 1.8V-5.5V -40°C to +125°C Tray
ATTINY826-MFR 8 KB/1 KB 20 VQFN 1.8V-5.5V -40°C to +125°C Tape & Reel
ATTINY826-MU 8 KB/1 KB 20 VQFN 1.8V-5.5V -40°C to +85°C Tray
ATTINY826-MUR 8 KB/1 KB 20 VQFN 1.8V-5.5V -40°C to +85°C Tape & Reel
ATTINY826-SF 8 KB/1 KB 20 SOIC 1.8V-5.5V -40°C to +125°C Tube
ATTINY826-SF 8 KB/1 KB 20 SSOP 1.8V-5.5V -40°C to +125°C Tape & Reel
ATTINY826-SFR 8 KB/1 KB 20 SOIC 1.8V-5.5V -40°C to +125°C Tube
ATTINY826-SU 8 KB/1 KB 20 SOIC 1.8V-5.5V -40°C to +85°C Tape & Reel
ATTINY826-SUR 8 KB/1 KB 20 SOIC 1.8V-5.5V -40°C to +85°C Tube
ATTINY826-XFR 8 KB/1 KB 20 SSOP 1.8V-5.5V -40°C to +125°C Tape & Reel
ATTINY826-XU 8 KB/1 KB 20 SSOP 1.8V-5.5V -40°C to +85°C Tube
ATTINY826-XUR 8 KB/1 KB 20 SSOP 1.8V-5.5V -40°C to +85°C Tape & Reel
ATTINY827-MF 8 KB/1 KB 24 VQFN 1.8V-5.5V -40°C to +125°C Tray
ATTINY827-MFR 8 KB/1 KB 24 VQFN 1.8V-5.5V -40°C to +125°C Tape & Reel
ATTINY827-MU 8 KB/1 KB 24 VQFN 1.8V-5.5V -40°C to +85°C Tray
ATTINY827-MUR 8 KB/1 KB 24 VQFN 1.8V-5.5V -40°C to +85°C Tape & Reel
Notes:
1. Pb-free packing complies with the European Directive for Restrictions of Hazardous Substances (RoHS
directive). Also halide-free and completely green.
2. Package outline drawings can be found in the Package Drawings section.
Note: The Tape & Reel identifier only appears in the catalog part number description. Use this identifier for ordering
purposes. Check with your Microchip Sales Office for package availability with the Tape and Reel option.
Note: The VAO variants have been designed, manufactured, tested, and qualified per AEC-Q100 requirements
for automotive applications. These products may use a different package than non-VAO parts and have additional
specifications in their Electrical Characteristics.
Note:
1. This package type has wettable flanks and will only be available for automotive (VAO) ordering codes.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
XXXXXXXXXXX ATTINY824
YYWWNNN 2114321
XXXXXXXX TINY824
YYWW 2114
NNN 321
XXXXXXXXXXXXXX ATTINY826
YYWWNNN 2114321
XXXXXXXXXXX ATTINY826
YYWWNNN 2114321
XXX 826
YYWW 2114
PIN 1 PIN 1
NNN 321
XXX 826
YYWW 2114
PIN 1 PIN 1
NNN 321
36.2.7 24-Pin VQFN
XXXXX TINY
XXXXXX 827
PIN 1 PIN 1
YWWNNN 114321
XXXXX TINY
XXXXXX 827
PIN 1 PIN 1
YWWNNN 114321
Package Drawings
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A NOTE 5 D
N
E
2
E2
2
E1 E
2X
0.10 C D
2X N/2 TIPS
NOTE 1 1 2 3 0.20 C
e NX b
B NOTE 5 0.25 C A–B D
TOP VIEW
0.10 C
C A A2
SEATING
PLANE 14X
A1 SIDE VIEW 0.10 C
h h
H R0.13
R0.13
SEE VIEW C
L
VIEW A–A (L1)
VIEW C
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e 1.27 BSC
Overall Height A - - 1.75
Molded Package Thickness A2 1.25 - -
Standoff § A1 0.10 - 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 8.65 BSC
Chamfer (Optional) h 0.25 - 0.50
Foot Length L 0.40 - 1.27
Footprint L1 1.04 REF
Lead Angle 0° - -
Foot Angle 0° - 8°
Lead Thickness c 0.10 - 0.25
Lead Width b 0.31 - 0.51
Mold Draft Angle Top 5° - 15°
Mold Draft Angle Bottom 5° - 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14
SILK SCREEN
1 2
X
E
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 1.27 BSC
Contact Pad Spacing C 5.40
Contact Pad Width (X14) X 0.60
Contact Pad Length (X14) Y 1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D A B
N
E
2
E1
2
E1 E
2X 7 TIPS
1 2 0.20 C B A
e
TOP VIEW
A
C A2 A
SEATING
PLANE
14X 14X b A1
A
0.10 C 0.10 C B A
SIDE VIEW
SEE DETAIL B
VIEW A–A
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(θ2)
R1
H
R2
L θ1
(L1)
(θ3)
DETAIL B
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 14
Pitch e 0.65 BSC
Overall Height A – – 1.20
Standoff A1 0.05 – 0.15
Molded Package Thickness A2 0.80 1.00 1.05
Overall Length D 4.90 5.00 5.10
Overall Width E 6.40 BSC
Molded Package Width E1 4.30 4.40 4.50
Terminal Width b 0.19 – 0.30
Terminal Thickness c 0.09 – 0.20
Terminal Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Lead Bend Radius R1 0.09 – –
Lead Bend Radius R2 0.09 – –
Foot Angle θ1 0° – 8°
Mold Draft Angle θ2 – 12° REF –
Mold Draft Angle θ3 – 12° REF –
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
X
E
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
E
2
E1
2
E1 E
2X 10 TIPS
NOTE 1 0.33 C
B 20X b
e 0.25 C A-B D
TOP VIEW
0.10 C A
A2 A C
SEATING
PLANE
A1 20X A
SIDE VIEW 0.10 C
h
SEE DETAIL B
VIEW A–A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
θ2
θ1
R1
H R
θ3 θ
L
(L1)
DETAIL B
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 20
Pitch e 1.27 BSC
Overall Height A - - 2.65
Standoff § A1 0.10 - 0.30
Molded Package Thickness A2 2.05 - -
Overall Length D 12.80 BSC
Overall Width E 10.30 BSC
Molded Package Width E1 7.50 BSC
Terminal Width b 0.31 - 0.51
Terminal Thickness c 0.25 - 0.75
Corner Chamfer h 0.25 - 0.41
Terminal Length L 0.41 0.65 0.89
Footprint L1 1.40 REF
Lead Bend Radius R1 0.07 - -
Lead Bend Radius R2 0.07 - -
Foot Angle θ 0° - 8°
Lead Angle θ1 0° - -
Mold Draft Angle θ2 5° - 15°
Mold Draft Angle θ3 5° - 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
or protrusion, which shall not exceed 0.25 mm per side.
4. § Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
G1
20
SILK SCREEN
C G
1 2
X
E
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 1.27 BSC
Contact Pad Spacing C 9.40
Contact Pad Width (X20) X 0.60
Contact Pad Length (X20) Y 1.95
Contact Pad to Contact Pad G 0.67
Contact Pad to Contact Pad G1 7.45
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
D
N
E1
NOTE 1
1 2
e
b
c
A A2
φ
A1
L1 L
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 20
Pitch e 0.65 BSC
Overall Height A – – 2.00
Molded Package Thickness A2 1.65 1.75 1.85
Standoff A1 0.05 – –
Overall Width E 7.40 7.80 8.20
Molded Package Width E1 5.00 5.30 5.60
Overall Length D 6.90 7.20 7.50
Foot Length L 0.55 0.75 0.95
Footprint L1 1.25 REF
Lead Thickness c 0.09 – 0.25
Foot Angle φ 0° 4° 8°
Lead Width b 0.22 – 0.38
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-072B
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.65 0.45
SILK SCREEN
c
Y1
G
X1
E
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.65 BSC
Contact Pad Spacing C 7.20
Contact Pad Width (X20) X1 0.45
Contact Pad Length (X20) Y1 1.75
Distance Between Pads G 0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
20-Lead Very Thin Plastic Quad Flat, No Lead Package (REB) - 3x3 mm Body [VQFN]
With 1.7 mm Exposed Pad; Atmel Legacy Global Package Code ZCL
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
16X
0.08 C
0.10 C
D A B
NOTE 1
N
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
A1
0.10 C TOP VIEW
(A3)
0.10 C A B
D2 A
SEATING
C
PLANE
SIDE VIEW
0.10 C A B
E2
2
(CH)
1
NOTE 1 K
N
L 20X b
e 0.10 C A B
0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-21380 Rev A Sheet 1 of 2
20-Lead Very Thin Plastic Quad Flat, No Lead Package (REB) - 3x3 mm Body [VQFN]
With 1.7 mm Exposed Pad; Atmel Legacy Global Package Code ZCL
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 20
Pitch e 0.40 BSC
Overall Height A 0.80 0.85 0.90
Standoff A1 0.00 0.035 0.05
Terminal Thickness A3 0.203 REF
Overall Length D 3.00 BSC
Exposed Pad Length D2 1.60 1.70 1.80
Overall Width E 3.00 BSC
Exposed Pad Width E2 1.60 1.70 1.80
Terminal Width b 0.15 0.20 0.25
Terminal Length L 0.35 0.40 0.45
Terminal-to-Exposed-Pad K 0.20 - -
Pin 1 Index Chamfer CH 0.35 REF
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
20-Lead Very Thin Plastic Quad Flat, No Lead Package (REB) - 3x3 mm Body [VQFN]
With 1.7 mm Exposed Pad; Atmel Legacy Global Package Code ZCL
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
ØV
G2
C2 Y2 EV
G1
Y1
X1
SILK SCREEN E
20X
0.08 C
D A 0.10 C
B
NOTE 1
N
E
(DATUM B)
(DATUM A)
2X
0.05 C
2X
A1
0.05 C TOP VIEW
(A3)
0.10 C A B A
D2 SEATING
C
PLANE
SIDE VIEW
0.10 C A B
DETAIL A
A A
E2
A4
2
1
K STEPPED
WETTABLE
D3 FLANK
NOTE 1
N
SECTION A-A
L 20X b
e 0.10 C A B
0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-476-2LX Rev C Sheet 1 of 2
20-Lead Very Thin Plastic Quad Flat, No Lead Package (2LX) - 3x3 mm Body [VQFN]
With 1.7 mm Exposed Pad and Stepped Wettable Flanks
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DETAIL 1
ALTERNATE TERMINAL
CONFIGURATIONS
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 20
Pitch e 0.40 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Terminal Thickness A3 0.203 REF
Overall Length D 3.00 BSC
Exposed Pad Length D2 1.60 1.70 1.80
Overall Width E 3.00 BSC
Exposed Pad Width E2 1.60 1.70 1.80
Terminal Width b 0.15 0.20 0.25
Terminal Length L 0.35 0.40 0.45
Terminal-to-Exposed-Pad K 0.20 - -
Wettable Flank Step Length D3 - - 0.085
Wettable Flank Step Height A4 0.10 - 0.19
Dimensions D3 and A4 above apply to all new products released after
November 1, and all products shipped after January 1, 2019, and supersede
dimensions D3 and A4 below.
No physical changes are being made to any package; this update is to align
cosmetic and tolerance variations from existing suppliers.
Wettable Flank Step Length D3 0.035 0.06 0.085
Wettable Flank Step Height A4 0.10 - 0.19
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
20-Lead Very Thin Plastic Quad Flat, No Lead Package (2LX) - 3x3 mm Body [VQFN]
With 1.7 mm Exposed Pad and Stepped Wettable Flanks
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
20
ØV
1
G2
2
C2 Y2 EV
G1
Y1
X1
SILK SCREEN E
24X
0.08 C
0.10 C
D A B
NOTE 1 N
E
(DATUM B)
(DATUM A)
2X
0.15 C
2X
0.15 C
TOP VIEW A1
(A3)
0.10 C A B
D2 A
SEATING
C
PLANE
SIDE VIEW
0.10 C A B
E2
e
2
2
NOTE 1
1
N
K
L 24X b
e 0.10 C A B
0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-21386 Rev A Sheet 1 of 2
24-Lead Very Thin Plastic Quad Flat, No Lead Package (RLB) - 4x4 mm Body [VQFN]
Atmel Legacy Global Package Code ZHA
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 24
Pitch e 0.50 BSC
Overall Height A 0.80 0.85 0.90
Standoff A1 0.00 - 0.05
Terminal Thickness A3 0.203 REF
Overall Length D 4.00 BSC
Exposed Pad Length D2 2.45 2.60 2.75
Overall Width E 4.00 BSC
Exposed Pad Width E2 2.45 2.60 2.75
Terminal Width b 0.18 0.25 0.30
Terminal Length L 0.35 0.40 0.45
Terminal-to-Exposed-Pad K 0.20 - -
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
24-Lead Very Thin Plastic Quad Flat, No Lead Package (RLB) - 4x4 mm Body [VQFN]
Atmel Legacy Global Package Code ZHA
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
24
ØV
1
2 G2
C2 Y2
EV
G1
Y1
X1
SILK SCREEN E
24X
0.08 C
D A 0.10 C
NOTE 1 B
N
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
0.10 C
TOP VIEW A1
(A3)
0.10 C A B A
D2 SEATING
C
PLANE
SIDE VIEW
0.10 C A B
DETAIL A
E2
A4
e
2
2
A A
1
STEPPED
D3
WETTABLE
K SECTION A-A FLANK
N
L 24X b
e 0.10 C A B
0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-21483 Rev A Sheet 1 of 2
24-Lead Very Thin Plastic Quad Flat, No Lead Package (U3B) - 4x4 mm Body [VQFN]
With 2.6mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZCY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DETAIL 1
ALTERNATE TERMINAL
CONFIGURATIONS
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 24
Pitch e 0.50 BSC
Overall Height A 0.80 0.85 0.90
Standoff A1 0.00 0.035 0.05
Terminal Thickness A3 0.203 REF
Overall Length D 4.00 BSC
Exposed Pad Length D2 2.50 2.60 2.70
Overall Width E 4.00 BSC
Exposed Pad Width E2 2.50 2.60 2.70
Terminal Width b 0.20 0.25 0.30
Terminal Length L 0.35 0.40 0.45
Terminal-to-Exposed-Pad K 0.20 - -
Wettable Flank Step Length D3 - - 0.085
Wettable Flank Step Height A4 0.10 - 0.19
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
24-Lead Very Thin Plastic Quad Flat, No Lead Package (U3B) - 4x4 mm Body [VQFN]
With 2.6mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZCY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
ØV
G2
C2 Y2
EV
G1
Y1
X1
SILK SCREEN E
Customer Support
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Embedded Solutions Engineer (ESE)
• Technical Support
Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to
help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the website at: www.microchip.com/support
Note: The Tape & Reel identifier only appears in the catalog part number description. Use this identifier for ordering
purposes. Check with your Microchip Sales Office for package availability with the Tape and Reel option.
Note: The VAO variants have been designed, manufactured, tested, and qualified per AEC-Q100 requirements
for automotive applications. These products may use a different package than non-VAO parts and have additional
specifications in their Electrical Characteristics.
Legal Notice
This publication and the information herein may be used only with Microchip products, including to design, test,
and integrate Microchip products with your application. Use of this information in any other manner violates these
terms. Information regarding device applications is provided only for your convenience and may be superseded
by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your
local Microchip sales office for additional support or, obtain additional support at www.microchip.com/en-us/support/
design-help/client-support-services.
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS
OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY
OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED
WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE,
OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR
CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW,
MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE
WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR
THE INFORMATION.
Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees
to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting
from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights
unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,
BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity,
SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron,
and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed
Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC
Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra,
TimeProvider, TrueTime, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the
U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching,
BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime,
IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity,
JitterBlocker, Knob-on-Display, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified
logo, MPLIB, MPLINK, MultiTRAK, NetDetach, NVM Express, NVMe, Omniscient Code Generation, PICDEM,
PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-
ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher,
SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY,
ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, Symmcom, and Trusted Time are registered
trademarks of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2021, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved.
ISBN: 978-1-5224-9462-1