XST Rev Mandrade

XST User Guide for Virtex-4,
Virtex-5, Spartan-3, and Newer

CPLD Devices
UG627 (v 14.5) March 20, 2013
This document applies to the following software versions: ISE Design Suite 14.5 through 14.7
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Frontmatter
2 www.xilinx.com UG627 (v 14.5) March 20, 2013
Table of Contents
Chapter 1 About This Guide ......................................................................................11
Guide Overview................................................................................................... 11
Supported Devices ............................................................................................... 12
Chapter 2 Introduction to Xilinx Synthesis Technology (XST)...............................13

About XST ............................................................................................................ 13
Setting XST Options ............................................................................................ 13
Chapter 3 XST HDL Coding Techniques ..................................................................15

Signed and Unsigned Support in XST................................................................ 16
Registers HDL Coding Techniques..................................................................... 17
Latches HDL Coding Techniques........................................................................ 27
Tristates HDL Coding Techniques ...................................................................... 32
Counters HDL Coding Techniques..................................................................... 36
Accumulators HDL Coding Techniques ............................................................. 49
Shift Registers HDL Coding Techniques ........................................................... 53
Dynamic Shift Registers HDL Coding Techniques ........................................... 59
Multiplexers HDL Coding Techniques............................................................... 63
Decoders HDL Coding Techniques .................................................................... 72
Priority Encoders HDL Coding Techniques ....................................................... 78
Logical Shifters HDL Coding Techniques.......................................................... 81
Arithmetic Operators HDL Coding Techniques ................................................ 86
Adders, Subtractors, and Adders/Subtractors HDL Coding
Techniques.................................................................................................... 88
Comparators HDL Coding Techniques............................................................... 99
Multipliers HDL Coding Techniques ............................................................... 101
Sequential Complex Multipliers HDL Coding Techniques ............................ 105
Pipelined Multipliers HDL Coding Techniques.............................................. 109
Multiply Adder/Subtractors HDL Coding Techniques ................................... 116
Multiply Accumulate HDL Coding Techniques .............................................. 122
Dividers HDL Coding Techniques ................................................................... 128
Resource Sharing HDL Coding Techniques..................................................... 130
RAMs and ROMs HDL Coding Techniques .................................................... 133
ROMs Using Block RAM Resources HDL Coding Techniques ...................... 188
Pipelined Distributed RAM HDL Coding Techniques ................................... 195
FSM HDL Coding Techniques .......................................................................... 199
Black Boxes HDL Coding Techniques .............................................................. 212
Frontmatter Send Feedback

UG627 (v 14.5) March 20, 2013 www.xilinx.com 3
Chapter 4 XST FPGA Optimization .........................................................................215
FPGA Synthesis and Optimization................................................................... 215
FPGA Specific Synthesis Options ..................................................................... 216
Macro Generation .............................................................................................. 216
DSP48 Block Resources ..................................................................................... 221
Mapping Logic Onto Block RAM ..................................................................... 223
Flip-Flop Retiming............................................................................................. 227
Partitions............................................................................................................. 228
Speed Optimization Under Area Constraint .................................................... 228
FPGA Device Optimization Report Section ..................................................... 230
Implementation Constraints ............................................................................. 236
FPGA Device Primitive Support ....................................................................... 237
Cores Processing ................................................................................................ 243
Specifying INIT and RLOC............................................................................... 245
Using PCI Flow With XST ................................................................................. 251
Chapter 5 XST CPLD Optimization .........................................................................253

CPLD Synthesis Options ................................................................................... 253
Implementation Details for Macro Generation................................................ 254
CPLD Synthesis Log File Analysis ................................................................... 255
CPLD Synthesis Constraints ............................................................................. 257
Improving Results in CPLD Synthesis ............................................................. 257
Chapter 6 XST Design Constraints .........................................................................261

About XST Design Constraints ......................................................................... 261
Mechanisms for Specifying Constraints........................................................... 262
Global and Local Constraint Settings ............................................................... 262
Rules for Applying Constraints ........................................................................ 262
Setting Global Constraints and Options .......................................................... 263
VHDL Attribute Syntax ..................................................................................... 268
Verilog-2001 Attributes ...................................................................................... 268
XST Constraint File (XCF) ................................................................................. 270
Constraints Priority............................................................................................ 272
XST Specific Non-Timing Options ................................................................... 273
XST Command Line Only Options................................................................... 279
Chapter 7 XST General Constraints .......................................................................285

Add I/O Buffers (-iobuf) .................................................................................... 286
BoxType (BOX_TYPE)........................................................................................ 287
Bus Delimiter (-bus_delimiter) ......................................................................... 288
Send Feedback Frontmatter

Case (-case) ......................................................................................................... 289
Case Implementation Style (-vlgcase)............................................................... 289
Duplication Suffix (-duplication_suffix)........................................................... 290
Full Case (FULL_CASE)..................................................................................... 292
Generate RTL Schematic (-rtlview) ................................................................... 293
Generics (-generics)............................................................................................ 294
HDL Library Mapping File (-xsthdpini) ........................................................... 295
Hierarchy Separator (-hierarchy_separator) ..................................................... 297
I/O Standard (IOSTANDARD) ......................................................................... 298
Keep (KEEP) ....................................................................................................... 298
Keep Hierarchy (KEEP_HIERARCHY)............................................................. 298
Library Search Order (-lso) ................................................................................ 300
LOC ..................................................................................................................... 301
Netlist Hierarchy (-netlist_hierarchy) ............................................................... 301
Optimization Effort (OPT_LEVEL) ................................................................... 302
Optimization Goal (OPT_MODE) .................................................................... 303
Parallel Case (PARALLEL_CASE)..................................................................... 304
RLOC (RLOC) .................................................................................................... 306
Save (S) ............................................................................................................... 306
Synthesis Constraint File (-uc) .......................................................................... 307
Translate Off (TRANSLATE_OFF) and Translate On
(TRANSLATE_ON).................................................................................... 308
Ignore Synthesis Constraints File (–iuc)........................................................... 309
Verilog 2001 (-verilog2001)................................................................................. 309
Verilog Include Directories (-vlgincdir)............................................................ 310
Verilog Macros (-define) .................................................................................... 311
Work Directory (-xsthdpdir) .............................................................................. 312
Chapter 8 XST HDL Constraints .............................................................................315

Automatic FSM Extraction (FSM_EXTRACT).................................................. 316
Enumerated Encoding (ENUM_ENCODING) ................................................. 317
Equivalent Register Removal
(EQUIVALENT_REGISTER_REMOVAL) ................................................ 318
FSM Encoding Algorithm (FSM_ENCODING) ............................................... 320
Mux Extraction (MUX_EXTRACT) ................................................................... 321
Resource Sharing (RESOURCE_SHARING) ................................................... 322
Safe Implementation (SAFE_IMPLEMENTATION)........................................ 324
Signal Encoding (SIGNAL_ENCODING)........................................................ 325
Safe Recovery State (SAFE_RECOVERY_STATE) ........................................... 326

Chapter 9 XST FPGA Constraints (Non-Timing) ...................................................329
Asynchronous to Synchronous (ASYNC_TO_SYNC) ..................................... 331
Automatic BRAM Packing (AUTO_BRAM_PACKING)................................. 332
BRAM Utilization Ratio (BRAM_UTILIZATION_RATIO) ............................ 332
Buffer Type (BUFFER_TYPE) ............................................................................ 334
Convert Tristates to Logic (TRISTATE2LOGIC) .............................................. 335
Cores Search Directories (-sd) ........................................................................... 337
Decoder Extraction (DECODER_EXTRACT) ................................................... 338
DSP Utilization Ratio (DSP_UTILIZATION_RATIO) .................................... 339
Extract BUFGCE (BUFGCE)............................................................................... 341
FSM Style (FSM_STYLE)................................................................................... 342
Logical Shifter Extraction (SHIFT_EXTRACT) ................................................ 343
LUT Combining (LC) ......................................................................................... 344
Map Entity on a Single LUT (LUT_MAP) ........................................................ 345
Map Logic on BRAM (BRAM_MAP)................................................................ 346
Max Fanout (MAX_FANOUT)........................................................................... 347
Move First Stage (MOVE_FIRST_STAGE)....................................................... 349
Move Last Stage (MOVE_LAST_STAGE) ........................................................ 351
Multiplier Style (MULT_STYLE) ...................................................................... 353
Mux Style (MUX_STYLE) .................................................................................. 354
Number of Global Clock Buffers (-bufg) ......................................................... 356
Number of Regional Clock Buffers (-bufr)....................................................... 357
Optimize Instantiated Primitives (OPTIMIZE_PRIMITIVES) ....................... 358
Pack I/O Registers Into IOBs (IOB) .................................................................. 359
Power Reduction (POWER) ............................................................................... 359
Priority Encoder Extraction (PRIORITY_EXTRACT)....................................... 361
RAM Extraction (RAM_EXTRACT) .................................................................. 362
RAM Style (RAM_STYLE) ................................................................................ 363
Read Cores (READ_CORES) ............................................................................. 365
Reduce Control Sets (REDUCE_CONTROL_SETS) ........................................ 367
Register Balancing (REGISTER_BALANCING).............................................. 367
Register Duplication (REGISTER_DUPLICATION) ....................................... 371
ROM Extraction (ROM_EXTRACT) ................................................................. 372
ROM Style (ROM_STYLE) ................................................................................ 373
Shift Register Extraction (SHREG_EXTRACT) ................................................ 374
Slice (LUT-FF Pairs) Utilization Ratio
(SLICE_UTILIZATION_RATIO)............................................................... 376
Slice (LUT-FF Pairs) Utilization Ratio Delta
(SLICE_UTILIZATION_RATIO_MAXMARGIN) ................................... 378

Slice Packing (-slice_packing) ........................................................................... 379
Use Low Skew Lines (USELOWSKEWLINES) ................................................ 380
Use Carry Chain (USE_CARRY_CHAIN)......................................................... 380
Use Clock Enable (USE_CLOCK_ENABLE)..................................................... 382
USE_DSP48 (Use DSP48)................................................................................... 383
Use Synchronous Set (USE_SYNC_SET).......................................................... 385
Use Synchronous Reset (USE_SYNC_RESET) ................................................. 387
XOR Collapsing (XOR_COLLAPSE) ................................................................ 388
Chapter 10 XST CPLD Constraints (Non-Timing)..................................................391

Clock Enable (-pld_ce) ....................................................................................... 391
Data Gate (DATA_GATE) .................................................................................. 392
Macro Preserve (-pld_mp) ................................................................................. 392
No Reduce (NOREDUCE) ................................................................................. 393
WYSIWYG (-wysiwyg) ...................................................................................... 393
XOR Preserve (-pld_xp) ..................................................................................... 394
Chapter 11 XST Timing Constraints .......................................................................397

Applying Timing Constraints ........................................................................... 398
XCF Timing Constraint Support ....................................................................... 399
Clock Signal (CLOCK_SIGNAL) ...................................................................... 399
Cross Clock Analysis (-cross_clock_analysis) .................................................. 400
From-To (FROM-TO) ......................................................................................... 401
Global Optimization Goal (-glob_opt) ............................................................. 401
Offset (OFFSET)................................................................................................. 404
Period (PERIOD) ................................................................................................ 404
Timing Name (TNM) ......................................................................................... 405
Timing Name on a Net (TNM_NET)................................................................. 405
Timegroup (TIMEGRP) ..................................................................................... 405
Timing Ignore (TIG) .......................................................................................... 406
Write Timing Constraints (-write_timing_constraints).................................... 406
Chapter 12 XST Implementation Constraints ........................................................409

Implementation Constraints Syntax Examples ................................................ 409
No Reduce (NOREDUCE) ................................................................................. 410
Power Mode (PWR_MODE).............................................................................. 411
RLOC (RLOC) .................................................................................................... 411
Chapter 13 XST Supported Third Party Constraints .............................................413

XST Equivalents to Third Party Constraints .................................................... 413

Third Party Constraints Syntax Examples ........................................................ 416
Chapter 14 XST VHDL Language Support .............................................................417

VHDL Logic Descriptions ................................................................................. 417
VHDL IEEE Support .......................................................................................... 418
VHDL File Type Support................................................................................... 419
VHDL Debugging Using Write Operation....................................................... 420
VHDL Data Types .............................................................................................. 423
VHDL Record Types .......................................................................................... 427
VHDL Initial Values .......................................................................................... 427
VHDL Objects .................................................................................................... 430
VHDL Operators ................................................................................................ 431
VHDL Entity and Architecture Descriptions ................................................... 432
VHDL Combinatorial Circuits .......................................................................... 438
VHDL Sequential Circuits ................................................................................ 444
VHDL Functions and Procedures...................................................................... 450
VHDL Assert Statements................................................................................... 452
VHDL Models Defined Using Packages........................................................... 455
VHDL Constructs Supported in XST................................................................ 458
VHDL Reserved Words...................................................................................... 462
Chapter 15 XST Verilog Language Support ...........................................................463

About XST Verilog Language Support ............................................................. 463
Behavioral Verilog.............................................................................................. 464
Variable Part Selects........................................................................................... 464
Structural Verilog Features ................................................................................ 464
Verilog Parameters ............................................................................................. 468
Verilog Parameter and Attribute Conflicts ....................................................... 469
Verilog Limitations in XST ................................................................................ 470
Verilog Attributes and Meta Comments........................................................... 473
Verilog Constructs Supported in XST............................................................... 475
Verilog System Tasks and Functions Supported in XST ................................. 478
Verilog Primitives .............................................................................................. 480
Verilog Reserved Keywords .............................................................................. 481
Verilog-2001 Support in XST ............................................................................. 482
Chapter 16 XST Behavioral Verilog Language Support........................................483

Behavioral Verilog Variable Declarations......................................................... 484
Behavioral Verilog Initial Values ...................................................................... 485
Behavioral Verilog Local Reset.......................................................................... 486

Behavioral Verilog Arrays ................................................................................. 487
Behavioral Verilog Multi-Dimensional Arrays ................................................ 487
Behavioral Verilog Data Types .......................................................................... 488
Behavioral Verilog Legal Statements ................................................................ 490
Behavioral Verilog Expressions......................................................................... 491
Behavioral Verilog Blocks ................................................................................. 494
Behavioral Verilog Modules.............................................................................. 494
Behavioral Verilog Module Declarations ......................................................... 495
Behavioral Verilog Continuous Assignments .................................................. 496
Behavioral Verilog Procedural Assignments.................................................... 497
Behavioral Verilog Constants ............................................................................ 510
Behavioral Verilog Macros ................................................................................ 510
Behavioral Verilog Include Files ....................................................................... 511
Behavioral Verilog Comments........................................................................... 512
Behavioral Verilog Generate Statements .......................................................... 513
Chapter 17 XST Mixed Language Support.............................................................515

About XST Mixed Language Support............................................................... 515
Mixed Language Project Files ........................................................................... 516
VHDL and Verilog Boundary Rules in Mixed Language Projects .................. 517
Port Mapping in Mixed Language Projects ...................................................... 519
Generics Support in Mixed Language Projects ................................................ 520
LSO Files in Mixed Language Projects ............................................................. 520
Chapter 18 XST Log File ..........................................................................................523

XST FPGA Log File Contents ............................................................................ 523
Reducing the Size of the XST Log File ............................................................. 527
Macros in XST Log Files .................................................................................... 529
XST Log File Examples ...................................................................................... 529
Chapter 19 XST Naming Conventions ....................................................................551

XST Net Naming Conventions.......................................................................... 551
XST Instance Naming Conventions.................................................................. 551
XST Name Generation Control ......................................................................... 552
Chapter 20 XST Command Line Mode ...................................................................553

About XST Command Line Mode..................................................................... 553
Launching XST in Command Line Mode Using the XST Shell ...................... 554
Launching XST in Command Line Mode Using a Script File ......................... 554
Setting Up an XST Script Using the Run Command ....................................... 555

Setting Up an XST Script Using the Set Command ......................................... 558
Setting Up an XST Script Using the Elaborate Command............................... 558
Running XST in Script Mode (VHDL) ............................................................. 559
Running XST in Script Mode (Verilog) ............................................................ 561
Running XST in Script Mode (Mixed Language)............................................. 563
Synthesizing VHDL Designs Using Command Line Mode............................ 564
Synthesizing Verilog Designs Using Command Line Mode........................... 566
Synthesizing Mixed Designs Using Command Line Mode ............................ 568

Chapter 1
About This Guide

This chapter includes:
• Guide Overview
• Supported Devices
• Additional Resources
• Conventions
Guide Overview
This Guide:
• Applies only to the devices listed in Supported Devices.
• Describes Xilinx Synthesis Technology (XST) support for:
– Hardware Description Language (HDL) designs
– Supported Xilinx® devices
– Design constraints for the Xilinx ISE® Design Suite software
• Discusses optimization and coding techniques when creating designs for use with
XST.
• Explains how to run XST from the:
– ISE Design Suite Process window
– Command line

Chapter 1: About This Guide
Supported Devices
This Guide applies to the following Xilinx® devices only:
• FPGA Devices
– Virtex®-4
– Virtex-5
– Spartan®-3 device family, including:
♦ Spartan-3
♦ Spartan-3A
♦ Spartan-3A DSP
♦ Spartan-3AN
♦ Spartan-3E
♦ Spartan-3L
• CPLD Devices
– CoolRunner™ XPLA3
– CoolRunner-II
– XC9500
– XC9500XL

Chapter 2
Introduction to Xilinx Synthesis

Technology (XST)
• About XST
• Setting XST Options
About XST
Xilinx Synthesis Technology (XST) is a Xilinx® application that synthesizes Hardware
Description Language (HDL) designs to create Xilinx specific netlist files called NGC
files.
The NGC file:
• Is a netlist that contains both logical design data and constraints.
• Takes the place of both Electronic Data Interchange Format (EDIF) and Netlist
Constraints File (NCF) files.
For more information, see:
Xilinx Synthesis Technology (XST) - Frequently Asked Questions (FAQ)
Search for keyword XST FAQ.
Setting XST Options

Before synthesizing your design, you can set a variety of options for XST.
Designs are usually made up of:
• Combinatorial logic
• Macros such as flip-flops, adders, subtractors, counters, FSMs, and RAMs
Macros greatly improve performance of the synthesized designs. It is important to use
coding techniques to model the macros so they are optimally processed by XST.
XST first tries to recognize (infer) as many macros as possible. These macros are then
passed to the Low Level Optimization step. In order to obtain better optimization
results, the macros are either preserved as separate blocks, or merged with surrounded
logic. This filtering depends on the type and size of a macro. For example, by default,
2-to-1 multiplexers are not preserved by the optimization engine. Synthesis constraints
control the processing of inferred macros.

Chapter 2: Introduction to Xilinx Synthesis Technology (XST)

• ISE® Design Suite Help
• XST Design Constraints
• XST Command Line Mode

Chapter 3
XST HDL Coding Techniques

This chapter discusses XST HDL Coding Techniques, and includes:
• Signed and Unsigned Support in XST
• Registers HDL Coding Techniques
• Latches HDL Coding Techniques
• Tristates HDL Coding Techniques
• Counters HDL Coding Techniques
• Accumulators HDL Coding Techniques
• Shift Registers HDL Coding Techniques
• Dynamic Shift Registers HDL Coding Techniques
• Multiplexers HDL Coding Techniques
• Decoders HDL Coding Techniques
• Priority Encoders HDL Coding Techniques
• Logical Shifters HDL Coding Techniques
• Arithmetic Operators HDL Coding Techniques
• Adders, Subtractors, and Adders/Subtractors HDL Coding Techniques
• Comparators HDL Coding Techniques
• Multipliers HDL Coding Techniques
• Sequential Complex Multipliers HDL Coding Techniques
• Pipelined Multipliers HDL Coding Techniques
• Multiply Adder/Subtractors HDL Coding Techniques
• Multiply Accumulate HDL Coding Techniques
• Dividers HDL Coding Techniques
• Resource Sharing HDL Coding Techniques
• RAMs and ROMs HDL Coding Techniques
• ROMs Using Block RAM Resources HDL Coding Techniques
• Pipelined Distributed RAM HDL Coding Techniques
• FSM HDL Coding Techniques
• Black Boxes HDL Coding Techniques
• XST FPGA Optimization
• XST CPLD Optimization
For information on accessing the synthesis templates from ISE® Design Suite, see the
ISE Design Suite Help.

Chapter 3: XST HDL Coding Techniques
Signed and Unsigned Support in XST

When using Verilog or VHDL in XST, some macros, such as adders or counters, can be
implemented for signed and unsigned values.
To enable support for signed and unsigned values in Verilog, enable Verilog-2001
as follows:
• ISE® Design Suite
Select Verilog 2001 as instructed in the Synthesis Options topic of ISE Design Suite
Help
• XST Command Line
Set -verilog2001 to yes.
For VHDL, depending on the operation and type of the operands, you must include
additional packages in your code. For example, to create an unsigned adder, use the
arithmetic packages and types that operate on unsigned values shown in the following
table.
Unsigned Adders
PACKAGE TYPE
numeric_std unsigned
std_logic_arith unsigned
std_logic_unsigned std_logic_vector
To create a signed adder, use the arithmetic packages and types that operate on signed
values shown in the following table.
Signed Adders
PACKAGE TYPE
numeric_std signed
std_logic_arith signed
std_logic_signed std_logic_vector
For more information about available types, see the IEEE VHDL Manual.

Registers HDL Coding Techniques

This section discusses Registers HDL Coding Techniques, and includes:
• About Registers
• Registers Log File
• Registers Related Constraints
• Registers Coding Examples
About Registers
XST recognizes flip-flops with the following control signals:
• Asynchronous Set/Reset
• Synchronous Set/Reset
• Clock Enable
Specifying INIT and RLOC
Registers Log File

The XST log file reports the type and size of recognized flip-flops during the Macro
Recognition step.
With device families such as the Virtex®-4 device family, XST may optimize different
slices of the same register in different ways. For example, XST may push a part of a
register into a DSP48 block, while another part may be implemented on slices, or even
become a part of a shift register. XST reports the total number of FF bits in the design in
the HDL Synthesis Report after the Advanced HDL Synthesis step.
Registers Log File Example

...
===============================================================
* HDL Synthesis *
===============================================================
Synthesizing Unit <registers_5>.

Related source file is "registers_5.vhd".
Found 4-bit register for signal <Q>.
Summary:
inferred 4 D-type flip-flop(s).
Unit <registers_5> synthesized.
===============================================================
HDL Synthesis Report
Macro Statistics
# Registers : 1
4-bit register : 1
===============================================================
===============================================================
* Advanced HDL Synthesis *
===============================================================
===============================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers : 4
Flip-Flops/Latches : 4
===============================================================
...
Registers Related Constraints

• Pack I/O Registers Into IOBs (IOB)
• Register Duplication (REGISTER_DUPLICATION)
• Equivalent Register Removal (EQUIVALENT_REGISTER_REMOVAL)
• Register Balancing (REGISTER_BALANCING)
Registers Coding Examples

Coding examples can be downloaded in text format from
http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
Flip-Flop With Positive-Edge Clock Diagram
Flip-Flop With Positive-Edge Clock Pin Descriptions

IO Pins Description
D Data Input
C Positive-Edge Clock
Q Data Output
Flip-Flop With Positive Edge Clock VHDL Coding Example

--
-- Flip-Flop with Positive-Edge Clock
--
library ieee;
use ieee.std_logic_1164.all;
entity registers_1 is
port(C, D : in std_logic;
Q : out std_logic);
end registers_1;
architecture archi of registers_1 is

begin
process (C)
begin
if (C’event and C=’1’) then
Q <= D;
end if;

end process;
end archi;
When using VHDL for a positive-edge clock, instead of using:

you can also use:
if (rising_edge(C)) then
Flip-Flop With Positive-Edge Clock Verilog Coding Example
//
// Flip-Flop with Positive-Edge Clock
//
module v_registers_1 (C, D, Q);

input C, D;
output Q;
reg Q;
always @(posedge C)
begin
Q <= D;
end
endmodule
Flip-Flop With Positive Edge Clock with INITSTATE of the Flop Set Verilog
Coding Example
module test(d, C, q);
input d;
input C;
output q;
reg qtemp = ’b1 ;
always @ (posedge C)
begin
qtemp = d;
end
assign q = qtemp;
endmodule

Flip-Flop With Positive Edge Clock with INITSTATE of the Flop Set VHDL
Coding Example
library ieee;
port(C, D : in std_logic;
Q : out std_logic);
end registers_1;

signal qtemp : std_logic := ’1’;
begin
process (C)
begin
qtemp <= D;
end if;
Q <= Qtemp;
end process;
end archi;
Flip-Flop With Negative-Edge Clock and Asynchronous Reset

Diagram
Flip-Flop With Negative-Edge Clock and Asynchronous Reset

Pin Descriptions
IO Pins Description
D Data Input
C Negative-Edge Clock
CLR Asynchronous Reset (active-High)
Q Data Output

Flip-Flop With Negative-Edge Clock and Asynchronous Reset VHDL

Coding Example
--
-- Flip-Flop with Negative-Edge Clock and Asynchronous Reset
--
library ieee;
port(C, D, CLR : in std_logic;
Q : out std_logic);
end registers_2;

begin
process (C, CLR)

begin
if (CLR = ’1’)then
Q <= ’0’;
elsif (C’event and C=’0’)then
Q <= D;
end if;
end process;
end archi;
Flip-Flop With Negative-Edge Clock and Asynchronous Reset Verilog

Coding Example
//
// Flip-Flop with Negative-Edge Clock and Asynchronous Reset
//
module v_registers_2 (C, D, CLR, Q);

input C, D, CLR;
output Q;
reg Q;
always @(negedge C or posedge CLR)

begin
if (CLR)
Q <= 1’b0;
else
Q <= D;
end
endmodule

Flip-Flop With Positive-Edge Clock and Synchronous Set Diagram
Flip-Flop With Positive-Edge Clock and Synchronous Set Pin

Descriptions
IO Pins Description
D Data Input
S Synchronous Set (active-High)
Q Data Output
Flip-Flop With Positive-Edge Clock and Synchronous Set VHDL Coding

Example
--
-- Flip-Flop with Positive-Edge Clock and Synchronous Set
--
library ieee;
port(C, D, S : in std_logic;
Q : out std_logic);
end registers_3;

begin
process (C)
begin
if (S=’1’) then
Q <= ’1’;
else
Q <= D;
end if;
end if;
end process;
end archi;

Flip-Flop With Positive-Edge Clock and Synchronous Set Verilog Coding

Example
//
// Flip-Flop with Positive-Edge Clock and Synchronous Set
//
module v_registers_3 (C, D, S, Q);
input C, D, S;
output Q;
reg Q;
always @(posedge C)
begin
if (S)
Q <= 1’b1;
else
Q <= D;
end
endmodule
Flip-Flop With Positive-Edge Clock and Clock Enable Diagram
Flip-Flop With Positive-Edge Clock and Clock Enable Pin

Descriptions
IO Pins Description
D Data Input
CE Clock Enable (active-High)
Q Data Output
Flip-Flop With Positive-Edge Clock and Clock Enable VHDL Coding

Example
--
-- Flip-Flop with Positive-Edge Clock and Clock Enable
--
library ieee;
port(C, D, CE : in std_logic;
Q : out std_logic);
end registers_4;

begin

process (C)
begin
if (CE=’1’) then
Q <= D;
end if;
end if;
end process;
end archi;
Flip-Flop With Positive-Edge Clock and Clock Enable Verilog Coding
Example
//
// Flip-Flop with Positive-Edge Clock and Clock Enable
//
module v_registers_4 (C, D, CE, Q);

input C, D, CE;
output Q;
reg Q;
always @(posedge C)
begin
if (CE)
Q <= D;
end
endmodule
4-Bit Register With Positive-Edge Clock, Asynchronous Set, and

Clock Enable Diagram
4-Bit Register With Positive-Edge Clock, Asynchronous Set, and

Clock Enable Pin Descriptions
IO Pins Description
D Data Input
PRE Asynchronous Set (active-High)
Q Data Output

4-Bit Register With Positive-Edge Clock, Asynchronous Set, and Clock

Enable VHDL Coding Example
--
-- 4-bit Register with Positive-Edge Clock,
-- Asynchronous Set and Clock Enable
--
library ieee;
port(C, CE, PRE : in std_logic;
D : in std_logic_vector (3 downto 0);
Q : out std_logic_vector (3 downto 0));
end registers_5;

begin
process (C, PRE)

begin
if (PRE=’1’) then
Q <= "1111";
elsif (C’event and C=’1’)then
Q <= D;
end if;
end if;
end process;
end archi;

4-Bit Register With Positive-Edge Clock, Asynchronous Set, and Clock

Enable Verilog Coding Example
//
// 4-bit Register with Positive-Edge Clock,
// Asynchronous Set and Clock Enable
//
module v_registers_5 (C, D, CE, PRE, Q);

input C, CE, PRE;
input [3:0] D;
output [3:0] Q;
reg [3:0] Q;
always @(posedge C or posedge PRE)

begin
if (PRE)
Q <= 4’b1111;
else
if (CE)
Q <= D;
end
endmodule

Latches HDL Coding Techniques

This section includes:
• About Latches
• Latches Log File
• Latches Related Constraints
• Latches Coding Examples
About Latches
XST can recognize latches with asynchronous set/reset control signals. Latches can
be described using:
• Process (VHDL)
• Always block (Verilog)
• Concurrent state assignment
XST does not support wait statements (VHDL) for latch descriptions.
Latches Log File

The XST log file reports the type and size of recognized latches during the Macro
Recognition step.
Latches Log File Example

...
Synthesizing Unit <latch>.
Related source file is latch_1.vhd.
WARNING:Xst:737 - Found 1-bit latch for signal <q>.
Summary:
inferred 1 Latch(s).
Unit <latch> synthesized.
=======================================
Macro Statistics
# Latches : 1
1-bit latch : 1
========================================
...
Latches Related Constraints

Pack I/O Registers Into IOBs (IOB)
Latches Coding Examples


Latch With Positive Gate Diagram
Latch With Positive Gate Pin Descriptions

IO Pins Description
D Data Input
G Positive Gate
Q Data Output
Latch With Positive Gate VHDL Coding Example

--
-- Latch with Positive Gate
--
library ieee;
entity latches_1 is
port(G, D : in std_logic;
Q : out std_logic);
end latches_1;
architecture archi of latches_1 is

begin
process (G, D)
begin
if (G=’1’) then
Q <= D;
end if;
end process;
end archi;
Latch With Positive Gate Verilog Coding Example
//
// Latch with Positive Gate
//
module v_latches_1 (G, D, Q);
input G, D;
output Q;
reg Q;
always @(G or D)
begin
if (G)
Q = D;
end
endmodule

Latch With Positive Gate and Asynchronous Reset Diagram
Latch With Positive Gate and Asynchronous Reset Pin

Descriptions
IO Pins Description
D Data Input
G Positive Gate
Q Data Output
Latch With Positive Gate and Asynchronous Reset VHDL Coding Example
--
-- Latch with Positive Gate and Asynchronous Reset
--
library ieee;
entity latches_2 is
port(G, D, CLR : in std_logic;
Q : out std_logic);
end latches_2;

begin
process (CLR, D, G)
begin
if (CLR=’1’) then
Q <= ’0’;
elsif (G=’1’) then
Q <= D;
end if;
end process;
end archi;

Latch With Positive Gate and Asynchronous Reset Verilog Coding Example
//
// Latch with Positive Gate and Asynchronous Reset
//
module v_latches_2 (G, D, CLR, Q);

input G, D, CLR;
output Q;
reg Q;
always @(G or D or CLR)

begin
if (CLR)
Q = 1’b0;
else if (G)
Q = D;
end
endmodule
4-Bit Latch With Inverted Gate and Asynchronous Set Diagram
4-Bit Latch With Inverted Gate and Asynchronous Set Pin

Descriptions
IO Pins Description
D Data Input
G Inverted Gate
PRE Asynchronous Preset (active-High)
Q Data Output
4-Bit Latch With Inverted Gate and Asynchronous Set VHDL Coding
Example
--
-- 4-bit Latch with Inverted Gate and Asynchronous Set
--
library ieee;
entity latches_3 is
port(D : in std_logic_vector(3 downto 0);
G, PRE : in std_logic;
Q : out std_logic_vector(3 downto 0));
end latches_3;


begin
process (PRE, G, D)
begin
if (PRE=’1’) then
Q <= "1111";
elsif (G=’0’) then
Q <= D;
end if;
end process;
end archi;
4-Bit Latch With Inverted Gate and Asynchronous Set Verilog Coding
Example
//
// 4-bit Latch with Inverted Gate and Asynchronous Set
//
module v_latches_3 (G, D, PRE, Q);

input G, PRE;
input [3:0] D;
output [3:0] Q;
reg [3:0] Q;
always @(G or D or PRE)

begin
if (PRE)
Q = 4’b1111;
else if (~G)
Q = D;
end
endmodule

Tristates HDL Coding Techniques

This section discusses Tristates HDL Coding Techniques, and includes:
• About Tristates
• Tristates Log File
• Tristates Related Constraints
• Tristates Coding Examples
About Tristates
Tristate elements can be described using:
• Combinatorial process (VHDL)
• Always block (Verilog)
• Concurrent assignment
In the Tristates Coding Examples, comparing to 0 instead of 1 infers a BUFT primitive
instead of a BUFE macro. The BUFE macro has an inverter on the E pin.
Tristates Log File

The XST log file reports the type and size of recognized tristates during the Macro
Recognition step.
Tristates Log File Example

...
Synthesizing Unit <three_st>.
Related source file is tristates_1.vhd.
Found 1-bit tristate buffer for signal <o>.
Summary:
inferred 1 Tristate(s).
Unit <three_st> synthesized.
=============================
Macro Statistics
# Tristates : 1
1-bit tristate buffer : 1
=============================
...
Tristates Related Constraints

Convert Tristates to Logic (TRISTATE2LOGIC)
Tristates Coding Examples


Tristate Description Using Combinatorial Process and Always

Block Diagram
Tristate Description Using Combinatorial Process and Always

Block Pin Descriptions
IO Pins Description
I Data Input
T Output Enable (active-Low)
O Data Output
Tristate Description Using Combinatorial Process VHDL Coding Example

--
-- Tristate Description Using Combinatorial Process
--
library ieee;
entity three_st_1 is
port(T : in std_logic;
I : in std_logic;
O : out std_logic);
end three_st_1;
architecture archi of three_st_1 is

begin
process (I, T)
begin
if (T=’0’) then
O <= I;
else
O <= ’Z’;
end if;
end process;
end archi;

Tristate Description Using Combinatorial Always Block Verilog Coding

Example
//
// Tristate Description Using Combinatorial Always Block
//
module v_three_st_1 (T, I, O);

input T, I;
output O;
reg O;
always @(T or I)
begin
if (~T)
O = I;
else
O = 1’bZ;
end
endmodule
Tristate Description Using Concurrent Assignment Diagram
Tristate Description Using Concurrent Assignment Pin

Descriptions
IO Pins Description
I Data Input
T Output Enable (active-Low)
O Data Output
Tristate Description Using Concurrent Assignment VHDL Coding Example

--
-- Tristate Description Using Concurrent Assignment
--
library ieee;
entity three_st_2 is
port(T : in std_logic;
I : in std_logic;
O : out std_logic);
end three_st_2;
architecture archi of three_st_2 is

begin
O <= I when (T=’0’) else ’Z’;

end archi;
Tristate Description Using Concurrent Assignment Verilog Coding Example

//
// Tristate Description Using Concurrent Assignment
//
module v_three_st_2 (T, I, O);

input T, I;
output O;
assign O = (~T) ? I: 1’bZ;
endmodule

Counters HDL Coding Techniques

This section discusses Counters HDL Coding Techniques, and includes:
• About Counters
• Counters Log File
• Counters Related Constraints
• Counters Coding Examples
About Counters
XST recognizes counters with the following control signals:
• Asynchronous/Synchronous Load (signal or constant or both)
• Clock Enable
• Modes (Up, Down, Up/Down)
• Mixture of all of the above
Hardware Description Language (HDL) coding styles for the following control signals
are equivalent to those described in Registers HDL Coding Techniques.
• Clock
XST supports both unsigned and signed counters.
Counters Log File

The XST log file reports the type and size of recognized counters during the Macro
Recognition step.
Counters Log File Example

...
Synthesizing Unit <counter>.
Related source file is counters_1.vhd.
Found 4-bit up counter for signal <tmp>.
Summary:
inferred 1 Counter(s).
Unit <counter> synthesized.
==============================
Macro Statistics
# Counters : 1
4-bit up counter : 1
==============================
...

Counters Related Constraints

• Use DSP48 (USE_DSP48)
• DSP Utilization Ratio (DSP_UTILIZATION_RATIO)
• Keep (KEEP)
Counters Coding Examples

4-Bit Unsigned Up Counter With Asynchronous Reset Diagram
4-Bit Unsigned Up Counter With Asynchronous Reset Pin

Descriptions
IO Pins Description
Q Data Output
4-Bit Unsigned Up Counter With Asynchronous Reset VHDL Coding

Example
--
-- 4-bit unsigned up counter with an asynchronous reset.
--
library ieee;
use ieee.std_logic_unsigned.all;
entity counters_1 is
port(C, CLR : in std_logic;
end counters_1;
architecture archi of counters_1 is

signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
tmp <= "0000";
elsif (C’event and C=’1’) then
tmp <= tmp + 1;
end if;
end process;

Q <= tmp;
end archi;
4-Bit Unsigned Up Counter With Asynchronous Reset Verilog Coding

Example
//
// 4-bit unsigned up counter with an asynchronous reset.
//
module v_counters_1 (C, CLR, Q);

input C, CLR;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C or posedge CLR)

begin
if (CLR)
tmp <= 4’b0000;
else
tmp <= tmp + 1’b1;
end
assign Q = tmp;
endmodule
4-Bit Unsigned Down Counter With Synchronous Set Diagram
4-Bit Unsigned Down Counter With Synchronous Set Pin

Descriptions
IO Pins Description
S Synchronous Set (active-High)
Q Data Output

4-Bit Unsigned Down Counter With Synchronous Set VHDL Coding

Example
--
-- 4-bit unsigned down counter with a synchronous set.
--
library ieee;
port(C, S : in std_logic;
end counters_2;

begin
process (C)
begin
if (S=’1’) then
tmp <= "1111";
else
tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
4-Bit Unsigned Down Counter With Synchronous Set Verilog Coding

Example
//
// 4-bit unsigned down counter with a synchronous set.
//
module v_counters_2 (C, S, Q);

input C, S;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C)
begin
if (S)
tmp <= 4’b1111;
else
tmp <= tmp - 1’b1;
end
assign Q = tmp;
endmodule

4-Bit Unsigned Up Counter With Asynchronous Load From

Primary Input Diagram
4-Bit Unsigned Up Counter With Asynchronous Load From

Primary Input Pin Descriptions
IO Pins Description
ALOAD Asynchronous Load (active-High)
D Data Input
Q Data Output
4-Bit Unsigned Up Counter With Asynchronous Load From Primary Input

VHDL Coding Example
--
-- 4-bit Unsigned Up Counter with Asynchronous Load
-- from Primary Input
--
library ieee;
port(C, ALOAD : in std_logic;
D : in std_logic_vector(3 downto 0);
end counters_3;

begin
process (C, ALOAD, D)
begin
if (ALOAD=’1’) then
tmp <= D;
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;

4-Bit Unsigned Up Counter With Asynchronous Load From Primary Input

Verilog Coding Example
//
// 4-bit Unsigned Up Counter with Asynchronous Load
// from Primary Input
//
module v_counters_3 (C, ALOAD, D, Q);

input C, ALOAD;
input [3:0] D;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C or posedge ALOAD)

begin
if (ALOAD)
tmp <= D;
else
tmp <= tmp + 1’b1;
end
assign Q = tmp;
endmodule
4-Bit Unsigned Up Counter With Synchronous Load With

Constant Diagram
4-Bit Unsigned Up Counter With Synchronous Load With

Constant Pin Descriptions
IO Pins Description
SLOAD Synchronous Load (active-High)
Q Data Output

4-Bit Unsigned Up Counter With Synchronous Load With Constant VHDL

Coding Example
--
-- 4-bit Unsigned Up Counter with Synchronous Load
-- with a Constant
--
library ieee;
port(C, SLOAD : in std_logic;
end counters_4;

begin
process (C)
begin
if (SLOAD=’1’) then
tmp <= "1010";
else
tmp <= tmp + 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
4-Bit Unsigned Up Counter With Synchronous Load With Constant Verilog
Coding Example
//
// 4-bit Unsigned Up Counter with Synchronous Load
// with a Constant
//
module v_counters_4 (C, SLOAD, Q);

input C, SLOAD;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C)
begin
if (SLOAD)
tmp <= 4’b1010;
else
tmp <= tmp + 1’b1;
end
assign Q = tmp;
endmodule

4-Bit Unsigned Up Counter With Asynchronous Reset and Clock

Enable Diagram
4-Bit Unsigned Up Counter With Asynchronous Reset and Clock

Enable Pin Descriptions
IO Pins Description
CE Clock Enable
Q Data Output
4-Bit Unsigned Up Counter With Asynchronous Reset and Clock Enable

VHDL Coding Example
--
-- 4-bit Unsigned Up Counter with Asynchronous Reset
-- and Clock Enable
--
library ieee;
port(C, CLR, CE : in std_logic;
end counters_5;

begin
process (C, CLR)
begin
tmp <= "0000";
tmp <= tmp + 1;
end if;
end if;
end process;
Q <= tmp;
end archi;

4-Bit Unsigned Up Counter With Asynchronous Reset and Clock Enable

//
// 4-bit Unsigned Up Counter with Asynchronous Reset
// and Clock Enable
//
module v_counters_5 (C, CLR, CE, Q);

input C, CLR, CE;
output [3:0] Q;
reg [3:0] tmp;

begin
if (CLR)
tmp <= 4’b0000;
else if (CE)
tmp <= tmp + 1’b1;
end
assign Q = tmp;
endmodule
4-Bit Unsigned Up/Down Counter With Asynchronous Reset

Diagram
4-Bit Unsigned Up/Down Counter With Asynchronous Reset Pin

Descriptions
IO Pins Description
UP_DOWN Up/Down Count Mode Selector
Q Data Output

4-Bit Unsigned Up/Down Counter With Asynchronous Reset VHDL Coding

Example
--
-- 4-bit Unsigned Up/Down counter
-- with Asynchronous Reset
--
library ieee;
port(C, CLR, UP_DOWN : in std_logic;
end counters_6;

begin
process (C, CLR)
begin
tmp <= "0000";
if (UP_DOWN=’1’) then
tmp <= tmp + 1;
else
tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
4-Bit Unsigned Up/Down Counter With Asynchronous Reset Verilog

Coding Example
//
// 4-bit Unsigned Up/Down counter
// with Asynchronous Reset
//
module v_counters_6 (C, CLR, UP_DOWN, Q);

input C, CLR, UP_DOWN;
output [3:0] Q;
reg [3:0] tmp;

begin
if (CLR)
tmp <= 4’b0000;
else if (UP_DOWN)
tmp <= tmp + 1’b1;
else
tmp <= tmp - 1’b1;

end
assign Q = tmp;
endmodule
4-Bit Signed Up Counter With Asynchronous Reset Diagram
4-Bit Signed Up Counter With Asynchronous Reset Pin

Descriptions
IO Pins Description
Q Data Output
4-Bit Signed Up Counter With Asynchronous Reset VHDL Coding Example

--
-- 4-bit Signed Up Counter with Asynchronous Reset
--
library ieee;
use ieee.std_logic_signed.all;
end counters_7;

begin
process (C, CLR)
begin
tmp <= "0000";
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;

4-Bit Signed Up Counter With Asynchronous Reset Verilog Coding

Example
//
// 4-bit Signed Up Counter with Asynchronous Reset
//

input C, CLR;
output signed [3:0] Q;
reg signed [3:0] tmp;
always @ (posedge C or posedge CLR)

begin
if (CLR)
tmp <= 4’b0000;
else
tmp <= tmp + 1’b1;
end
assign Q = tmp;
endmodule
4-Bit Signed Up Counter With Asynchronous Reset and Modulo

Maximum Diagram
4-Bit Signed Up Counter With Asynchronous Reset and Modulo

Maximum Pin Descriptions
IO Pins Description
Q Data Output
4-Bit Signed Up Counter With Asynchronous Reset and Modulo Maximum

VHDL Coding Example
--
-- 4-bit Signed Up Counter with Asynchronous Reset
-- and Modulo Maximum
--
library ieee;
use ieee.std_logic_arith.all;

generic (MAX : integer := 16);

Q : out integer range 0 to MAX-1);
end counters_8;

signal cnt : integer range 0 to MAX-1;
begin
process (C, CLR)
begin
cnt <= 0;
elsif (rising_edge(C)) then
cnt <= (cnt + 1) mod MAX ;
end if;
end process;
Q <= cnt;
end archi;
4-Bit Signed Up Counter With Asynchronous Reset and Modulo Maximum

//
// 4-bit Signed Up Counter with Asynchronous Reset
// and Modulo Maximum
//

parameter
MAX_SQRT = 4,
MAX = (MAX_SQRT*MAX_SQRT);
input C, CLR;
output [MAX_SQRT-1:0] Q;
reg [MAX_SQRT-1:0] cnt;
always @ (posedge C or posedge CLR)

begin
if (CLR)
cnt <= 0;
else
cnt <= (cnt + 1) %MAX;
end
assign Q = cnt;
endmodule

Accumulators HDL Coding Techniques

This section discusses Accumulators HDL Coding Techniques, and includes:
• About Accumulators
• Accumulators in Virtex®-4 Devices and Virtex-5 Device
• Accumulators Log File
• Accumulators Related Constraints
• Accumulators Coding Examples
About Accumulators
An accumulator differs from a counter in the nature of the operands of the add and
subtract operation.
• In a counter:
– The destination and first operand is a signal or variable
– The second operand is a constant equal to 1:
A <= A + 1
• In an accumulator:
– The destination and first operand is a signal or variable
– The second operand is either:
♦ A signal or variable:
A <= A + B
♦ A constant not equal to 1:
A <= A + Constant
An inferred accumulator can be up, down, or updown. For an updown accumulator,
the accumulated data may differ between the up and down mode:
...
if updown = ’1’ then
a <= a + b;
else
a <= a - c;
...
XST can infer an accumulator with the same set of control signals available for counters.
Counters HDL Coding Techniques
Accumulators in Virtex-4 Devices and Virtex-5 Devices

This section discusses Accumulators in Virtex®-4 Devices and Virtex-5 Devices, and
includes:
• About Accumulators in Virtex-4 Devices and Virtex-5 Devices
• Macro Implementation on DSP48 Resources
• Maximum Macro Configuration
• Reporting of Inferred Accumulators

About Accumulators in Virtex-4 Devices and Virtex-5 Devices

Virtex-4 devices and Virtex-5 devices enable accumulators to be implemented on DSP48
resources. XST can push up to two levels of input registers into DSP48 blocks.
XST can implement an accumulator in a DSP48 block if its implementation requires only
a single DSP48 resource. If an accumulator macro does not fit in a single DSP48, XST
implements the entire macro using slice logic.
Macro Implementation on DSP48 Resources

Macro implementation on DSP48 resources is controlled by Use DSP48 (USE_DSP48),
with a default value of auto. In auto mode, XST implements accumulators taking into
account DSP48 resources on the device.
Use DSP Utilization Ratio (DSP_UTILIZATION_RATIO) in auto mode to control DSP48
resources for synthesis. By default, XST tries to utilize all DSP48 resources.
DSP48 Block Resources
Maximum Macro Configuration

To deliver the best performance, XST by default tries to infer and implement the
maximum macro configuration, including as many registers as possible in the DSP48.
Use Keep (KEEP) to shape a macro in a specific way. For example, to exclude the first
register stage from the DSP48, place Keep (KEEP) constraints on the outputs of these
registers.
Reporting of Inferred Accumulators

XST reports the details of inferred accumulators at the HDL Synthesis step. Because
accumulators are implemented within the MAC implementation mechanism, they are
no longer visible in the Final Synthesis Report.
Accumulators Log File

The XST log file reports the type and size of recognized accumulators during the Macro
Recognition step.
Accumulators Log File Example

...
Synthesizing Unit <accum>.
Related source file is accumulators_1.vhd.
Found 4-bit up accumulator for signal <tmp>.
Summary:
inferred 1 Accumulator(s).
Unit <accum> synthesized.
==============================
Macro Statistics
# Accumulators : 1
4-bit up accumulator : 1
==============================
...

Accumulators Related Constraints

• Keep (KEEP)
Accumulators Coding Examples

4-Bit Unsigned Up Accumulator With Asynchronous Reset

Diagram
4-Bit Unsigned Up Accumulator With Asynchronous Reset Pin

Descriptions
IO Pins Description
D Data Input
Q Data Output
4-Bit Unsigned Up Accumulator With Asynchronous Reset VHDL Coding

Example
--
-- 4-bit Unsigned Up Accumulator with Asynchronous Reset
--
library ieee;
entity accumulators_1 is
D : in std_logic_vector(3 downto 0);
end accumulators_1;
architecture archi of accumulators_1 is

begin

process (C, CLR)

begin
tmp <= "0000";
tmp <= tmp + D;
end if;
end process;
Q <= tmp;
end archi;
4-Bit Unsigned Up Accumulator With Asynchronous Reset Verilog Coding

Example
//
// 4-bit Unsigned Up Accumulator with Asynchronous Reset
//
module v_accumulators_1 (C, CLR, D, Q);
input C, CLR;
input [3:0] D;
output [3:0] Q;
reg [3:0] tmp;

begin
if (CLR)
tmp = 4’b0000;
else
tmp = tmp + D;
end
assign Q = tmp;
endmodule

Shift Registers HDL Coding Techniques

This section discusses Shift Registers HDL Coding Techniques, and includes:
• About Shift Registers
• Shift Registers Log File
• Shift Registers Related Constraints
• Shift Registers Coding Examples
About Shift Registers

This section discusses About Shift Registers, and includes:
• Shift Register Definition
• Static Shift Register Components
• Additional Functionality
• Describing Shift Registers
• Implementing Shift Registers
Shift Register Definition

A shift register is a chain of flip-flops allowing propagation of data across a fixed (static)
number of latency stages. In Dynamic Shift Registers HDL Coding Techniques, the
length of the propagation chain dynamically varies during circuit operation.
Static Shift Register Components

A static shift register usually involves:
• A clock
• An optional clock enable
• A serial data input
• A serial data output
Additional Functionality
You can include additional functionality, such as reset, set, or parallel load logic.
In this case however, XST may not always be able to take advantage of dedicated
SRL-type primitives for reduced device utilization and optimized performance. Xilinx®
recommends removing such logic, and loading the desired contents serially instead.
Describing Shift Registers

Ways to describe shift registers in VHDL include:
• Concatenation operator
shreg <= shreg (6 downto 0) & SI;
• For loop construct
for i in 0 to 6 loop
shreg(i+1) <= shreg(i);
end loop;
shreg(0) <= SI;
• Predefined shift operators (for example, SLL or SRL)
For more information, see your VHDL and Verilog language reference manuals.

Implementing Shift Registers

Inferred shift registers are implemented on SRL-type resources. The resources shown in
the following table are leveraged.
Devices SRL16 SRL16E SRLC16 SRLC16E SRLC32E
Spartan®-3 Yes Yes Yes Yes No
Spartan-3E
Spartan-3A
Virtex®-4 Yes Yes Yes Yes No
Virtex-5 Yes Yes Yes Yes Yes
Shift Registers Log File

XST recognizes shift registers in the Low Level Optimization step. The XST log file
reports the size of recognized shift registers.
Shift Registers Log File Example

...
=============================================
* HDL Synthesis *
=============================================
Synthesizing Unit <shift_registers_1>.

Related source file is "shift_registers_1.vhd".
Found 8-bit register for signal <tmp>.
Summary:
Unit <shift_registers_1> synthesized.
=============================================
=============================================
Macro Statistics
# Registers : 8
Flip-Flops : 8
=============================================
=============================================
* Low Level Synthesis *
=============================================
Processing Unit <shift_registers_1> :
Found 8-bit shift register for signal <tmp_7>.
Unit <shift_registers_1> processed.
=============================================
Final Register Report
Macro Statistics
# Shift Registers : 1
8-bit shift register : 1
=============================================
Shift Registers Related Constraints

Shift Register Extraction (SHREG_EXTRACT)

Shift Registers Coding Examples

8-Bit Shift-Left Register With Positive-Edge Clock, Serial In and

Serial Out Diagram
8-Bit Shift-Left Register With Positive-Edge Clock, Serial In and

Serial Out Pin Descriptions
IO Pins Description
SI Serial In
SO Serial Output
8-Bit Shift-Left Register With Positive-Edge Clock, Serial In and Serial

Out VHDL Coding Example
--
-- 8-bit Shift-Left Register with Positive-Edge Clock,
-- Serial In, and Serial Out
--
library ieee;
entity shift_registers_1 is
port(C, SI : in std_logic;
SO : out std_logic);
end shift_registers_1;
architecture archi of shift_registers_1 is

begin
process (C)
begin
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end process;
SO <= tmp(7);
end archi;

8-Bit Shift-Left Register With Positive-Edge Clock, Serial In and Serial

Out Verilog Coding Example
//
// 8-bit Shift-Left Register with Positive-Edge Clock,
// Serial In, and Serial Out
//
module v_shift_registers_1 (C, SI, SO);

input C,SI;
output SO;
reg [7:0] tmp;
always @(posedge C)
begin
tmp = {tmp[6:0], SI};
end
assign SO = tmp[7];
endmodule
8-Bit Shift-Left Register With Negative-Edge Clock, Clock Enable,

Serial In and Serial Out Diagram
8-Bit Shift-Left Register With Negative-Edge Clock, Clock Enable,

Serial In and Serial Out Pin Descriptions
IO Pins Description
C Negative-Edge Clock
SI Serial In
SO Serial Output

8-Bit Shift-Left Register With Negative-Edge Clock, Clock Enable, Serial In

and Serial Out VHDL Coding Example
--
-- 8-bit Shift-Left Register with Negative-Edge Clock,
-- Clock Enable,Serial In, and Serial Out
--
library ieee;
entity shift_registers_2 is
port(C, SI, CE : in std_logic;
SO : out std_logic);
end shift_registers_2;
architecture archi of shift_registers_2 is

begin
process (C)
begin
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end if;
end process;
SO <= tmp(7);
end archi;

8-Bit Shift-Left Register With Negative-Edge Clock, Clock Enable, Serial In

and Serial Out Verilog Coding Example
//
// 8-bit Shift-Left Register with Negative-Edge Clock,
// Clock Enable, Serial In, and Serial Out
//
module v_shift_registers_2 (C, CE, SI, SO);

input C,SI, CE;
output SO;
reg [7:0] tmp;
always @(negedge C)
begin
if (CE)
begin
tmp = {tmp[6:0], SI};
end
end
assign SO = tmp[7];
endmodule

Dynamic Shift Registers HDL Coding Techniques

This section discusses Dynamic Shift Registers HDL Coding Techniques, and includes:
• About Dynamic Shift Registers
• Dynamic Shift Registers Log File
• Dynamic Shift Registers Related Constraints
• Dynamic Shift Registers Coding Examples
About Dynamic Shift Registers

XST can infer Dynamic Shift Registers. Once a Dynamic Shift Register has been
identified, its characteristics are handed to the XST macro generator for optimal
implementation using the primitives shown in the following table.
Devices SRL16 SRL16E SRLC16 SRLC16E SRLC32E
Spartan®-3 Yes Yes Yes Yes No
Spartan-3E
Spartan-3A
Virtex®-4 Yes Yes Yes Yes No
Virtex-5 Yes Yes Yes Yes Yes
Dynamic Shift Registers Log File

Dynamic shift registers are recognized in the Advanced HDL Synthesis step. The
XST log file reports the size of recognized dynamic shift registers during the Macro
Recognition step.
Dynamic Shift Registers Log File Example

...
=============================================
* HDL Synthesis *
=============================================
Synthesizing Unit <dynamic_shift_registers_1>.

Related source file is "dynamic_shift_registers_1.vhd".
Found 1-bit 16-to-1 multiplexer for signal <Q>.
Found 16-bit register for signal <SRL_SIG>.
Summary:
inferred 1 Multiplexer(s).
Unit <dynamic_shift_registers_1> synthesized.
=============================================
=============================================
...
Synthesizing (advanced) Unit <dynamic_shift_registers_1>.
Found 16-bit dynamic shift register for signal <Q>.
Unit <dynamic_shift_registers_1> synthesized (advanced).
=============================================

Macro Statistics
# Shift Registers : 1
16-bit dynamic shift register : 1
=============================================
...
Dynamic Shift Registers Related Constraints

Dynamic Shift Registers Coding Examples

16-Bit Dynamic Shift Register With Positive-Edge Clock, Serial In

and Serial Out Diagram
The following table shows pin descriptions for a dynamic register. The register can:
• Be either serial or parallel
• Be left or right
• Have a synchronous or asynchronous reset
• Have a depth up to 16 bits.
16-Bit Dynamic Shift Register With Positive-Edge Clock, Serial In

and Serial Out Pin Descriptions
IO Pins Description
SI Serial In
AClr Asynchronous Reset
SClr Synchronous Reset
SLoad Synchronous Parallel Load
Data Parallel Data Input Port
ClkEn Clock Enable
LeftRight Direction selection
SerialInRight Serial Input Right for Bidirectional Shift
Register
PSO Serial or Parallel Output

16-Bit Dynamic Shift Register With Positive-Edge Clock, Serial In and

Serial Out VHDL Coding Example
--
-- 16-bit dynamic shift register.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity dynamic_shift_registers_1 is
port(CLK : in std_logic;
DATA : in std_logic;
CE : in std_logic;
A : in std_logic_vector(3 downto 0);
Q : out std_logic);
end dynamic_shift_registers_1;
architecture rtl of dynamic_shift_registers_1 is

constant DEPTH_WIDTH : integer := 16;
type SRL_ARRAY is array (0 to DEPTH_WIDTH-1) of std_logic;

-- The type SRL_ARRAY can be array
-- (0 to DEPTH_WIDTH-1) of
-- std_logic_vector(BUS_WIDTH downto 0)
-- or array (DEPTH_WIDTH-1 downto 0) of
-- std_logic_vector(BUS_WIDTH downto 0)
-- (the subtype is forward (see below))
signal SRL_SIG : SRL_ARRAY;
begin
PROC_SRL16 : process (CLK)
begin
if (CLK’event and CLK = ’1’) then
if (CE = ’1’) then
SRL_SIG <= DATA & SRL_SIG(0 to DEPTH_WIDTH-2);
end if;
end if;
end process;
Q <= SRL_SIG(conv_integer(A));
end rtl;

16-Bit Dynamic Shift Register With Positive-Edge Clock, Serial In and

Serial Out Verilog Coding Example
//
// 16-bit dynamic shift register.
//
module v_dynamic_shift_registers_1 (Q,CE,CLK,D,A);

input CLK, D, CE;
input [3:0] A;
output Q;
reg [15:0] data;
assign Q = data[A];
always @(posedge CLK)

begin
if (CE == 1’b1)
data <= {data[14:0], D};
end
endmodule

Multiplexers HDL Coding Techniques

This section discusses Multiplexers HDL Coding Techniques, and includes:
• About Multiplexers
• Multiplexers Log File
• Multiplexers Related Constraints
• Multiplexers Coding Examples
About Multiplexers
This section discusses About Multiplexers, and includes:
• Multiplexers Description Styles
• Verilog Case Statements
• Verilog Case Statement Resources
• Case Implementation Style Parameter
• Multiplexers Case Statements
Multiplexers Description Styles

XST supports different description styles for multiplexers (MUX), such as:
• if-then-else
• case
If you describe a MUX using a case statement, and you do not specify all values of the
selector, the result may be latches instead of a multiplexer. When writing a MUX, you
can use dont care to describe selector values.
XST decides whether to infer the MUX during the Macro Inference step. If the MUX has
several inputs that are the same, XST can decide not to infer it. Use MUX_EXTRACT
to force XST to infer the MUX.
Verilog Case Statements

Verilog case statements can be:
• full or not full
• parallel or not parallel
A Verilog case statement is:
• full if all possible branches are specified
• parallel if it does not contain branches that can be executed simultaneously
Verilog Case Statement Resources

Verilog Case Statement Resources indicates the resources used to synthesize the
Multiplexers Case Statement Examples using the four Case Implementation Styles.
The term resources means the functionality.
For example, if you code the case statement neither full nor parallel with Case
Implementation Style set to none, from the functionality point of view, XST implements
a priority encoder + latch. But it does not inevitably mean that XST infers the priority
encoder during the Macro Recognition step.

Parameter
Value Case Implementation
Full Not Full Neither Full nor Parallel
none MUX Latch Priority Encoder + Latch
parallel MUX Latch Latch
full MUX MUX Priority Encoder
full-parallel MUX MUX MUX
Specifying full, parallel or full-parallel may result in an implementation with a

behavior that may differ from the behavior of the initial model.
Case Implementation Style Parameter

This characterization of the case statements can be guided or modified by using Case
Implementation Style. Accepted values for this parameter are:
• none
• full
• parallel
• full-parallel
Value XST Behavior
none Implements the exact behavior of the case statements
(default)
full Considers that case statements are complete and avoids latch creation
parallel Considers that the branches cannot occur in parallel and does not use a priority
encoder
full-parallel Considers that case statements are complete and that the branches cannot occur
in parallel, therefore saving latches and priority encoders

XST Design Constraints
Multiplexers Case Statements

Following are three examples of Case statements:
• Full and Parallel Case Statement
• Not Full But Parallel Case Statement
• Neither Full Nor Parallel Case Statement

Full and Parallel Case Statement

module full (sel, i1, i2, i3, i4, o1);
input [1:0] sel;
input [1:0] i1, i2, i3, i4;
output [1:0] o1;
reg [1:0] o1;
always @(sel or i1 or i2 or i3 or i4)

begin
case (sel)
2’b00: o1 = i1;
2’b01: o1 = i2;
2’b10: o1 = i3;
2’b11: o1 = i4;
endcase
end
endmodule
Not Full But Parallel Case Statement
module notfull (sel, i1, i2, i3, o1);
input [1:0] sel;
input [1:0] i1, i2, i3;
output [1:0] o1;
reg [1:0] o1;
always @(sel or i1 or i2 or i3)

begin
case (sel)
2’b00: o1 = i1;
2’b01: o1 = i2;
2’b10: o1 = i3;
endcase
end
endmodule
Neither Full Nor Parallel Case Statement

module notfull_notparallel (sel1, sel2, i1, i2, o1);
input [1:0] sel1, sel2;
input [1:0] i1, i2;
output [1:0] o1;
reg [1:0] o1;
always @(sel1 or sel2)

begin
case (2’b00)
sel1: o1 = i1;
sel2: o1 = i2;
endcase
end
endmodule

XST automatically determines the characteristics of the case statements and generates
logic using multiplexers, priority encoders, and latches that best implement the exact
behavior of the case statement.
Multiplexers Log File

The XST log file reports the type and size of recognized multiplexers (MUX) during the
Macro Recognition step.
Multiplexers Log File Example

...
Synthesizing Unit <mux>.
Related source file is multiplexers_1.vhd.
Found 1-bit 4-to-1 multiplexer for signal <o>.
Summary:
Unit <mux> synthesized.
=============================
Macro Statistics
# Multiplexers : 1
1-bit 4-to-1 multiplexer : 1
==============================
...
Explicit inference and reporting of multiplexers may vary depending on the targeted
device families. The following coding examples are limited to 4-to-1 multiplexers. They
are reported as shown above only if the target is a LUT4-based device family. For
Virtex®-5 devices, multiplexers are explicitly inferred only for sizes of 8-to-1 and above.
Multiplexers Related Constraints

• Mux Extraction (MUX_EXTRACT)
• Mux Style (MUX_STYLE)
• Enumerated Encoding (ENUM_ENCODING)
Multiplexers Coding Examples

4-to-1 1-Bit MUX Using IF Statement Diagram

4-to-1 1-Bit MUX Using IF Statement Pin Descriptions

IO Pins Description
a, b, c, d Data Inputs
s MUX Selector
o Data Output
4-to-1 1-Bit MUX Using IF Statement VHDL Coding Example

--
-- 4-to-1 1-bit MUX using an If statement.
--
library ieee;
entity multiplexers_1 is
port (a, b, c, d : in std_logic;
s : in std_logic_vector (1 downto 0);
o : out std_logic);
end multiplexers_1;
architecture archi of multiplexers_1 is

begin
process (a, b, c, d, s)
begin
if (s = "00") then o <= a;
elsif (s = "01") then o <= b;
elsif (s = "10") then o <= c;
else o <= d;
end if;
end process;
end archi;
4-to-1 1-Bit MUX Using IF Statement Verilog Coding Example

//
// 4-to-1 1-bit MUX using an If statement.
//
module v_multiplexers_1 (a, b, c, d, s, o);

input a,b,c,d;
input [1:0] s;
output o;
reg o;
always @(a or b or c or d or s)
begin
if (s == 2’b00) o = a;
else if (s == 2’b01) o = b;
else if (s == 2’b10) o = c;
else o = d;
end
endmodule

4-to-1 1-Bit MUX Using Case Statement Diagram
4-to-1 1-Bit MUX Using Case Statement Pin Descriptions

IO Pins Description
s MUX Selector
o Data Output
4-to-1 1-Bit MUX Using Case Statement VHDL Coding Example

--
-- 4-to-1 1-bit MUX using a Case statement.
--
library ieee;
o : out std_logic);
end multiplexers_2;

begin
process (a, b, c, d, s)
begin
case s is
when "00" => o <= a;
when "01" => o <= b;
when "10" => o <= c;
when others => o <= d;
end case;
end process;
end archi;

4-to-1 1-Bit MUX Using Case Statement Verilog Coding Example

//
// 4-to-1 1-bit MUX using a Case statement.
//

input a,b,c,d;
input [1:0] s;
output o;
reg o;
always @(a or b or c or d or s)
begin
case (s)
2’b00 : o = a;
2’b01 : o = b;
2’b10 : o = c;
default : o = d;
endcase
end
endmodule
4-to-1 1-Bit MUX Using Tristate Buffers Diagram
4-to-1 1-Bit MUX Using Tristate Buffers Pin Descriptions

IO Pins Description
s MUX Selector
o Data Output
4-to-1 1-Bit MUX Using Tristate Buffers VHDL Coding Example

--
-- 4-to-1 1-bit MUX using tristate buffers.
--
library ieee;
o : out std_logic);
end multiplexers_3;

begin
o <= a when (s(0)=’0’) else ’Z’;
o <= b when (s(1)=’0’) else ’Z’;
o <= c when (s(2)=’0’) else ’Z’;

o <= d when (s(3)=’0’) else ’Z’;

end archi;
4-to-1 1-Bit MUX Using Tristate Buffers Verilog Coding Example

//
// 4-to-1 1-bit MUX using tristate buffers.
//

input a,b,c,d;
input [3:0] s;
output o;
assign o = s[3] ? a :1’bz;

assign o = s[2] ? b :1’bz;
assign o = s[1] ? c :1’bz;
assign o = s[0] ? d :1’bz;
endmodule
VHDL Coding Example of a Missing Else Statement Leading to a Latch

Inference
The following coding examples illustrate how XST infers a latch when no else statement
is described at the end of an if/elsif construct. Since the else statement is missing, XST
assumes that, for the s=11 case, o retains its old value, and that a memory element is
needed. XST issues the following warning message.
WARNING:Xst:737 - Found 1-bit latch for signal <o1>. INFO:Xst
- HDL ADVISOR - Logic functions respectively driving the data
and gate enable inputs of this latch share common terms. This
situation will potentially lead to setup/hold violations and,
as a result, to simulation problems. This situation may come
from an incomplete case statement (all selector values are
not covered). You should carefully review if it was in your
intentions to describe such a latch.

Unless you actually intended to describe such a latch, add the missing else statement.
Caution! Leaving out an else statement may result in errors during simulation.
--
-- 3-to-1 1-bit MUX with a 1-bit latch.
--
library ieee;
port (a, b, c: in std_logic;
o : out std_logic);
end multiplexers_4;

begin
process (a, b, c, s)
begin
if (s = "00") then o <= a;
elsif (s = "01") then o <= b;
elsif (s = "10") then o <= c;
end if;
end process;
end archi;
Verilog Coding Example of a Missing Else Statement Leading to a Latch

Inference
//
// 3-to-1 1-bit MUX with a 1-bit latch.
//
module v_multiplexers_4 (a, b, c, s, o);
input a,b,c;
input [1:0] s;
output o;
reg o;
always @(a or b or c or s)
begin
if (s == 2’b00) o = a;
else if (s == 2’b01) o = b;
else if (s == 2’b10) o = c;
end
endmodule

Decoders HDL Coding Techniques

• About Decoders
• Decoders Log File
• Decoders Related Constraints
• Decoders Coding Examples
About Decoders
A decoder is a multiplexer the inputs of which are all constant with distinct one-hot (or
one-cold) coded values.
Decoders Log File

The XST log file reports the type and size of recognized decoders during the Macro
Recognition step.
Decoders Log File Example
Synthesizing Unit <dec>.

Related source file is decoders_1.vhd.
Found 1-of-8 decoder for signal <res>.
Summary:
inferred 1 Decoder(s).
Unit <dec> synthesized.
==============================
Macro Statistics
# Decoders : 1
1-of-8 decoder : 1
==============================
...
Decoders Related Constraints

Decoder Extraction (DECODER_EXTRACT)
Decoders Coding Examples


1-of-8 Decoder (One-Hot) Diagram
1-of-8 Decoders (One-Hot) Pin Descriptions

IO Pins Description
s Selector
res Data Output
1-of-8 Decoder (One-Hot) VHDL Coding Example

--
-- 1-of-8 decoder (One-Hot)
--
library ieee;
entity decoders_1 is
port (sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0));
end decoders_1;
architecture archi of decoders_1 is

begin
res <= "00000001" when sel = "000" else
"00000010" when sel = "001" else
"00000100" when sel = "010" else
"00001000" when sel = "011" else
"00010000" when sel = "100" else
"00100000" when sel = "101" else
"01000000" when sel = "110" else
"10000000";
end archi;
1-of-8 decoder (One-Hot) Verilog Coding Example

//
// 1-of-8 decoder (One-Hot)
//
module v_decoders_1 (sel, res);

input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel or res)

begin
case (sel)

3’b000 : res = 8’b00000001;

3’b001 : res = 8’b00000010;
3’b010 : res = 8’b00000100;
3’b011 : res = 8’b00001000;
3’b100 : res = 8’b00010000;
3’b101 : res = 8’b00100000;
3’b110 : res = 8’b01000000;
default : res = 8’b10000000;
endcase
end
endmodule
1-of-8 Decoder (One-Cold) Pin Descriptions

IO Pins Description
s Selector
res Data Output
1-of-8 decoder (One-Cold) VHDL Coding Example

--
-- 1-of-8 decoder (One-Cold)
--
library ieee;
end decoders_2;

begin
res <= "11111110" when sel = "000" else
"11111101" when sel = "001" else
"11111011" when sel = "010" else
"11110111" when sel = "011" else
"11101111" when sel = "100" else
"11011111" when sel = "101" else
"10111111" when sel = "110" else
"01111111";
end archi;

1-of-8 Decoder (One-Cold) Verilog Coding Example

//
// 1-of-8 decoder (One-Cold)
//

input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel)
begin
case (sel)
3’b000 : res = 8’b11111110;
3’b001 : res = 8’b11111101;
3’b010 : res = 8’b11111011;
3’b011 : res = 8’b11110111;
3’b100 : res = 8’b11101111;
3’b101 : res = 8’b11011111;
3’b110 : res = 8’b10111111;
default : res = 8’b01111111;
endcase
end
endmodule
Decoder With Unselected Outputs Pin Descriptions

IO Pins Description
s Selector
res Data Output
No Decoder Inference (Unused Decoder Output) VHDL Coding Example

--
-- No Decoder Inference (unused decoder output)
--
library ieee;
end decoders_3;

begin
res <= "00000001" when sel = "000" else
-- unused decoder output
"XXXXXXXX" when sel = "001" else
"00000100" when sel = "010" else
"00001000" when sel = "011" else
"00010000" when sel = "100" else
"00100000" when sel = "101" else
"01000000" when sel = "110" else
"10000000";

end archi;
No Decoder Inference (Unused Decoder Output) Verilog Coding Example

//
// No Decoder Inference (unused decoder output)
//

input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel)
begin
case (sel)
3’b000 : res = 8’b00000001;
// unused decoder output
3’b001 : res = 8’bxxxxxxxx;
3’b010 : res = 8’b00000100;
3’b011 : res = 8’b00001000;
3’b100 : res = 8’b00010000;
3’b101 : res = 8’b00100000;
3’b110 : res = 8’b01000000;
default : res = 8’b10000000;
endcase
end
endmodule
No Decoder Inference (Some Selector Values Unused) VHDL Coding

Example
--
-- No Decoder Inference (some selector values are unused)
--
library ieee;
end decoders_4;

begin
res <= "00000001" when sel = "000" else
"00000010" when sel = "001" else
"00000100" when sel = "010" else
"00001000" when sel = "011" else
"00010000" when sel = "100" else
"00100000" when sel = "101" else
-- 110 and 111 selector values are unused
"XXXXXXXX";
end archi;

No Decoder Inference (Some Selector Values Unused) Verilog Coding

Example
//
// No Decoder Inference (some selector values are unused)
//

input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel or res)

begin
case (sel)
3’b000 : res = 8’b00000001;
3’b001 : res = 8’b00000010;
3’b010 : res = 8’b00000100;
3’b011 : res = 8’b00001000;
3’b100 : res = 8’b00010000;
3’b101 : res = 8’b00100000;
// 110 and 111 selector values are unused
default : res = 8’bxxxxxxxx;
endcase
end
endmodule

Priority Encoders HDL Coding Techniques

This section discusses Priority Encoders HDL Coding Techniques, and includes:
• About Priority Encoders
• Priority Encoders Log File
• Priority Encoders Related Constraints
• Priority Encoders Coding Examples
About Priority Encoders

XST can recognize a priority encoder, but in most cases XST does not infer it. To force
priority encoder inference, use Priority Encoder Extraction (PRIORITY_EXTRACT)
with the value force.
Xilinx® recommends that you use Priority Encoder Extraction (PRIORITY_EXTRACT) on
a signal-by-signal basis. Otherwise, Priority Encoder Extraction (PRIORITY_EXTRACT)
may give less than optimal results.
Priority Encoders Log File

The XST log file reports the type and size of recognized priority encoders during the
Priority Encoders Log File Example

...
Synthesizing Unit <priority>.
Related source file is priority_encoders_1.vhd.
Found 3-bit 1-of-9 priority encoder for signal <code>.
Summary:
inferred 3 Priority encoder(s).
Unit <priority> synthesized.
==============================
Macro Statistics
# Priority Encoders : 1
3-bit 1-of-9 priority encoder : 1
==============================
...
Priority Encoders Related Constraints

Priority Encoder Extraction (PRIORITY_EXTRACT)
Priority Encoders Coding Examples

For this example XST may infer a priority encoder. Use Priority Encoder Extraction
(PRIORITY_EXTRACT) with a value of force to force its inference.

3-Bit 1-of-9 Priority Encoder Pin Descriptions

IO Pins Description
sel Selector
code Encoded Output Bus
3-Bit 1-of-9 Priority Encoder VHDL Coding Example

--
-- 3-Bit 1-of-9 Priority Encoder
--
library ieee;
entity priority_encoder_1 is
port ( sel : in std_logic_vector (7 downto 0);
code :out std_logic_vector (2 downto 0));
attribute priority_extract: string;

attribute priority_extract of priority_encoder_1: entity is "force";
end priority_encoder_1;
architecture archi of priority_encoder_1 is

begin
code <= "000" when sel(0) = ’1’ else

"001" when sel(1) = ’1’ else
"010" when sel(2) = ’1’ else
"011" when sel(3) = ’1’ else
"100" when sel(4) = ’1’ else
"101" when sel(5) = ’1’ else
"110" when sel(6) = ’1’ else
"111" when sel(7) = ’1’ else
"---";
end archi;
3-Bit 1-of-9 Priority Encoder Verilog Coding Example

//
// 3-Bit 1-of-9 Priority Encoder
//
(* priority_extract="force" *)
module v_priority_encoder_1 (sel, code);
input [7:0] sel;
output [2:0] code;
reg [2:0] code;
always @(sel)
begin
if (sel[0]) code = 3’b000;
else if (sel[1]) code = 3’b001;
else code = 3’bxxx;
end

endmodule

Logical Shifters HDL Coding Techniques

This section discusses Logical Shifters HDL Coding Techniques, and includes:
• About Logical Shifters
• Logical Shifters Log File
• Logical Shifters Related Constraints
• Logical Shifters Coding Examples
About Logical Shifters

Xilinx® defines a logical shifter as a combinatorial circuit with 2 inputs and 1 output:
• The first input is a data input that is shifted.
• The second input is a selector whose binary value defines the shift distance.
• The output is the result of the shift operation.
All of these I/Os are mandatory. Otherwise, XST does not infer a logical shifter.
When writing your Hardware Description Language (HDL) code:
• Use only logical, arithmetic, and rotate shift operators. Shift operations that fill
vacated positions with values from another signal are not recognized.
• For VHDL, you can use predefined shift (for example, SLL, SRL, ROL) or
concatenation operations only. For more information on predefined shift operations,
see the IEEE VHDL reference manual.
• Use only one type of shift operation.
• The n value in the shift operation must be incremented or decremented only by 1 for
each consequent binary value of the selector.
• The n value can be positive only.
• All values of the selector must be presented.
Logical Shifters Log File

The XST log file reports the type and size of a recognized logical shifter during the
Logical Shifters Log File Example

...
Synthesizing Unit <lshift>.
Related source file is Logical_Shifters_1.vhd.
Found 8-bit shifter logical left for signal <so>.
Summary:
inferred 1 Combinational logic shifter(s).
Unit <lshift> synthesized.
...
==============================
Macro Statistics
# Logic shifters : 1
8-bit shifter logical left : 1
==============================
...

Logical Shifters Related Constraints

Logical Shifter Extraction (SHIFT_EXTRACT)
Logical Shifters Coding Examples

The minimal size for XST to explicitly infer logical shifter macros may vary depending
on the targeted device family. The following coding examples have been validated on
LUT4-based device families such as Virtex®-4 devices. For Virtex-5 devices, logical
shifters are explicitly inferred only when the selector size is at least 3.
Logical Shifter One Diagram
Logical Shifter One Pin Descriptions

IO Pins Description
DI Data Input
SEL Shift Distance Selector
SO Data Output
Logical Shifter One VHDL Coding Example

--
-- Following is the VHDL code for a logical shifter.
--
library ieee;
use ieee.numeric_std.all;
entity logical_shifters_1 is
port(DI : in unsigned(7 downto 0);
SEL : in unsigned(1 downto 0);
SO : out unsigned(7 downto 0));
end logical_shifters_1;
architecture archi of logical_shifters_1 is

begin
with SEL select
SO <= DI when "00",
DI sll 1 when "01",
DI sll 2 when "10",
DI sll 3 when others;
end archi;

Logical Shifter One Verilog Coding Example

//
// Following is the Verilog code for a logical shifter.
//
module v_logical_shifters_1 (DI, SEL, SO);

input [7:0] DI;
input [1:0] SEL;
output [7:0] SO;
reg [7:0] SO;
always @(DI or SEL)

begin
case (SEL)
2’b00 : SO = DI;
2’b01 : SO = DI << 1;
2’b10 : SO = DI << 2;
default : SO = DI << 3;
endcase
end
endmodule
Logical Shifter Two Pin Descriptions

IO Pins Description
DI Data Input
SO Data Output
Logical Shifter Two VHDL Coding Example

XST does not infer a logical shifter for Logical Shifter Two, since not all selector values
are presented.
--
-- XST does not infer a logical shifter for this example,
-- as not all of the selector values are presented.
--
library ieee;

begin
with SEL select
SO <= DI when "00",
DI sll 1 when "01",
end archi;

Logical Shifter Two Verilog Coding Example

//
// XST does not infer a logical shifter for this example,
// as not all of the selector values are presented.
//

input [7:0] DI;
input [1:0] SEL;
output [7:0] SO;
reg [7:0] SO;
always @(DI or SEL)

begin
case (SEL)
2’b00 : SO = DI;
2’b01 : SO = DI << 1;
endcase
end
endmodule
Logical Shifter Three Pin Descriptions

IO Pins Description
DI Data Input
SO Data Output
Logical Shifter Three VHDL Coding Example

XST does not infer a logical shifter for this example, as the value is not incremented by 1
for each consequent binary value of the selector.
--
-- XST does not infer a logical shifter for this example,
-- as the value is not incremented by 1 for each consequent
-- binary value of the selector.
--
library ieee;

begin
with SEL select
SO <= DI when "00",
DI sll 1 when "01",
DI sll 3 when "10",


end archi;
Logical Shifter Three Verilog Coding Example

//
// XST does not infer a logical shifter for this example,
// as the value is not incremented by 1 for each consequent
// binary value of the selector.
//

input [7:0] DI;
input [1:0] SEL;
output [7:0] SO;
reg[7:0] SO;
always @(DI or SEL)

begin
case (SEL)
2’b00 : SO = DI;
2’b01 : SO = DI << 1;
2’b10 : SO = DI << 3;
endcase
end
endmodule

Arithmetic Operators HDL Coding Techniques

This section and includes:
• About Arithmetic Operators
• Arithmetic Operators Log File
• Arithmetic Operators Related Constraints
• Arithmetic Operators Coding Examples
About Arithmetic Operators

This section discusses Arithmetic Operators, and includes:
• Supported Arithmetic Operators
• Signed and Unsigned Operators
• Resource Sharing
Supported Arithmetic Operators

XST supports the following arithmetic operators:
• Adders with:
– Carry In
– Carry Out
– Carry In/Out
• Subtractors
• Adders/Subtractors
• Comparators:
– =
– /=
– <
– <=
– >
– >=
• Multipliers
• Dividers
Signed and Unsigned Operators

XST supports the following for signed and unsigned operators:
• Adders
• Subtractors
• Comparators
• Multipliers
For more information on signed and unsigned operators support in VHDL, see:

Resource Sharing
XST performs resource sharing for:
• Adders
• Subtractors
• Adders/subtractors
• Multipliers
Arithmetic Operators Log File

The XST log file reports the type and size of recognized adder, subtractor and
adder/subtractor during the Macro Recognition step.
Arithmetic Operators Log File Example

...
Synthesizing Unit <adder>.
Related source file is arithmetic_operations_1.vhd.
Found 8-bit adder for signal <sum>.
Summary:
inferred 1 Adder/Subtracter(s).
Unit <adder> synthesized.
=============================
Macro Statistics
# Adders/Subtractors : 1
8-bit adder : 1
==============================
Arithmetic Operators Related Constraints

• Keep (KEEP)
Arithmetic Operators Coding Examples

None

Adders, Subtractors, and Adders/Subtractors HDL Coding

Techniques
• About Adders, Subtractors, and Adders/Subtractors
• Adders, Subtractors, and Adders/Subtractors Log File
• Adders, Subtractors, and Adders/Subtractors Related Constraints
• Adders, Subtractors, and Adders/Subtractors Coding Examples
About Adders, Subtractors, and Adders/Subtractors

• Supported Device Families
• XST DSP48 Block Support
• Macro Implementation on DSP48 Blocks
• Automatic DSP48 Resource Control
Supported Device Families

The following device families allow adders and subtractors to be implemented on
DSP48 resources:
• Virtex®-4
• Virtex-5
• Spartan®-3A DSP
XST DSP48 Block Support

XST supports the one level of output registers into DSP48 blocks. If the Carry In or
Add/Sub operation selectors are registered, XST pushes these registers into the DSP48 as
well.
XST can implement an adder/subtractor in a DSP48 block if its implementation requires
only a single DSP48 resource. If an adder/subtractor macro does not fit in a single
DSP48, XST implements the entire macro using slice logic.
Macro Implementation on DSP48 Blocks

Macro implementation on DSP48 blocks is controlled by DSP Utilization Ratio
(DSP_UTILIZATION_RATIO) with a default value of auto. In auto mode, if an
adder/subtractor is a part of a more complex macro such as a filter, XST automatically
places it on the DSP block. Otherwise, XST implements adders/subtractors using LUTs.
Set the value of Use DSP48 (USE_DSP48) to yes in order to force XST to push these
macros into a DSP48. When placing an Adder/Subtractor on a DSP block, XST checks
to see if it is connected to other DSP chains. If so, XST tries to take advantage of fast
DSP connections, and connects this adder/subtractor to the DSP chain using these fast
connections.
Automatic DSP48 Resource Control

When implementing adders/subtractors on DSP48 blocks, XST performs automatic
DSP48 resource control.


maximum macro configuration, including as many registers in the DSP48 as possible.
registers.
Adders, Subtractors, and Adders/Subtractors Log File

In the log file, XST reports the details of inferred multipliers, adders, subtractors, and
registers at the HDL Synthesis step. XST reports about inferred MACs during the
Advanced HDL Synthesis Step where the MAC implementation mechanism takes place.
Adders, Subtractors, and Adders/Subtractors Log File Example
Synthesizing Unit <v_adders_4>.

Related source file is "v_adders_4.v".
Found 8-bit adder carry in/out for signal <$addsub0000>.
Summary:
inferred 1 Adder/Subtractor(s).
Unit <v_adders_4> synthesized.
===========================================================
Macro Statistics
8-bit adder carry in/out : 1
============================================================
Adders, Subtractors, and Adders/Subtractors Related Constraints

• Keep (KEEP)
Adders, Subtractors, and Adders/Subtractors Coding Examples

Unsigned 8-Bit Adder Diagram

Unsigned 8-Bit Adder Pin Descriptions IO Pins

IO Pins Description
A, B Add Operands
SUM Add Result
Unsigned 8-Bit Adder VHDL Coding Example

--
-- Unsigned 8-bit Adder
--
library ieee;
entity adders_1 is
port(A,B : in std_logic_vector(7 downto 0);
SUM : out std_logic_vector(7 downto 0));
end adders_1;
architecture archi of adders_1 is

begin
SUM <= A + B;
end archi;
Unsigned 8-Bit Adder Verilog Coding Example
//
// Unsigned 8-bit Adder
//
module v_adders_1(A, B, SUM);

input [7:0] A;
input [7:0] B;
output [7:0] SUM;
assign SUM = A + B;
endmodule
Unsigned 8-Bit Adder With Carry In Diagram

Unsigned 8-Bit Adder With Carry In Pin Descriptions IO Pins

IO Pins Description
A, B Add Operands
CI Carry In
SUM Add Result
Unsigned 8-Bit Adder With Carry In VHDL Coding Example

--
-- Unsigned 8-bit Adder with Carry In
--
library ieee;
entity adders_2 is
CI : in std_logic;
end adders_2;

begin
SUM <= A + B + CI;
end archi;
Unsigned 8-Bit Adder With Carry In Verilog Coding Example
//
// Unsigned 8-bit Adder with Carry In
//
module v_adders_2(A, B, CI, SUM);

input [7:0] A;
input [7:0] B;
input CI;
output [7:0] SUM;
assign SUM = A + B + CI;
endmodule
Unsigned 8-Bit Adder With Carry Out

Before writing a + (plus) operation with carry out in VHDL, read the arithmetic package
you plan to use. For example, std_logic_unsigned does not allow you to write + (plus)
in the following form to obtain Carry Out:
Res(9-bit) = A(8-bit) + B(8-bit)
The reason is that the size of the result for + (plus) in this package is equal to the size
of the longest argument (8 bits).

One solution for the example is to adjust the size of operands A and B to 9 bits using
concatenation.
Res <= ("0" & A) + ("0" & B);
In this case, XST recognizes that this 9-bit adder can be implemented as an 8-bit adder
with carry out.
Another solution is:
• Convert A and B to integers
• Convert the result back to the std_logic vector
• Specify the size of the vector equal to 9
Unsigned 8-Bit Adder With Carry Out Diagram
Unsigned 8-Bit Adder With Carry Out Pin Descriptions IO Pins

IO Pins Description
A, B Add Operands
SUM Add Result
CO Carry Out
Unsigned 8-Bit Adder With Carry Out VHDL Coding Example

--
-- Unsigned 8-bit Adder with Carry Out
--
library ieee;
entity adders_3 is
SUM : out std_logic_vector(7 downto 0);
CO : out std_logic);
end adders_3;

begin
tmp <= conv_std_logic_vector((conv_integer(A) + conv_integer(B)),9);

SUM <= tmp(7 downto 0);
CO <= tmp(8);
end archi;

The preceding example uses two arithmetic packages:

• std_logic_arith
Contains the integer to std_logic conversion function (conv_std_logic_vector)
• std_logic_unsigned
Contains the unsigned + (plus) operation
Unsigned 8-Bit Adder With Carry Out Verilog Coding Example

//
// Unsigned 8-bit Adder with Carry Out
//
module v_adders_3(A, B, SUM, CO);

input [7:0] A;
input [7:0] B;
output [7:0] SUM;
output CO;
wire [8:0] tmp;
assign tmp = A + B;
assign SUM = tmp [7:0];
assign CO = tmp [8];
endmodule
Unsigned 8-Bit Adder With Carry In and Carry Out Diagram
Unsigned 8-Bit Adder With Carry In and Carry Out Pin Descriptions IO Pins
IO Pins Description
A, B Add Operands
CI Carry In
SUM Add Result
CO Carry Out

Unsigned 8-Bit Adder With Carry In and Carry Out VHDL Coding Example
--
-- Unsigned 8-bit Adder with Carry In and Carry Out
--
library ieee;
entity adders_4 is
CI : in std_logic;
SUM : out std_logic_vector(7 downto 0);
CO : out std_logic);
end adders_4;

begin
tmp <= conv_std_logic_vector((conv_integer(A) + conv_integer(B) + conv_integer(CI)),9);

SUM <= tmp(7 downto 0);
CO <= tmp(8);
end archi;
Unsigned 8-Bit Adder With Carry In and Carry Out Verilog Coding Example
//
// Unsigned 8-bit Adder with Carry In and Carry Out
//
module v_adders_4(A, B, CI, SUM, CO);

input CI;
input [7:0] A;
input [7:0] B;
output [7:0] SUM;
output CO;
wire [8:0] tmp;
assign tmp = A + B + CI;

assign SUM = tmp [7:0];
assign CO = tmp [8];
endmodule
Signed 8-Bit Adder Diagram

Signed 8-Bit Adder Pin Descriptions IO Pins

IO Pins Description
A, B Add Operands
SUM Add Result
Signed 8-Bit Adder VHDL Coding Example

--
-- Signed 8-bit Adder
--
library ieee;
entity adders_5 is
end adders_5;

begin
SUM <= A + B;
end archi;
Signed 8-Bit Adder Verilog Coding Example

//
// Signed 8-bit Adder
//
module v_adders_5 (A,B,SUM);

input signed [7:0] A;
input signed [7:0] B;
output signed [7:0] SUM;
wire signed [7:0] SUM;
assign SUM = A + B;
endmodule
Unsigned 8-Bit Subtractor Diagram

Unsigned 8-Bit Subtractor Pin Descriptions

IO Pins Description
A, B Sub Operands
RES Sub Result
Unsigned 8-Bit Subtractor VHDL Coding Example

--
-- Unsigned 8-bit Subtractor
--
library ieee;
entity adders_6 is
RES : out std_logic_vector(7 downto 0));
end adders_6;

begin
RES <= A - B;
end archi;
Unsigned 8-Bit Subtractor Verilog Coding Example
//
// Unsigned 8-bit Subtractor
//
module v_adders_6(A, B, RES);

input [7:0] A;
input [7:0] B;
output [7:0] RES;
assign RES = A - B;
endmodule
Unsigned 8-Bit Subtractor With Borrow In Pin Descriptions

IO Pins Description
A, B Sub Operands
BI Borrow In
RES Sub Result

Unsigned 8-Bit Subtractor With Borrow In VHDL Coding Example

--
-- Unsigned 8-bit Subtractor with Borrow In
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adders_8 is
BI : in std_logic;
end adders_8;
begin
RES <= A - B - BI;
end archi;
Unsigned 8-Bit Subtractor With Borrow In Verilog Coding Example

//
// Unsigned 8-bit Subtractor with Borrow In
//
module v_adders_8(A, B, BI, RES);

input [7:0] A;
input [7:0] B;
input BI;
output [7:0] RES;
assign RES = A - B - BI;
endmodule
Unsigned 8-Bit Adder/Subtractor Diagram

Unsigned 8-Bit Adder/Subtractor Pin Descriptions

IO Pins Description
A, B Add/Sub Operands
OPER Add/Sub Select
SUM Add/Sub Result
Unsigned 8-Bit Adder/Subtractor VHDL Coding Example

--
-- Unsigned 8-bit Adder/Subtractor
--
library ieee;
entity adders_7 is
OPER: in std_logic;
end adders_7;

begin
RES <= A + B when OPER=’0’

else A - B;
end archi;
Unsigned 8-Bit Adder/Subtractor Verilog Coding Example

//
// Unsigned 8-bit Adder/Subtractor
//
module v_adders_7(A, B, OPER, RES);

input OPER;
input [7:0] A;
input [7:0] B;
output [7:0] RES;
reg [7:0] RES;
always @(A or B or OPER)

begin
if (OPER==1’b0) RES = A + B;
else RES = A - B;
end
endmodule

Comparators HDL Coding Techniques

This section discusses Comparators HDL Coding Techniques, and includes:
• About Comparators
• Comparators Log File
• Comparators Related Constraints
• Comparators Coding Examples
About Comparators
Not applicable.
Comparators Log File

The XST log file reports the type and size of recognized comparators during the Macro
Recognition step.
Comparators Log File Example

...
Synthesizing Unit <compar>.
Related source file is comparators_1.vhd.
Found 8-bit comparator greatequal for signal <$n0000> created at line 10.
Summary:
inferred 1 Comparator(s).
Unit <compar> synthesized.
=============================
Macro Statistics
# Comparators : 1
8-bit comparator greatequal : 1
==============================
...
Comparators Related Constraints

None
Comparators Coding Examples

Unsigned 8-Bit Greater or Equal Comparator Diagram
Unsigned 8-Bit Greater or Equal Comparator Pin Descriptions

IO Pins Description
A, B Comparison Operands
CMP Comparison Result

Unsigned 8-Bit Greater or Equal Comparator VHDL Coding Example

--
-- Unsigned 8-bit Greater or Equal Comparator
--
library ieee;
entity comparator_1 is
CMP : out std_logic);
end comparator_1;
architecture archi of comparator_1 is

begin
CMP <= ’1’ when A >= B else ’0’;
end archi;
Unsigned 8-Bit Greater or Equal Comparator Verilog Coding Example

//
// Unsigned 8-bit Greater or Equal Comparator
//
module v_comparator_1 (A, B, CMP);

input [7:0] A;
input [7:0] B;
output CMP;
assign CMP = (A >= B) ? 1’b1 : 1’b0;

endmodule

Multipliers HDL Coding Techniques

This section discusses Multipliers HDL Coding Techniques, and includes:
• About Multipliers
• Multipliers (Virtex®-4, Virtex-5, and Spartan®-3A DSP Devices)
• Multipliers Log File
• Multipliers Related Constraints
• Multipliers Coding Examples
About Multipliers
This section discusses Multipliers, and includes:
• Implementing a Multiplier
• Registered Multipliers
• Multiplication with Constant
Implementing a Multiplier
When implementing a multiplier, the size of the resulting signal is equal to the sum of
two operand lengths. For example, if you multiply A (8-bit signal) by B (4-bit signal),
the size of the result must be declared as a 12-bit signal.
Registered Multipliers
In instances where a multiplier would have a registered output, XST infers a unique
registered multiplier for the following devices:
• Virtex®-4
• Virtex-5
This registered multiplier is 18x18 bits.
Under the following conditions, a registered multiplier is not used, and a multiplier +
register is used instead.
• Output from the multiplier goes to any component other than the register.
• The Multiplier Style (MULT_STYLE) constraint is set to:
lut
• The multiplier is asynchronous.
• The multiplier has control signals other than synchronous reset or clock enable.
• The multiplier does not fit in a single 18x18 bit block multiplier.
The following pins are optional for a registered multiplier:
• Clock enable port
• Synchronous and asynchronous reset, and load ports
Multiplication with Constant

When one of the arguments is a constant, XST can create efficient dedicated
implementations of a multiplier with a constant using two methods:
• Constant Coefficient Multiplier (KCM)
• Canonical Signed Digit (CSD)

Dedicated implementations do not always provide the best results for multiplication
with constants. XST can automatically choose between KCM or standard multiplier
implementation. The CSD method cannot be automatically chosen. Use Mux Style
(MUX_STYLE) to force CSD implementation.
XST does not support KCM or CSD implementation for signed numbers.
If the either of the arguments is larger than 32 bits, XST does not use KCM or CSD
implementation, even if it is specified with Multiplier Style (MULT_STYLE).
Multipliers (Virtex-4, Virtex-5, and Spartan-3A DSP Devices)

Note This section applies to Virtex®-4 devices, Virtex-5 devices, and Spartan®-3A
DSP devices only.
This section discusses Multipliers (Virtex-4, Virtex-5, and Spartan-3A DSP Devices),
and includes:
• Implementing Multipliers on DSP48 Resources
• Multiple DSP48 Resources
• Recognizing the Multiplier Style Constraint
Implementing Multipliers on DSP48 Resources

Virtex-4 devices, Virtex-5 devices, and Spartan-3A DSP devices allow multipliers to
be implemented on DSP48 resources. XST supports the registered version of these
macros and can push up to 2 levels of input registers and 2 levels of output registers
into DSP48 blocks.
Multiple DSP48 Resources

If a multiplier implementation requires multiple DSP48 resources, XST automatically
decomposes it onto multiple DSP48 blocks. Depending on the operand size, and to
obtain the best performance, XST may implement most of a multiplier using DSP48
blocks, and use slice logic for the rest of the macro. For example, it is not sufficient to use
a single DSP48 to implement an 18x18 unsigned multiplier. In this case, XST implements
most of the logic in one DSP48, and the rest in LUTs.
For Virtex-4 devices, Virtex-5 devices, and Spartan-3A DSP devices, XST can infer
pipelined multipliers, not only for the LUT implementation, but for the DSP48
implementation as well.

Macro implementation on DSP48 blocks is controlled by the Use DSP48 (USE_DSP48)
constraint or command line option, with a default value of auto. In this mode, XST
implements multipliers taking into account available DSP48 resources in the device.
In auto mode, use DSP Utilization Ratio (DSP_UTILIZATION_RATIO) to control DSP48
resources for synthesis. By default, XST tries to utilize all DSP48 resources.
DSP48 Block Resources.
Recognizing the Multiplier Style Constraint

XST can automatically recognize the Multiplier Style (MULT_STYLE) constraint with
values lut and block and then convert it to Use DSP48 (USE_DSP48).

Xilinx® recommends:
• Use Use DSP48 (USE_DSP48) for Virtex-4 devices and Virtex-5 devices to define
FPGA resources used for multiplier implementation.
• Use Multiplier Style (MULT_STYLE) to define the multiplier implementation
method on the selected FPGA resources.
The following rules apply:
• If Use DSP48 (USE_DSP48) is set to auto or yes, you may use mult_style=pipe_block
to pipeline the DSP48 implementation if the multiplier implementation requires
multiple DSP48 blocks.
• If Use DSP48 (USE_DSP48) is set to no, use mult_style=pipe_lut|KCM|CSD to
define the multiplier implementation method on LUTs.

registers.
Multipliers Log File

The XST log file reports the type and size of recognized multipliers during the Macro
Recognition step.
Multipliers Log File Example

...
Synthesizing Unit <mux>.
Related source file is multiplexers_1.vhd.
Found 1-bit 4-to-1 multiplexer for signal <o>.
Summary:
Unit <mux> synthesized.
=============================
Macro Statistics
# Multiplexers : 1
1-bit 4-to-1 multiplexer : 1
==============================
...
Multipliers Related Constraints

• Multiplier Style (MULT_STYLE)
• Keep (KEEP)
Multipliers Coding Examples


Unsigned 8x4-Bit Multiplier Diagram
Unsigned 8x4-Bit Multiplier Pin Descriptions

IO Pins Description
A, B MULT Operands
RES MULT Result
Unsigned 8x4-Bit Multiplier VHDL Coding Example

--
-- Unsigned 8x4-bit Multiplier
--
library ieee;
entity multipliers_1 is
port(A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(3 downto 0);
end multipliers_1;
architecture beh of multipliers_1 is

begin
RES <= A * B;
end beh;
Unsigned 8x4-Bit Multiplier Verilog Coding Example

//
// Unsigned 8x4-bit Multiplier
//
module v_multipliers_1(A, B, RES);

input [7:0] A;
input [3:0] B;
output [11:0] RES;
assign RES = A * B;
endmodule

Sequential Complex Multipliers HDL Coding Techniques

This section discusses Sequential Complex Multipliers HDL Coding Techniques, and
includes:
• About Sequential Complex Multipliers
• Sequential Complex Multipliers Log File
• Sequential Complex Multipliers Related Constraints
• Sequential Complex Multipliers Coding Examples
About Sequential Complex Multipliers

A sequential complex multiplier requires:
• Four cycles to make a complete multiplication by accumulating intermediate results.
• One DSP block for implementation.
Multiplying two complex numbers A and B requires four cycles.
The first two first cycles compute:
Res_real = A_real * B_real - A_imag * B_imag
The second two cycles compute:
Res_imag = A_real * B_imag + A_imag * B_real
While several templates could be used to describe the above functionality, XST does not
support using enum or integer types to describe the different DSP modes and store
the enum values. Instead, Xilinx® recommends a very regular template to ease XST
inferencing. This general accumulator template allows XST to inference a single DSP to
perform the following operations:
• Load:P <= Value
• Load: P <= -Value
• Accumulate: P <= P + Value
• Accumulate: P <= P - Value
This template works with the following two control signals that perform the above
four operations when combined:
• load
• addsub
Sequential Complex Multipliers Log File

None
Sequential Complex Multipliers Related Constraints

None
Sequential Complex Multipliers Coding Examples


Signed 18x18-bit Sequential Complex Multiplier Pin Descriptions

IO Pins Description
CLK Clock Signal
Oper_Load, Oper_AddSub Control Signals controlling Load and AddSub
Operations
A, B MULT Operands
RES MULT Result
Signed 18x18-bit Sequential Complex Multiplier VHDL Coding Example

--
-- Sequential Complex Multiplier
--
library ieee;
generic(A_WIDTH: positive:=18;
B_WIDTH: positive:=18;
RES_WIDTH: positive:=48);
port( CLK: in std_logic;
A: in signed(A_WIDTH-1 downto 0);
B: in signed(B_WIDTH-1 downto 0);
Oper_Load: in std_logic;
Oper_AddSub: in std_logic;
-- Oper_Load Oper_AddSub Operation
-- 0 0 R= +A*B
-- 0 1 R= -A*B
-- 1 0 R=R+A*B
-- 1 1 R=R-A*B
RES: out signed(RES_WIDTH-1 downto 0)

);
end multipliers_8;
constant P_WIDTH: integer:=A_WIDTH+B_WIDTH;
signal oper_load0: std_logic:=’0’;

signal oper_addsub0: std_logic:=’0’;
signal p1: signed(P_WIDTH-1 downto 0):=(others=>’0’);

signal oper_load1: std_logic:=’0’;
signal oper_addsub1: std_logic:=’0’;
signal res0: signed(RES_WIDTH-1 downto 0);

begin
process (clk)
variable acc: signed(RES_WIDTH-1 downto 0);
begin
if rising_edge(clk) then

oper_load0 <= Oper_Load;

oper_addsub0 <= Oper_AddSub;
p1 <= A*B;
oper_load1 <= oper_load0;
oper_addsub1 <= oper_addsub0;
if (oper_load1=’1’) then
acc := res0;
else
acc := (others=>’0’);
end if;
if (oper_addsub1=’1’) then
res0 <= acc-p1;
else
res0 <= acc+p1;
end if;
end if;
end process;
RES <= res0;
end architecture;

Signed 18x18-bit Sequential Complex Multiplier Verilog Coding Example

module v_multipliers_8(CLK,A,B,Oper_Load,Oper_AddSub, RES);
parameter A_WIDTH = 18;
parameter B_WIDTH = 18;
parameter RES_WIDTH = 48;
parameter P_WIDTH = A_WIDTH+B_WIDTH;
input CLK;
input signed [A_WIDTH-1:0] A, B;
input Oper_Load, Oper_AddSub;

// Oper_Load Oper_AddSub Operation
// 0 0 R= +A*B
// 0 1 R= -A*B
// 1 0 R=R+A*B
// 1 1 R=R-A*B
output [RES_WIDTH-1:0] RES;
reg oper_load0 = 0;
reg oper_addsub0 = 0;
reg signed [P_WIDTH-1:0] p1 = 0;

reg oper_load1 = 0;
reg oper_addsub1 = 0;
reg signed [RES_WIDTH-1:0] res0 = 0;

reg signed [RES_WIDTH-1:0] acc;

begin
oper_load0 <= Oper_Load;
oper_addsub0 <= Oper_AddSub;
p1 <= A*B;
oper_load1 <= oper_load0;
oper_addsub1 <= oper_addsub0;
if (oper_load1==1’b1)
acc = res0;
else
acc = 0;
if (oper_addsub1==1’b1)
res0 <= acc-p1;
else
res0 <= acc+p1;
end
assign RES = res0;
endmodule

Pipelined Multipliers HDL Coding Techniques

This section discusses Pipelined Multipliers HDL Coding Techniques, and includes:
• About Pipelined Multipliers
• Pipelined Multipliers Log File
• Pipelined Multipliers Related Constraints
• Pipelined Multipliers Coding Examples
About Pipelined Multipliers

This section discusses About Pipelined Multipliers, and includes:
• Inferring Pipelined Multipliers
• Maximizing Performance
• Implementing Unused Stages
• XST Limitations
Inferring Pipelined Multipliers

In order to increase the speed of designs with large multipliers, XST can infer pipelined
multipliers. By interspersing registers between the stages of large multipliers, pipelining
can significantly increase the overall frequency of your design. The effect of pipelining
is similar to Flip-Flop Retiming.
To insert pipeline stages:
1. Describe the necessary registers in your HDL code
2. Place them after any multipliers
3. Set Multiplier Style (MULT_STYLE) to:
pipe_lut
XST can also pipeline an implementation when:
• The target is a Virtex®-4 device or a Virtex-5 device, and
• Implementation of a multiplier requires multiple DSP48 blocks
Set Multiplier Style (MULT_STYLE) in this instance to:
pipe_block
Maximizing Performance
In order to reach the maximum multiplier speed, XST uses the maximum number of
available registers when:
• XST detects valid registers for pipelining, and
• Multiplier Style (MULT_STYLE) is set to:
pipe_lut or pipe_block
In order to obtain the best frequency, XST automatically calculates the maximum
number of registers for each multiplier .
During the Advanced HDL Synthesis step, the XST HDL Advisor advises you to specify
the optimum number of register stages if:
• You have not specified sufficient register stages, and
• Multiplier Style (MULT_STYLE) is coded directly on a signal,

Implementing Unused Stages

XST implements the unused stages as shift registers if:
• The number of registers placed after the multiplier exceeds the maximum required,
and
• Shift register extraction is activated
XST Limitations
XST has the following limitations:
• XST cannot pipeline hardware Multipliers (implementation using MULT18X18S
resource)
• XST cannot pipeline Multipliers if registers contain async set/reset or sync reset
signals. XST can pipeline if registers contain sync reset signals.
Pipelined Multipliers Log File

Following is a Pipelined Multipliers Log File Example.
Pipelined Multipliers Log File Example

====================================================================
* HDL Synthesis *
====================================================================
Synthesizing Unit <multipliers_2>.

Related source file is "multipliers_2.vhd".
Found 36-bit register for signal <MULT>.
Found 18-bit register for signal <a_in>.
Found 18-bit register for signal <b_in>.
Found 18x18-bit multiplier for signal <mult_res>.
Found 36-bit register for signal <pipe_1>.
Summary:
inferred 1 Multiplier(s).
Unit <multipliers_2> synthesized.
...
====================================================================
====================================================================
Synthesizing (advanced) Unit <multipliers_2>.

Found pipelined multiplier on signal <mult_res>:
- 4 pipeline level(s) found in a register connected to the
multiplier macro output.
Pushing register(s) into the multiplier macro.
INFO:Xst - HDL ADVISOR - You can improve the performance of the
multiplier Mmult_mult_res by adding 1 register level(s).
Unit <multipliers_2> synthesized (advanced).
====================================================================
Macro Statistics
# Multipliers : 1
18x18-bit registered multiplier : 1
====================================================================

Pipelined Multipliers Related Constraints

• Keep (KEEP)
Pipelined Multipliers Coding Examples

Pipelined Multiplier (Outside, Single) Diagram
Pipelined Multiplier (Outside, Single) Pin Descriptions

IO Pins Description
clk Positive-Edge Clock
A, B MULT Operands
MULT MULT Result
Pipelined Multiplier (Outside, Single) VHDL Coding Example

--
-- Pipelined multiplier
-- The multiplication operation placed outside the
-- process block and the pipeline stages represented
-- as single registers.
--
library ieee;
generic(A_port_size : integer := 18;
B_port_size : integer := 18);
port(clk : in std_logic;
A : in unsigned (A_port_size-1 downto 0);
B : in unsigned (B_port_size-1 downto 0);
MULT : out unsigned ( (A_port_size+B_port_size-1) downto 0));
attribute mult_style: string;

attribute mult_style of multipliers_2: entity is "pipe_lut";
end multipliers_2;

signal a_in, b_in : unsigned (A_port_size-1 downto 0);
signal mult_res : unsigned ( (A_port_size+B_port_size-1) downto 0);
signal pipe_1,
pipe_2,

pipe_3 : unsigned ((A_port_size+B_port_size-1) downto 0);
begin
mult_res <= a_in * b_in;
process (clk)
begin
if (clk’event and clk=’1’) then
a_in <= A; b_in <= B;
pipe_1 <= mult_res;
pipe_2 <= pipe_1;
pipe_3 <= pipe_2;
MULT <= pipe_3;
end if;
end process;
end beh;
Pipelined Multiplier (Outside, Single) Verilog Coding Example

//
// Pipelined multiplier
// The multiplication operation placed outside the
// always block and the pipeline stages represented
// as single registers.
//
(*mult_style="pipe_lut"*)
module v_multipliers_2(clk, A, B, MULT);
input clk;
input [17:0] A;
input [17:0] B;
output [35:0] MULT;
reg [35:0] MULT;
reg [17:0] a_in, b_in;
wire [35:0] mult_res;
reg [35:0] pipe_1, pipe_2, pipe_3;
assign mult_res = a_in * b_in;
always @(posedge clk)

begin
a_in <= A; b_in <= B;
pipe_1 <= mult_res;
pipe_2 <= pipe_1;
pipe_3 <= pipe_2;
MULT <= pipe_3;
end
endmodule
Pipelined Multiplier (Inside, Single) Pin Descriptions

IO Pins Description
A, B MULT Operands
MULT MULT Result

Pipelined Multiplier (Inside, Single) VHDL Coding Example

--
-- The multiplication operation placed inside the
-- as single registers.
--
library ieee;
generic(A_port_size: integer := 18;
B_port_size: integer := 18);
MULT : out unsigned ((A_port_size+B_port_size-1) downto 0));

end multipliers_3;

signal mult_res : unsigned ((A_port_size+B_port_size-1) downto 0);
signal pipe_2,
pipe_3 : unsigned ((A_port_size+B_port_size-1) downto 0);
begin
process (clk)
begin
a_in <= A; b_in <= B;
pipe_2 <= mult_res;
pipe_3 <= pipe_2;
MULT <= pipe_3;
end if;
end process;
end beh;
Pipelined Multiplier (Inside, Single) Verilog Coding Example

//
// The multiplication operation placed inside the
// process block and the pipeline stages are represented
// as single registers.
//
input clk;
input [17:0] A;
input [17:0] B;
output [35:0] MULT;
reg [35:0] MULT;
reg [35:0] mult_res;
reg [35:0] pipe_2, pipe_3;

begin
a_in <= A; b_in <= B;
pipe_2 <= mult_res;
pipe_3 <= pipe_2;
MULT <= pipe_3;
end
endmodule
Pipelined Multiplier (Outside, Shift) Pin Descriptions

IO Pins Description
A, B MULT Operands
MULT MULT Result
Pipelined Multiplier (Outside, Shift) VHDL Coding Example

--
-- The multiplication operation placed outside the
-- as shift registers.
--
library ieee;
generic(A_port_size: integer := 18;
B_port_size: integer := 18);
MULT : out unsigned ( (A_port_size+B_port_size-1) downto 0));

end multipliers_4;

signal mult_res : unsigned ((A_port_size+B_port_size-1) downto 0);
type pipe_reg_type is array (2 downto 0) of unsigned ((A_port_size+B_port_size-1) downto 0);

signal pipe_regs : pipe_reg_type;
begin
process (clk)
begin
a_in <= A; b_in <= B;
pipe_regs <= mult_res & pipe_regs(2 downto 1);
MULT <= pipe_regs(0);
end if;
end process;
end beh;

Pipelined Multiplier (Outside, Shift) Verilog Coding Example

//
// The multiplication operation placed outside the
// always block and the pipeline stages represented
// as shift registers.
//
input clk;
input [17:0] A;
input [17:0] B;
output [35:0] MULT;
reg [35:0] MULT;
wire [35:0] mult_res;
reg [35:0] pipe_regs [2:0];
integer i;
assign mult_res = a_in * b_in;

begin
a_in <= A; b_in <= B;
pipe_regs[2] <= mult_res;

for (i=0; i<=1; i=i+1) pipe_regs[i] <= pipe_regs[i+1];
MULT <= pipe_regs[0];

end
endmodule

Multiply Adder/Subtractors HDL Coding Techniques

This section discusses Multiply Adder/Subtractors HDL Coding Techniques, and
includes:
• About Multiply Adder/Subtractors
• Multiply Adder/Subtractors in Virtex-4 Devices and Virtex-5 Devices
• Multiply Adder/Subtractors Log File
• Multiply Adder/Subtractors Related Constraints
• Multiply Adder/Subtractors Coding Examples
About Multiply Adder/Subtractors

The Multiply Adder/Subtractor macro is a complex macro consisting of several basic
macros such as:
• Multipliers
• Adder/subtractors
• Registers
The recognition of this complex macro enables XST to implement it on dedicated DSP48
resources in the following devices:
• Virtex®-4
• Virtex-5
Multiply Adder/Subtractors in Virtex-4 Devices and Virtex-5 Devices

This section discusses Multiply Adder/Subtractors in Virtex®-4 Devices and Virtex-5
Devices, and includes:
• XST Registered Macro Support
XST Registered Macro Support

XST supports the registered version of this macro and can push up to:
• Two levels of input registers on multiplier inputs
• One register level on the Adder/Subtractor input
• One level of output register into the DSP48 block
If the Carry In or Add/Sub operation selectors are registered, XST pushes these registers
into the DSP48. In addition, the multiplication operation could be registered as well.

XST can implement a multiply adder/subtractor in a DSP48 block if its implementation
requires only a single DSP48 resource. If the macro exceeds the limits of a single DSP48,
XST processes it as two separate Multiplier and Adder/Subtractor macros, making
independent decisions on each macro.
• Multipliers Hardware Description Language (HDL) Coding Techniques
• Adders, Subtractors, and Adders/Subtractors Hardware Description Language
(HDL) Coding Techniques


Macro implementation on DSP48 blocks is controlled by Use DSP48 (USE_DSP48) with a
default value of auto. In this mode, XST implements multiply adder/subtractors taking
into account DSP48 resources in the device.
In auto mode, use DSP Utilization Ratio (DSP_UTILIZATION_RATIO) to control DSP48
resources for the synthesis. By default, XST tries to utilize all available DSP48 resources.

registers.
Multiply Adder/Subtractors Log File

In the log file, XST reports the details of inferred multipliers, adder/subtractors and
registers at the HDL Synthesis step. The composition of multiply adder/subtractor
macros happens at the Advanced HDL Synthesis step. XST reports information about
inferred MACs, because they are implemented within the MAC implementation
mechanism.
Multiply Adder/Subtractors Log File Example

====================================================================
* HDL Synthesis *
====================================================================
Synthesizing Unit <multipliers_6>.

Related source file is "multipliers_6.vhd".
Found 8-bit register for signal <A_reg1>.
Found 8-bit register for signal <A_reg2>.
Found 8-bit register for signal <B_reg1>.
Found 8-bit register for signal <B_reg2>.
Found 8x8-bit multiplier for signal <mult>.
Found 16-bit addsub for signal <multaddsub>.
Summary:
Unit <multipliers_6> synthesized.
...
====================================================================
====================================================================
...
Synthesizing (advanced) Unit <Mmult_mult>.
Multiplier <Mmult_mult> in block <multipliers_6> and adder/subtractor
<Maddsub_multaddsub> in block <multipliers_6> are combined into a
MAC<Mmac_Maddsub_multaddsub>.
The following registers are also absorbed by the MAC: <A_reg2> in block
<multipliers_6>, <A_reg1> in block <multipliers_6>, <B_reg2> in
block <multipliers_6>, <B_reg1> in block <multipliers_6>.
Unit <Mmult_mult> synthesized (advanced).
====================================================================
Macro Statistics
# MACs : 1
8x8-to-16-bit MAC : 1

====================================================================
Multiply Adder/Subtractors Related Constraints

• Keep (KEEP)
Multiply Adder/Subtractors Coding Examples

Multiplier Adder With 2 Register Levels on Multiplier Inputs

Diagram
Multiplier Adder With 2 Register Levels on Multiplier Inputs Pin

Descriptions
IO Pins Description
A, B, C MULT-Add Operands
RES MULT-Add Result
Multiplier Adder With 2 Register Levels on Multiplier Inputs VHDL Coding

Example
--
-- Multiplier Adder with 2 Register Levels on Multiplier Inputs
--
library IEEE;
generic (p_width: integer:=8);
port (clk : in std_logic;
A, B, C : in std_logic_vector(p_width-1 downto 0);
RES : out std_logic_vector(p_width*2-1 downto 0));
end multipliers_5;

signal A_reg1, A_reg2,
B_reg1, B_reg2 : std_logic_vector(p_width-1 downto 0);

signal multaddsub : std_logic_vector(p_width*2-1 downto 0);

begin
multaddsub <= A_reg2 * B_reg2 + C;
process (clk)
begin
A_reg1 <= A; A_reg2 <= A_reg1;
B_reg1 <= B; B_reg2 <= B_reg1;
end if;
end process;
RES <= multaddsub;
end beh;
Multiplier Adder With 2 Register Levels on Multiplier Inputs Verilog Coding
Example
//
// Multiplier Adder with 2 Register Levels on Multiplier Inputs
//
module v_multipliers_5 (clk, A, B, C, RES);
input clk;
input [7:0] A;
input [7:0] B;
input [7:0] C;
output [15:0] RES;
reg [7:0] A_reg1, A_reg2, B_reg1, B_reg2;
wire [15:0] multaddsub;

begin
end
assign multaddsub = A_reg2 * B_reg2 + C;

assign RES = multaddsub;
endmodule
Multiplier Adder/Subtractor With 2 Register Levels On Multiplier

Inputs Diagram

Multiplier Adder/Subtractor With 2 Register Levels On Multiplier

Inputs Pin Descriptions
IO Pins Description
add_sub AddSub Selector
A, B, C MULT-AddSub Operands
RES MULT-AddSub Result
Multiplier Adder/Subtractor With 2 Register Levels On Multiplier Inputs

VHDL Coding Example
--
-- Multiplier Adder/Subtractor with
-- 2 Register Levels on Multiplier Inputs
--
library IEEE;
port (clk,add_sub: in std_logic;
A, B, C: in std_logic_vector(p_width-1 downto 0);
RES: out std_logic_vector(p_width*2-1 downto 0));
end multipliers_6;

signal A_reg1, A_reg2,
B_reg1, B_reg2 : std_logic_vector(p_width-1 downto 0);
signal mult, multaddsub : std_logic_vector(p_width*2-1 downto 0);
begin
mult <= A_reg2 * B_reg2;

multaddsub <= C + mult when add_sub = ’1’ else C - mult;
process (clk)
begin
end if;
end process;
RES <= multaddsub;
end beh;
Multiplier Adder/Subtractor With 2 Register Levels On Multiplier Inputs

//
// Multiplier Adder/Subtractor with
// 2 Register Levels on Multiplier Inputs
//
module v_multipliers_6 (clk, add_sub, A, B, C, RES);
input clk,add_sub;
input [7:0] A;
input [7:0] B;
input [7:0] C;

output [15:0] RES;

reg [7:0] A_reg1, A_reg2, B_reg1, B_reg2;
wire [15:0] mult, multaddsub;

begin
end
assign mult = A_reg2 * B_reg2;

assign multaddsub = add_sub ? C + mult : C - mult;
assign RES = multaddsub;
endmodule

Multiply Accumulate HDL Coding Techniques

This section discusses Multiply Accumulate HDL Coding Techniques, and includes:
• About Multiply Accumulate
• Multiply Accumulate in Virtex-4 Devices and Virtex-5 Devices
• Multiply Accumulate Log File
• Multiply Accumulate Related Constraints
• Multiply Accumulate Coding Examples
About Multiply Accumulate

The Multiply Accumulate macro is a complex macro consisting of several basic macros
such as:
• Multipliers
• Accumulators
• Registers
The recognition of this complex macro enables XST to implement it on dedicated DSP48
resources in the following devices:
• Virtex®-4
• Virtex-5
Multiply Accumulate in Virtex-4 Devices and Virtex-5 Devices

This section discusses Multiply Accumulate in Virtex®-4 Devices and Virtex-5 Devices,
and includes:
• XST Registered Macro Support
• Multipliers HDL Coding Techniques
• Accumulators HDL Coding Techniques
XST Registered Macro Support

XST supports the registered version of this macro, and can push up to 2 levels of input
registers into the DSP48 block. If Adder/Subtractor operation selectors are registered,
XST pushes these registers into the DSP48. In addition, the multiplication operation
could be registered as well.

XST can implement a multiply accumulate in a DSP48 block if its implementation
requires only a single DSP48 resource. If the macro exceeds the limits of a single
DSP48, XST processes it as two separate Multiplier and Accumulate macros, making
independent decisions on each macro.


Macro implementation on DSP48 blocks is controlled by the Use DSP48 (USE_DSP48)
constraint or command line option, with a default value of auto. In auto mode, XST
implements multiply accumulate taking into account available DSP48 resources in the
device.
In auto mode, use DSP Utilization Ratio (DSP_UTILIZATION_RATIO) to control
DSP48 resources. XST tries to utilize as many DSP48 resources as possible. For more
information, see DSP48 Block Resources.

To shape a macro in a specific way, use the Keep (KEEP) constraint. For example, to
exclude the first register stage from the DSP48, place Keep (KEEP) constraints on the
outputs of these registers.
Multiply Accumulate Log File

XST reports the following information in the Multiply Accumulate Log File.
Step Report
HDL Synthesis Details of inferred multipliers, accumulators
and registers
Advanced HDL Synthesis Composition of multiply accumulate macros
Multiply Accumulate Log File Example

====================================================================
* HDL Synthesis *
====================================================================
...
Synthesizing Unit <multipliers_7a>.
Related source file is "multipliers_7a.vhd".
Found 8x8-bit multiplier for signal <$n0002> created at line 28.
Found 16-bit up accumulator for signal <accum>.
Found 16-bit register for signal <mult>.
Summary:
inferred 1 Accumulator(s).
Unit <multipliers_7a> synthesized....
====================================================================
====================================================================
...
Synthesizing (advanced) Unit <Mmult__n0002>.
Multiplier <Mmult__n0002> in block <multipliers_7a> and accumulator
<accum> in block <multipliers_7a> are combined into a MAC<Mmac_accum>.
The following registers are also absorbed by the MAC: <mult> in block
<multipliers_7a>. Unit <Mmult__n0002> synthesized (advanced).
====================================================================
Macro Statistics
# MACs : 1
8x8-to-16-bit MAC : 1
====================================================================

Multiply Accumulate Related Constraints

• Keep (KEEP)
Multiply Accumulate Coding Examples

Multiplier Up Accumulate With Register After Multiplication

Diagram
Multiplier Up Accumulate With Register After Multiplication Pin

Descriptions
IO Pins Description
reset Synchronous Reset
A, B MAC Operands
RES MAC Result
Multiplier Up Accumulate With Register After Multiplication VHDL Coding

Example
--
-- Multiplier Up Accumulate with Register After Multiplication
--
library IEEE;
entity multipliers_7a is
port (clk, reset: in std_logic;
A, B: in std_logic_vector(p_width-1 downto 0);
end multipliers_7a;
architecture beh of multipliers_7a is

signal mult, accum: std_logic_vector(p_width*2-1 downto 0);

begin
process (clk)
begin
if (reset = ’1’) then
accum <= (others => ’0’);
mult <= (others => ’0’);
else
accum <= accum + mult;
mult <= A * B;
end if;
end if;
end process;
RES <= accum;
end beh;
Multiplier Up Accumulate With Register After Multiplication Verilog Coding
Example
//
// Multiplier Up Accumulate with Register After Multiplication
//
module v_multipliers_7a (clk, reset, A, B, RES);
input clk, reset;
input [7:0] A;
input [7:0] B;
output [15:0] RES;
reg [15:0] mult, accum;

begin
if (reset)
mult <= 16’b0000000000000000;
else
mult <= A * B;
end

begin
if (reset)
accum <= 16’b0000000000000000;
else
end
assign RES = accum;
endmodule

Multiplier Up/Down Accumulate With Register After Multiplication

Diagram
Multiplier Up/Down Accumulate With Register After Multiplication

Pin Descriptions
IO Pins Description
reset Synchronous Reset
add_sub AddSub Selector
A, B MAC Operands
RES MAC Result
Multiplier Up/Down Accumulate With Register After Multiplication VHDL

Coding Example
--
-- Multiplier Up/Down Accumulate with Register
-- After Multiplication
--
library IEEE;
entity multipliers_7b is
port (clk, reset, add_sub: in std_logic;
A, B: in std_logic_vector(p_width-1 downto 0);
end multipliers_7b;
architecture beh of multipliers_7b is

signal mult, accum: std_logic_vector(p_width*2-1 downto 0);
begin
process (clk)
begin
if (reset = ’1’) then
accum <= (others => ’0’);
mult <= (others => ’0’);
else

if (add_sub = ’1’) then

else
accum <= accum - mult;
end if;
mult <= A * B;
end if;
end if;
end process;
RES <= accum;
end beh;
Multiplier Up/Down Accumulate With Register After Multiplication Verilog
Coding Example
//
// Multiplier Up/Down Accumulate with Register
// After Multiplication
//
module v_multipliers_7b (clk, reset, add_sub, A, B, RES);
input clk, reset, add_sub;

input [7:0] A;
input [7:0] B;
output [15:0] RES;
reg [15:0] mult, accum;

begin
if (reset)
mult <= 16’b0000000000000000;
else
mult <= A * B;
end

begin
if (reset)
accum <= 16’b0000000000000000;
else
if (add_sub)
else
accum <= accum - mult;
end
assign RES = accum;
endmodule

Dividers HDL Coding Techniques

This section discusses Dividers HDL Coding Techniques, and includes:
• About Dividers
• Dividers Log File
• Dividers Related Constraints
• Dividers Coding Examples
About Dividers
Dividers are supported only when the divisor is a constant and is a power of 2. In that
case, the operator is implemented as a shifter. Otherwise, XST issues an error message.
Dividers Log File

When you implement a divider with a constant with the power of 2, XST does not issue
any message during the Macro Recognition step. If the divider does not correspond to
the case supported by XST, then XST issues the following error message:
...
ERROR:Xst:719 - file1.vhd (Line 172).
Operator is not supported yet : ’DIVIDE’
...
Dividers Related Constraints

None
Dividers Coding Examples

Division by Constant 2 Divider Diagram
Division by Constant 2 Divider Pin Descriptions

IO Pins Description
DI Division Operands
DO Division Result

Division by Constant 2 Divider VHDL Coding Example

--
-- Division By Constant 2
--
library ieee;
entity divider_1 is
DO : out unsigned(7 downto 0));
end divider_1;
architecture archi of divider_1 is

begin
DO <= DI / 2;
end archi;
Division by Constant 2 Divider Verilog Coding Example

//
// Division By Constant 2
//
module v_divider_1 (DI, DO);

input [7:0] DI;
output [7:0] DO;
assign DO = DI / 2;
endmodule

Resource Sharing HDL Coding Techniques

This section discusses Resource Sharing HDL Coding Techniques, and includes:
• About Resource Sharing
• Resource Sharing Log File
• Resource Sharing Related Constraints
• Resource Sharing Coding Examples
About Resource Sharing

The goal of resource sharing (also known as folding) is to minimize the number of
operators and the subsequent logic in the synthesized design. This optimization is based
on the principle that two similar arithmetic resources may be implemented as one single
arithmetic operator if they are never used at the same time. XST performs both resource
sharing and, if required, reduces the number of multiplexers.
XST supports resource sharing for:
• Adders
• Subtractors
• Multipliers
If the optimization goal is speed, disabling resource sharing may give better results. To
improve clock frequency, Xilinx® recommends deactivating resource sharing at the
Advanced HDL Synthesis step.
Resource Sharing Log File

The XST log file reports the type and size of recognized arithmetic blocks and
multiplexers during the Macro Recognition step.
Resource Sharing Log File Example

...
Synthesizing Unit <addsub>.
Related source file is resource_sharing_1.vhd.
Found 8-bit addsub for signal <res>.
Found 8 1-bit 2-to-1 multiplexers.
Summary:
inferred 1 Adder/Subtracter(s).
Unit <addsub> synthesized.
==============================
Macro Statistics
# Multiplexers : 1
2-to-1 multiplexer : 1
8-bit addsub : 1
==============================
...
===================================================================
===================================================================
INFO:Xst - HDL ADVISOR - Resource sharing has identified that some

arithmetic operations in this design can share the same physical resources
for reduced device utilization. For improved clock frequency you may
try to disable resource sharing.
...

Resource Sharing Related Constraints

Resource Sharing (RESOURCE_SHARING)
Resource Sharing Coding Examples

For the following VHDL and Verilog examples, XST gives the following solution.
Resource Sharing Diagram
Resource Sharing Pin Descriptions

IO Pins Description
A, B, C Operands
OPER Operation Selector
RES Data Output
Resource Sharing VHDL Coding Example

--
-- Resource Sharing
--
library ieee;
entity resource_sharing_1 is
port(A,B,C : in std_logic_vector(7 downto 0);
OPER : in std_logic;
end resource_sharing_1;
architecture archi of resource_sharing_1 is

begin
RES <= A + B when OPER=’0’ else A - C;
end archi;

Resource Sharing Verilog Coding Example

//
// Resource Sharing
//
module v_resource_sharing_1 (A, B, C, OPER, RES);

input [7:0] A, B, C;
input OPER;
output [7:0] RES;
wire [7:0] RES;
assign RES = !OPER ? A + B : A - C;
endmodule

RAMs and ROMs HDL Coding Techniques

This section discusses RAMs and ROMs HDL Coding Techniques, and includes:
• About RAMs and ROMs
• RAMs and ROMs Log File
• RAMs and ROMs Related Constraints
• RAMs and ROMs Coding Examples
• Initializing RAM Coding Examples
• Initializing RAM From an External File Coding Examples
About RAMs and ROMs

This section discusses About RAMs and ROMs, and includes:
• Automatic RAM Recognition
• RAMs and ROMs with Negative Addresses
• Types of Inferred RAM
• Block and Distributed RAM
• Unsupported Block RAM Features
• Speed-Oriented Implementation
• Additional XST Capabilities
• Automatic BRAM Resource Control
• Small RAMs and ROMs
• Available BRAM Resources
Automatic RAM Recognition

If you do not want to instantiate RAM primitives to keep your Hardware Description
Language (HDL) code architecture independent, use XST automatic RAM recognition.
XST can infer distributed as well as block RAM. It covers the following characteristics,
offered by these RAM types:
• Synchronous write
• Write enable
• RAM enable
• Asynchronous or synchronous read
• Reset of the data output latches
• Data output reset
• Single, dual, or multiple-port read
• Single-port and dual-port write
• Parity bits
• Block Ram with Byte-Wide Write Enable
• Simple dual-port BRAM
RAMs and ROMs with Negative Addresses

XST does not support RAMs and ROMs with negative addresses.

Types of Inferred RAM

The type of Inferred RAM depends on its description.
• RAM descriptions with an asynchronous read generate a distributed RAM macro.
• RAM descriptions with a synchronous read generate a block RAM macro. In some
cases, a block RAM macro can actually be implemented with distributed RAM. The
decision on the actual RAM implementation is done by the macro generator.
Block and Distributed RAM

If a given template can be implemented using Block and Distributed RAM, XST
implements BLOCK ones. Use the RAM Style (RAM_STYLE) constraint to control RAM
implementation and select a desirable RAM type.
Unsupported Block RAM Features

The following block RAM features are not supported:
• Parity bits
• Different aspect ratios on each port
• Simple dual-port distributed RAMs
• Quad-port distributed RAMs
Speed-Oriented Implementation
XST uses speed-oriented implementation to implement RAMs on BRAM resources. This
gives good results for speed, but may require more BRAM resources than area-oriented
implementation. XST does not support area-oriented BRAM implementation. Xilinx®
recommends the CORE Generator™ software for area-oriented implementation.
XST FPGA Optimization
Additional XST Capabilities

XST can:
• Implement Finite State Machine (FSM) components.
Finite State Machine (FSM) HDL Coding Techniques.
• Map general logic onto block RAMs
Mapping Logic Onto Block RAM
Automatic BRAM Resource Control

XST automatically controls BRAM resources on the target device. BRAM Utilization
Ratio (BRAM_UTILIZATION_RATIO) allows you to specify the number of BRAM
blocks that XST must not exceed during synthesis.
Small RAMs and ROMs

Use RAM Style (RAM_STYLE) and ROM Style (ROM_STYLE) to force implementation
of small RAMs and ROMs on BRAM resources.

To achieve better design speed, XST implements small RAMs and ROMs using
distributed resources. RAMs and ROMs are considered small if their sizes follow the
rules shown in the following table.
Devices Size (bits) * Width (bits)
Virtex®-4 <= 512
Virtex-5 <= 512
Available BRAM Resources

XST calculates the available BRAM resources for inference using the following formula:
Total_Number_of_Available_BRAMs - Number_of_Reserved_BRAMs
where
Total_Number_of_Available_BRAMs is the number of BRAMs specified by the BRAM
Utilization Ratio (BRAM_UTILIZATION_RATIO) constraint. By default it is 100%.
The Number of Reserved_BRAMs encapsulates:
• The number of instantiated BRAMs in the Hardware Description Language (HDL)
code from the UNISIM library
• The number of RAM which were forced to be implemented as BRAMs by the RAM
Style (RAM_STYLE) and ROM Style (ROM_STYLE) constraints
• The number of BRAMs generated using BRAM mapping optimizations
(BRAM_MAP).
Where there are available BRAM resources, XST implements the largest inferred RAMs
and ROMs using BRAM, and the smallest on distributed resources.
If the Number_of_Reserved_BRAMs exceeds available resources, XST implements
them as block RAMs, and all inferred RAMs are implemented on distributed memory.
As soon as this process is completed, XST can automatically pack two small single-port
BRAMs in a single BRAM primitive. This optimization is controlled by Automatic
BRAM Packing (AUTO_BRAM_PACKING). It is disabled by default.
• BRAM Utilization Ratio (BRAM_UTILIZATION_RATIO)
• Automatic BRAM Packing (AUTO_BRAM_PACKING)
RAMs and ROMs Log File

The XST RAMs and ROMs log file reports the following:
• Type and size of recognized RAM
• Complete information on its I/O ports
Steps in RAM Recognition

Step XST Behavior
HDL Synthesis Recognizes the presence of the memory structure in the Hardware
Description Language (HDL) code
Advanced HDL Decides how to implement a specific memory (that is, whether to use
Synthesis Block or Distributed memory resources)

RAMs and ROMs Log File Example

=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <rams_16>.

Related source file is "rams_16.vhd".
Found 64x16-bit dual-port RAM <Mram_RAM> for signal <RAM>.
Found 16-bit register for signal <doa>.
Found 16-bit register for signal <dob>.
Summary:
inferred 1 RAM(s).
inferred32 D-type flip-flop(s).
Unit <rams_16> synthesized.
=========================================================================
Macro Statistics
# RAMs : 1
64x16-bit dual-port RAM : 1
# Registers: 2
16-bit register : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis*
=========================================================================
Synthesizing (advanced) Unit <rams_16>.

INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing
the following register(s): <doa> <dob>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 64-word x 16-bit | |
| mode | write-first | |
| clkA | connected to signal <clka> | rise |
| enA | connected to signal <ena> | high |
| weA | connected to internal <wea> | high |
| addrA | connected to signal <addra> | |
| diA | connected to internal <dia> | |
| doA | connected to signal <doa> | |
-----------------------------------------------------------------------
| optimization | speed | |
=========================================================================
-----------------------------------------------------------------------
-----------------------------------------------------------------------
| Port B |
| clkB | connected to signal <clkb> | rise |
| enB | connected to signal <enb> | high |
| weB | connected to internal <web> | high |
| addrB | connected to signal <addrb> | |
| diB | connected to internal <dib> | |
| doB | connected to signal <dob> | |
-----------------------------------------------------------------------
| optimization | speed | |
=========================================================================
-----------------------------------------------------------------------
Unit <rams_16> synthesized (advanced).
=========================================================================

Macro Statistics
# RAMs : 1
64x16-bit dual-port block RAM : 1
=========================================================================
RAMs and ROMs Related Constraints

• RAM Extraction (RAM_EXTRACT)
• RAM Style (RAM_STYLE)
• ROM Extraction (ROM_EXTRACT)
• ROM Style (ROM_STYLE)
XST accepts LOC and RLOC constraints on inferred RAMs that can be implemented
in a single block RAM primitive. The LOC and RLOC constraints are propagated
to the NGC netlist.
RAMs and ROMs Coding Examples

See Also:
Initializing RAM Coding Examples
Initializing RAM From an External File Coding Examples
About RAMs and ROMs Coding Examples

Block RAM resources in the following devices offer different read/write synchronization
modes:
• Virtex®-4
• Virtex-5
• Spartan®-3
• Spartan-3E
• Spartan-3A
The following coding examples describe a single-port block RAM. You can deduce
descriptions of dual-port block RAMs from these examples. Dual-port block RAMs
can be configured with a different read/write mode on each port. Inference supports
this capability.
This table summarizes support for read/write modes according to the targeted devices
and how XST handles it.

Support For Read/Write Modes

Devices Inferred Modes Behavior
Spartan-3 write-first Macro inference and generation
Spartan-3E read-first Attach adequate WRITE_MODE,
WRITE_MODE_A, WRITE_MODE_B
Spartan-3A no-change constraints to generated block RAMs
Virtex-4 in NCF
Virtex-5
CPLD none RAM inference completely disabled
Single-Port RAM in Read-First Mode Diagram
Single-Port RAM in Read-First Mode Pin Descriptions

IO Pins Description
we Synchronous Write Enable (active-High)
en Clock Enable
addr Read/Write Address
di Data Input
do Data Output
Single-Port RAM in Read-First Mode VHDL Coding Example One

--
-- Read-First Mode
--
library ieee;
entity rams_01 is
we : in std_logic;
en : in std_logic;
addr : in std_logic_vector(5 downto 0);
di : in std_logic_vector(15 downto 0);
do : out std_logic_vector(15 downto 0));
end rams_01;
architecture syn of rams_01 is

type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);
signal RAM: ram_type;
begin
process (clk)

begin
if clk’event and clk = ’1’ then
if en = ’1’ then
if we = ’1’ then
RAM(conv_integer(addr)) <= di;
end if;
do <= RAM(conv_integer(addr)) ;
end if;
end if;
end process;
end syn;
Single-Port RAM in Read-First Mode Verilog Coding Example One

//
// Read-First Mode
//
module v_rams_01 (clk, en, we, addr, di, do);
input clk;
input we;
input en;
input [5:0] addr;
input [15:0] di;
output [15:0] do;
reg [15:0] RAM [63:0];
reg [15:0] do;

begin
if (en)
begin
if (we)
RAM[addr]<=di;
do <= RAM[addr];
end
end
endmodule
Single-Port RAM in Write-First Mode Diagram

Single-Port RAM in Write-First Mode Pin Descriptions

IO Pins Description
en Clock Enable
di Data Input
do Data Output
Single-Port RAM in Write-First Mode VHDL Coding Example One

--
-- Write-First Mode (template 1)
--
library ieee;
entity rams_02a is
we : in std_logic;
en : in std_logic;
end rams_02a;
architecture syn of rams_02a is

type ram_type is array (63 downto 0)
of std_logic_vector (15 downto 0);
signal RAM : ram_type;
begin
process (clk)
begin
do <= di;
else
do <= RAM( conv_integer(addr));
end if;
end if;
end if;
end process;
end syn;

Single-Port RAM in Write-First Mode VHDL Coding Example Two

--
-- Write-First Mode (template 2)
--
library ieee;
entity rams_02b is
we : in std_logic;
en : in std_logic;
end rams_02b;
architecture syn of rams_02b is

signal read_addr: std_logic_vector(5 downto 0);
begin
process (clk)
begin
ram(conv_integer(addr)) <= di;
end if;
read_addr <= addr;
end if;
end if;
end process;
do <= ram(conv_integer(read_addr));
end syn;
Single-Port RAM In Write-First Mode Verilog Coding Example One

//
// Write-First Mode (template 1)
//
module v_rams_02a (clk, we, en, addr, di, do);
input clk;
input we;
input en;
input [5:0] addr;
input [15:0] di;
output [15:0] do;
reg [15:0] RAM [63:0];
reg [15:0] do;

begin
if (en)
begin
if (we)
begin
RAM[addr] <= di;

do <= di;
end
else
do <= RAM[addr];
end
end
endmodule
Single-Port RAM In Write-First Mode Verilog Coding Example Two

//
// Write-First Mode (template 2)
//
module v_rams_02b (clk, we, en, addr, di, do);
input clk;
input we;
input en;
input [5:0] addr;
input [15:0] di;
output [15:0] do;
reg [15:0] RAM [63:0];
reg [5:0] read_addr;

begin
if (en)
begin
if (we)
RAM[addr] <= di;
read_addr <= addr;
end
end
assign do = RAM[read_addr];
endmodule
Single-Port RAM In No-Change Mode Diagram

Single-Port RAM In No-Change Mode Pin Descriptions

IO Pins Description
en Clock Enable
di Data Input
do Data Output
Single-Port RAM In No-Change Mode VHDL Coding Example Two

--
-- No-Change Mode (template 1)
--
library ieee;
entity rams_03 is
we : in std_logic;
en : in std_logic;
end rams_03;

begin
process (clk)
begin
else
do <= RAM( conv_integer(addr));
end if;
end if;
end if;
end process;
end syn;
Single-Port RAM In No-Change Mode Verilog Coding Example Two

//
// No-Change Mode (template 1)
//
module v_rams_03 (clk, we, en, addr, di, do);
input clk;
input we;
input en;
input [5:0] addr;
input [15:0] di;
output [15:0] do;

reg [15:0] RAM [63:0];

reg [15:0] do;

begin
if (en)
begin
if (we)
RAM[addr] <= di;
else
do <= RAM[addr];
end
end
endmodule
The following descriptions are directly mappable onto distributed RAM only.
Single-Port RAM With Asynchronous Read Diagram
Single-Port RAM With Asynchronous Read Pin Descriptions

IO Pins Description
a Read/Write Address
di Data Input
do Data Output
Single-Port RAM With Asynchronous Read VHDL Coding Example

--
-- Single-Port RAM with Asynchronous Read
--
library ieee;
entity rams_04 is
we : in std_logic;
a : in std_logic_vector(5 downto 0);
end rams_04;

begin
process (clk)

begin
if (clk’event and clk = ’1’) then
if (we = ’1’) then
RAM(conv_integer(a)) <= di;
end if;
end if;
end process;
do <= RAM(conv_integer(a));
end syn;
Single-Port RAM With Asynchronous Read Verilog Coding Example

//
// Single-Port RAM with Asynchronous Read
//
module v_rams_04 (clk, we, a, di, do);
input clk;
input we;
input [5:0] a;
input [15:0] di;
output [15:0] do;
reg [15:0] ram [63:0];
always @(posedge clk) begin

if (we)
ram[a] <= di;
end
assign do = ram[a];
endmodule
The following description implements a true synchronous read. A true synchronous
read is the synchronization mechanism in Virtex device block RAMs, where the read
address is registered on the RAM clock edge. Such descriptions are directly mappable
onto block RAM, as shown in the diagram below. The same descriptions can also be
mapped onto Distributed RAM.
Single-Port RAM With Synchronous Read (Read Through)

Diagram

Single-Port RAM With Synchronous Read (Read Through) Pin

Descriptions
IO Pins Description
di Data Input
do Data Output
Single-Port RAM With Synchronous Read (Read Through) VHDL Coding

Example
--
-- Single-Port RAM with Synchronous Read (Read Through)
--
library ieee;
entity rams_07 is
we : in std_logic;
end rams_07;

signal read_a : std_logic_vector(5 downto 0);
begin
process (clk)
begin
end if;
read_a <= a;
end if;
end process;
do <= RAM(conv_integer(read_a));
end syn;
Single-Port RAM With Synchronous Read (Read Through) Verilog Coding

Example
//
// Single-Port RAM with Synchronous Read (Read Through)
//
module v_rams_07 (clk, we, a, di, do);
input clk;
input we;
input [5:0] a;
input [15:0] di;
output [15:0] do;

reg [15:0] ram [63:0];

reg [5:0] read_a;

if (we)
ram[a] <= di;
read_a <= a;
end
assign do = ram[read_a];
endmodule
Single-Port RAM With Enable Diagram
Single-Port RAM With Enable Pin Descriptions

IO Pins Description
en Global Enable
di Data Input
do Data Output
Single-Port RAM With Enable VHDL Coding Example

--
-- Single-Port RAM with Enable
--
library ieee;
entity rams_08 is
en : in std_logic;
we : in std_logic;
end rams_08;

begin
process (clk)

begin
if (en = ’1’) then
end if;
read_a <= a;
end if;
end if;
end process;
do <= RAM(conv_integer(read_a));
end syn;
Single-Port RAM With Enable Verilog Coding Example

//
// Single-Port RAM with Enable
//
module v_rams_08 (clk, en, we, a, di, do);
input clk;
input en;
input we;
input [5:0] a;
input [15:0] di;
output [15:0] do;
reg [15:0] ram [63:0];
reg [5:0] read_a;

if (en)
begin
if (we)
ram[a] <= di;
read_a <= a;
end
end
assign do = ram[read_a];
endmodule
The following diagram shows where the two output ports are used. It is directly
mappable onto Distributed RAM only.
Dual-Port RAM With Asynchronous Read Diagram

Dual-Port RAM With Asynchronous Read Pin Descriptions

IO Pins Description
a Write Address/Primary Read Address
dpra Dual Read Address
di Data Input
spo Primary Output Port
dpo Dual Output Port
Dual-Port RAM With Asynchronous Read VHDL Coding Example

--
-- Dual-Port RAM with Asynchronous Read
--
library ieee;
entity rams_09 is
we : in std_logic;
dpra : in std_logic_vector(5 downto 0);
spo : out std_logic_vector(15 downto 0);
dpo : out std_logic_vector(15 downto 0));
end rams_09;

begin
process (clk)
begin
end if;
end if;
end process;
spo <= RAM(conv_integer(a));

dpo <= RAM(conv_integer(dpra));
end syn;

Dual-Port RAM With Asynchronous Read Verilog Coding Example

//
// Dual-Port RAM with Asynchronous Read
//
module v_rams_09 (clk, we, a, dpra, di, spo, dpo);
input clk;
input we;
input [5:0] a;
input [5:0] dpra;
input [15:0] di;
output [15:0] spo;
output [15:0] dpo;
reg [15:0] ram [63:0];

if (we)
ram[a] <= di;
end
assign spo = ram[a];

assign dpo = ram[dpra];
endmodule
The following descriptions are directly mappable onto block RAM, as shown in the
diagram below. They may also be implemented with Distributed RAM.
Dual-Port RAM With Synchronous Read (Read Through) Diagram
Dual-Port RAM With Synchronous Read (Read Through) Pin

Descriptions
IO Pins Description
a Write Address/Primary Read Address
dpra Dual Read Address
di Data Input
spo Primary Output Port
dpo Dual Output Port

Dual-Port RAM With Synchronous Read (Read Through) VHDL Coding

Example
--
-- Dual-Port RAM with Synchronous Read (Read Through)
--
library ieee;
entity rams_11 is
we : in std_logic;
dpra : in std_logic_vector(5 downto 0);
spo : out std_logic_vector(15 downto 0);
dpo : out std_logic_vector(15 downto 0));
end rams_11;

type ram_type is array (63 downto 0)
of std_logic_vector (15 downto 0);
signal read_dpra : std_logic_vector(5 downto 0);
begin
process (clk)
begin
end if;
read_a <= a;
read_dpra <= dpra;
end if;
end process;
spo <= RAM(conv_integer(read_a));

dpo <= RAM(conv_integer(read_dpra));
end syn;
Dual-Port RAM With Synchronous Read (Read Through) Verilog Coding

Example
//
// Dual-Port RAM with Synchronous Read (Read Through)
//
module v_rams_11 (clk, we, a, dpra, di, spo, dpo);
input clk;
input we;
input [5:0] a;
input [5:0] dpra;

input [15:0] di;

output [15:0] spo;
output [15:0] dpo;
reg [15:0] ram [63:0];
reg [5:0] read_a;
reg [5:0] read_dpra;

if (we)
ram[a] <= di;
read_a <= a;
read_dpra <= dpra;
end
assign spo = ram[read_a];

assign dpo = ram[read_dpra];
endmodule
Dual-Port RAM With Synchronous Read (Read Through) and Two

Clocks Diagram
Dual-Port RAM With Synchronous Read (Read Through) and Two

Clocks Pin Descriptions
IO Pins Description
clk1 Positive-Edge Write/Primary Read Clock
clk2 Positive-Edge Dual Read Clock
add1 Write/Primary Read Address
add2 Dual Read Address
di Data Input
do1 Primary Output Port
do2 Dual Output Port

Dual-Port RAM With Synchronous Read (Read Through) and Two Clocks
VHDL Coding Example
--
-- Dual-Port RAM with Synchronous Read (Read Through)
-- using More than One Clock
--
library ieee;
entity rams_12 is
port (clk1 : in std_logic;
clk2 : in std_logic;
we : in std_logic;
add1 : in std_logic_vector(5 downto 0);
add2 : in std_logic_vector(5 downto 0);
do1 : out std_logic_vector(15 downto 0);
do2 : out std_logic_vector(15 downto 0));
end rams_12;

signal read_add1 : std_logic_vector(5 downto 0);
signal read_add2 : std_logic_vector(5 downto 0);
begin
process (clk1)
begin
if (clk1’event and clk1 = ’1’) then
RAM(conv_integer(add1)) <= di;
end if;
read_add1 <= add1;
end if;
end process;
do1 <= RAM(conv_integer(read_add1));
process (clk2)
begin
if (clk2’event and clk2 = ’1’) then
read_add2 <= add2;
end if;
end process;
do2 <= RAM(conv_integer(read_add2));
end syn;
Dual-Port RAM With Synchronous Read (Read Through) and Two Clocks
//
// Dual-Port RAM with Synchronous Read (Read Through)
// using More than One Clock
//
module v_rams_12 (clk1, clk2, we, add1, add2, di, do1, do2);
input clk1;
input clk2;
input we;
input [5:0] add1;
input [5:0] add2;

input [15:0] di;

output [15:0] do1;
output [15:0] do2;
reg [15:0] ram [63:0];
reg [5:0] read_add1;
reg [5:0] read_add2;
always @(posedge clk1) begin

if (we)
ram[add1] <= di;
read_add1 <= add1;
end
assign do1 = ram[read_add1];
always @(posedge clk2) begin

read_add2 <= add2;
end
assign do2 = ram[read_add2];
endmodule
Dual-Port RAM With One Enable Controlling Both Ports Diagram
Dual-Port RAM With One Enable Controlling Both Ports Pin

Descriptions
IO Pins Description
en Primary Global Enable (active-High)
we Primary Synchronous Write Enable (active-High)
addra Write Address/Primary Read Address
addrb Dual Read Address
di Primary Data Input
doa Primary Output Port
dob Dual Output Port

Dual-Port RAM With One Enable Controlling Both Ports VHDL Coding
Example
--
-- Dual-Port RAM with One Enable Controlling Both Ports
--
library ieee;
entity rams_13 is
en : in std_logic;
we : in std_logic;
addra : in std_logic_vector(5 downto 0);
addrb : in std_logic_vector(5 downto 0);
doa : out std_logic_vector(15 downto 0);
dob : out std_logic_vector(15 downto 0));
end rams_13;

signal read_addra : std_logic_vector(5 downto 0);
signal read_addrb : std_logic_vector(5 downto 0);
begin
process (clk)
begin
RAM(conv_integer(addra)) <= di;
end if;
read_addra <= addra;

read_addrb <= addrb;
end if;
end if;
end process;
doa <= RAM(conv_integer(read_addra));

dob <= RAM(conv_integer(read_addrb));
end syn;
Dual-Port RAM With One Enable Controlling Both Ports Verilog Coding
Example
//
// Dual-Port RAM with One Enable Controlling Both Ports
//
module v_rams_13 (clk, en, we, addra, addrb, di, doa, dob);
input clk;
input en;
input we;
input [5:0] addra;
input [5:0] addrb;
input [15:0] di;
output [15:0] doa;
output [15:0] dob;
reg [15:0] ram [63:0];
reg [5:0] read_addra;

reg [5:0] read_addrb;

if (en)
begin
if (we)
ram[addra] <= di;
end
end
assign doa = ram[read_addra];

assign dob = ram[read_addrb];
endmodule
The following descriptions are directly mappable onto block RAM, as shown in the
diagram.
Dual Port RAM With Enable on Each Port Diagram
Dual Port RAM With Enable on Each Port Pin Descriptions

IO Pins Description
ena Primary Global Enable (active-High)
enb Dual Global Enable (active-High)
wea Primary Synchronous Write Enable
(active-High)
dia Primary Data Input

Dual Port RAM With Enable on Each Port VHDL Coding Example
--
-- Dual-Port RAM with Enable on Each Port
--
library ieee;
entity rams_14 is
ena : in std_logic;
enb : in std_logic;
wea : in std_logic;
dia : in std_logic_vector(15 downto 0);
end rams_14;

signal read_addra : std_logic_vector(5 downto 0);
signal read_addrb : std_logic_vector(5 downto 0);
begin
process (clk)
begin
if (ena = ’1’) then

if (wea = ’1’) then
RAM (conv_integer(addra)) <= dia;
end if;
end if;
if (enb = ’1’) then

end if;
end if;
end process;
doa <= RAM(conv_integer(read_addra));

dob <= RAM(conv_integer(read_addrb));
end syn;
Dual Port RAM With Enable on Each Port Verilog Coding Example
//
// Dual-Port RAM with Enable on Each Port
//
module v_rams_14 (clk,ena,enb,wea,addra,addrb,dia,doa,dob);
input clk;
input ena;
input enb;
input wea;
input [5:0] addra;
input [5:0] addrb;
input [15:0] dia;
output [15:0] doa;
output [15:0] dob;

reg [15:0] ram [63:0];

reg [5:0] read_addra;
reg [5:0] read_addrb;

if (ena)
begin
if (wea)
ram[addra] <= dia;
end
if (enb)
end
assign doa = ram[read_addra];

assign dob = ram[read_addrb];
endmodule
Dual-Port Block RAM With Different Clocks Diagram
Dual-Port Block RAM With Different Clock Pin Descriptions

IO Pins Description
clka Positive-Edge Clock
clkb Positive-Edge Clock
wea Primary Synchronous Write Enable
(active-High)
XST supports dual-port block RAMs with two write ports for VHDL and Verilog.
The concept of dual-write ports implies not only distinct data ports, but the possibility
of distinct write clocks and write enables as well. Distinct write clocks also mean distinct
read clocks, since the dual-port block RAM offers two clocks, one shared by the primary
read and write port, the other shared by the secondary read and write port.

In VHDL, the description of this type of block RAM is based on the usage of shared
variables. The XST VHDL analyzer accepts shared variables, but errors out in the HDL
Synthesis step if a shared variable does not describe a valid RAM macro.
Dual-Port Block RAM With Two Write Ports Diagram
Dual-Port Block RAM With Two Write Ports Pin Descriptions

IO Pins Description
clka, clkb Positive-Edge Clock
ena Primary Global Enable (active-High)
enb Dual Global Enable (active-High)
wea, web Primary Synchronous Write Enable
(active-High)
dib Dual Data Input
Dual-Port Block RAM With Two Write Ports VHDL Coding Example
This is the most general example. It has different clocks, enables, and write enables.
--
-- Dual-Port Block RAM with Two Write Ports
--
library IEEE;
entity rams_16 is
port(clka : in std_logic;
clkb : in std_logic;
ena : in std_logic;
enb : in std_logic;
wea : in std_logic;
web : in std_logic;
dia : in std_logic_vector(15 downto 0);
dib : in std_logic_vector(15 downto 0);
end rams_16;

type ram_type is array (63 downto 0) of std_logic_vector(15 downto 0);

shared variable RAM : ram_type;
begin
process (CLKA)
begin
if CLKA’event and CLKA = ’1’ then
if ENA = ’1’ then
if WEA = ’1’ then
RAM(conv_integer(ADDRA)) := DIA;
end if;
DOA <= RAM(conv_integer(ADDRA));
end if;
end if;
end process;
process (CLKB)
begin
if CLKB’event and CLKB = ’1’ then
if ENB = ’1’ then
if WEB = ’1’ then
RAM(conv_integer(ADDRB)) := DIB;
end if;
DOB <= RAM(conv_integer(ADDRB));
end if;
end if;
end process;
end syn;
Because of the shared variable, the description of the different read/write

synchronizations may be different from coding examples recommended for single-write
RAMs. The order of appearance of the different lines of code is significant.
Dual-Port Block RAM With Two Write Ports Verilog Coding Example
This is the most general example. It has different clocks, enables, and write enables.
//
// Dual-Port Block RAM with Two Write Ports
//
module v_rams_16 (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
input clka,clkb,ena,enb,wea,web;
input [5:0] addra,addrb;
input [15:0] dia,dib;
output [15:0] doa,dob;
reg [15:0] ram [63:0];
reg [15:0] doa,dob;
always @(posedge clka) begin

if (ena)
begin
if (wea)
ram[addra] <= dia;
doa <= ram[addra];
end
end
always @(posedge clkb) begin

if (enb)
begin
if (web)
ram[addrb] <= dib;
dob <= ram[addrb];
end
end
endmodule

Write-First Synchronization Coding Example One

process (CLKA)
begin
DOA <= DIA;
else
end if;
end if;
end process;
Write-First Synchronization Coding Example Two
In this example, the read statement necessarily comes after the write statement.
process (CLKA)
begin
end if;
DOA <= RAM(conv_integer(ADDRA)); -- The read statement must come
-- AFTER the write statement
end if;
end process;
Although they may look the same except for the signal/variable difference, it is also
important to understand the functional difference between this template and the
following well known template which describes a read-first synchronization in a
single-write RAM.
signal RAM : RAMtype;
process (CLKA)
begin
RAM(conv_integer(ADDRA)) <= DIA;
end if;
end if;
end process;
Read-First Synchronization Coding Example
A read-first synchronization is described as follows, where the read statement must
come BEFORE the write statement.
process (CLKA)
begin
DOA <= RAM(conv_integer(ADDRA)); -- The read statement must come
-- BEFORE the write statement
end if;
end if;
end process;

No-Change Synchronization Coding Example

process (CLKA)
begin
else
end if;
end if;
end process;
Single and Dual-Port Block RAM with Byte-Wide Write Enable
XST supports single and dual-port block RAM with Byte-wide Write Enable for VHDL
and Verilog. The RAM can be seen as a collection of equal size columns. During a write
cycle, you separately control writing into each of these columns.
• Multiple Write Statement
There is one separate write access statement, including the description of the related
write enable, for each column.
• Single Write Statement
Allows you to describe only one write access statement. The write enables are
described separately outside the main sequential process. XST currently supports
this method only.
The two methods for describing column-based RAM writes are shown in the following
coding examples.
Multiple Write Statement VHDL Coding Example

type ram_type is array (SIZE-1 downto 0)
of std_logic_vector (2*WIDTH-1 downto 0);
(...)
process(clk)
begin
if posedge(clk) then
if we(1) = ’1’ then
RAM(conv_integer(addr))(2*WIDTH-1 downto WIDTH) <= di(2*WIDTH-1 downto WIDTH);
end if;
RAM(conv_integer(addr))(WIDTH-1 downto 0) <= di(WIDTH-1 downto 0);
end if;
do <= RAM(conv_integer(addr));
end if;
end process;

Multiple Write Statement Verilog Coding Example

reg [2*DI_WIDTH-1:0] RAM [SIZE-1:0];

begin
if (we[1]) then
RAM[addr][2*WIDTH-1:WIDTH] <= di[2*WIDTH-1:WIDTH];
end if;
if (we[0]) then
RAM[addr][WIDTH-1:0] <= di[WIDTH-1:0;
end if;
do <= RAM[addr];
end
Single Write Statement VHDL Coding Example
type ram_type is array (SIZE-1 downto 0)
of std_logic_vector (2*WIDTH-1 downto 0);
signal di0, di1 : std_logic_vector (WIDTH-1 downto 0);
(...)
-- Write enables described outside main sequential process

process(we, di, addr)
begin

di1 <= di(2*WIDTH-1 downto WIDTH);
else
di1 <= RAM(conv_integer(addr))(2*WIDTH-1 downto WIDTH);
end if;

di0 <= di(WIDTH-1 downto 0);
else
di0 <= RAM(conv_integer(addr))(WIDTH-1 downto 0);
end if;
end process;
process(clk)
begin
if posedge(clk) then
RAM(conv_integer(addr)) <= di1 & di0; -- single write access statement
end if;
end if;
end process;
Single Write Statement Verilog Coding Example

reg [DI_WIDTH-1:0] di0, di1;
always @(we or di or addr)

begin
if (we[1])
di1 = di[2*DI_WIDTH-1:1*DI_WIDTH];
else
di1 = RAM[addr][2*DI_WIDTH-1:1*DI_WIDTH];
if (we[0])
di0 = di[DI_WIDTH-1:0];

else
di0 = RAM[addr][DI_WIDTH-1:0];
end

begin
RAM[addr]<={di1,di0};
do <= RAM[addr];
end
To simplify the understanding of byte-wide write enable templates, the following
coding examples use single-port block RAMs. XST supports dual-port Block RAM, as
well as byte-wide write enable.
Read-First Mode: Single-Port BRAM with Byte-wide Write Enable

(2 Bytes) Pin Descriptions
IO Pins Description
we Write Enable
addr Write/Read Address
di Data Input
do RAM Output Port
Read-First Mode: Single-Port BRAM With Byte-Wide Write Enable (2 Bytes)

VHDL Coding Example
--
-- Single-Port BRAM with Byte-wide Write Enable (2 bytes) in Read-First Mode
--
library ieee;
entity rams_24 is
generic (SIZE : integer := 512;
ADDR_WIDTH : integer := 9;
DI_WIDTH : integer := 8);

we : in std_logic_vector(1 downto 0);
addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
di : in std_logic_vector(2*DI_WIDTH-1 downto 0);
do : out std_logic_vector(2*DI_WIDTH-1 downto 0));
end rams_24;
type ram_type is array (SIZE-1 downto 0) of std_logic_vector (2*DI_WIDTH-1 downto 0);

signal di0, di1 : std_logic_vector (DI_WIDTH-1 downto 0);

begin
process(we, di)
begin
di1 <= di(2*DI_WIDTH-1 downto 1*DI_WIDTH);
else
di1 <= RAM(conv_integer(addr))(2*DI_WIDTH-1 downto 1*DI_WIDTH);
end if;


di0 <= di(DI_WIDTH-1 downto 0);
else
di0 <= RAM(conv_integer(addr))(DI_WIDTH-1 downto 0);
end if;
end process;
process(clk)
begin
RAM(conv_integer(addr)) <= di1 & di0;
end if;
end process;
end syn;
Read-First Mode: Single-Port BRAM With Byte-wide Write Enable (2 Bytes)

//
// Single-Port BRAM with Byte-wide Write Enable (2 bytes) in Read-First Mode
//
module v_rams_24 (clk, we, addr, di, do);
parameter SIZE = 512;

parameter ADDR_WIDTH = 9;
parameter DI_WIDTH = 8;
input clk;
input [1:0] we;
input [ADDR_WIDTH-1:0] addr;
input [2*DI_WIDTH-1:0] di;
output [2*DI_WIDTH-1:0] do;
reg [2*DI_WIDTH-1:0] do;
always @(we or di)

begin
if (we[1])
else
if (we[0])
di0 = di[DI_WIDTH-1:0];
else
di0 = RAM[addr][DI_WIDTH-1:0];
end

begin
do <= RAM[addr];
end
endmodule

Write-First Mode: Single-Port BRAM with Byte-wide Write Enable

IO Pins Description
Clk Positive-Edge Clock
We Write Enable
Addr Write/Read Address
Di Data Input
Do RAM Output Port
Write-First Mode: Single-Port BRAM with Byte-Wide Write Enable (2 Bytes)

VHDL Coding Example
--
-- Single-Port BRAM with Byte-wide Write Enable (2 bytes) in Write-First Mode
--
library ieee;
entity rams_25 is

end rams_25;


signal do0, do1 : std_logic_vector (DI_WIDTH-1 downto 0);
begin
process(we, di)
begin
do1 <= di(2*DI_WIDTH-1 downto 1*DI_WIDTH);
else
do1 <= RAM(conv_integer(addr))(2*DI_WIDTH-1 downto 1*DI_WIDTH);
end if;

do0 <= di(DI_WIDTH-1 downto 0);
else
do0 <= RAM(conv_integer(addr))(DI_WIDTH-1 downto 0);
end if;
end process;
process(clk)
begin
do <= do1 & do0;
end if;
end process;

end syn;
Write-First Mode: Single-Port BRAM with Byte-Wide Write Enable (2 Bytes)

//
// Single-Port BRAM with Byte-wide Write Enable
// (2 bytes) in Write-First Mode
//

input clk;
input [1:0] we;

reg [DI_WIDTH-1:0] do0, do1;
always @(we or di)

begin
if (we[1])
begin
do1 = di[2*DI_WIDTH-1:1*DI_WIDTH];
end
else
begin
do1 = RAM[addr][2*DI_WIDTH-1:1*DI_WIDTH];
end
if (we[0])
begin
di0 <= di[DI_WIDTH-1:0];
do0 <= di[DI_WIDTH-1:0];
end
else
begin
di0 <= RAM[addr][DI_WIDTH-1:0];
do0 <= RAM[addr][DI_WIDTH-1:0];
end
end

begin
do <= {do1,do0};
end

endmodule
No-Change Mode: Single-Port BRAM with Byte-Wide Write Enable

IO Pins Description
Clk Positive-Edge Clock
We Write Enable
Addr Write/Read Address
Di Data Input
Do RAM Output Port
XST infers latches for do1 and do0 signals during the basic HDL Synthesis. These
latches are absorbed by BRAM during the Advanced HDL Synthesis step.
No-Change Mode: Single-Port BRAM with Byte-Wide Write Enable (2

Bytes) VHDL Coding Example
--
-- Single-Port BRAM with Byte-wide Write Enable (2 bytes) in No-Change Mode
--
library ieee;
entity rams_26 is

end rams_26;


signal do0, do1 : std_logic_vector (DI_WIDTH-1 downto 0);
begin
process(we, di)
begin
else
do1 <= RAM(conv_integer(addr))(2*DI_WIDTH-1 downto 1*DI_WIDTH);
end if;

else
do0 <= RAM(conv_integer(addr))(DI_WIDTH-1 downto 0);
end if;
end process;
process(clk)

begin
do <= do1 & do0;
end if;
end process;
end syn;
No-Change Mode: Single-Port BRAM with Byte-Wide Write Enable (2

Bytes) in Verilog Coding Example
//
// Single-Port BRAM with Byte-wide Write Enable
// (2 bytes) in No-Change Mode
//

input clk;
input [1:0] we;

reg [DI_WIDTH-1:0] do0, do1;
always @(we or di)

begin
if (we[1])
else
begin
do1 = RAM[addr][2*DI_WIDTH-1:1*DI_WIDTH];
end
if (we[0])
di0 <= di[DI_WIDTH-1:0];
else
begin
di0 <= RAM[addr][DI_WIDTH-1:0];
do0 <= RAM[addr][DI_WIDTH-1:0];
end
end

begin
do <= {do1,do0};
end

endmodule
XST can identify RAM descriptions with two or more read ports that access the RAM
contents at addresses different from the write address. However, there can only be one
write port. XST implements the following descriptions by replicating the RAM contents
for each output port, as shown in the following figure.
Multiple-Port RAM Descriptions Diagram
Multiple-Port RAM Descriptions Pin Descriptions

IO Pins Description
wa Write Address
ra1 Read Address of the First RAM
ra2 Read Address of the Second RAM
di Data Input
do1 First RAM Output Port
do2 Second RAM Output Port
Multiple-Port RAM Descriptions VHDL Coding Example

--
-- Multiple-Port RAM Descriptions
--
library ieee;
entity rams_17 is
we : in std_logic;
wa : in std_logic_vector(5 downto 0);
ra1 : in std_logic_vector(5 downto 0);
ra2 : in std_logic_vector(5 downto 0);
end rams_17;

begin
process (clk)
begin
RAM(conv_integer(wa)) <= di;

end if;
end if;
end process;
do1 <= RAM(conv_integer(ra1));

do2 <= RAM(conv_integer(ra2));
end syn;
Multiple-Port RAM Descriptions Verilog Coding Example

//
// Multiple-Port RAM Descriptions
//
module v_rams_17 (clk, we, wa, ra1, ra2, di, do1, do2);
input clk;
input we;
input [5:0] wa;
input [5:0] ra1;
input [5:0] ra2;
input [15:0] di;
output [15:0] do1;
output [15:0] do2;
reg [15:0] ram [63:0];

begin
if (we)
ram[wa] <= di;
end
assign do1 = ram[ra1];

assign do2 = ram[ra2];
endmodule
Block RAM with Reset on the Data Outputs
XST supports block RAM with reset on the data outputs, as offered with Virtex-4
devices, Virtex-5 devices, and related block RAM resources. Optionally, you can include
a synchronously controlled initialization of the RAM data outputs.
Block RAM with the following synchronization modes can have re-settable data ports.
• Read-First Block RAM with Reset
• Write-First Block RAM with Reset
• No-Change Block RAM with Reset
• Registered ROM with Reset
• Supported Dual-Port Templates
Because XST does not support block RAMs with dual-write in a dual-read block RAM
description, both data outputs may be reset, but the various read-write synchronizations
are allowed for the primary data output only. The dual output may be used in Read-First
Mode only.

Block RAM With Reset Pin Descriptions

IO Pins Description
en Global Enable
we Write Enable (active-High)
rst Reset for data output
di Data Input
do RAM Output Port
Block RAM With Reset VHDL Coding Example

--
-- Block RAM with Reset
--
library ieee;
entity rams_18 is
en : in std_logic;
we : in std_logic;
rst : in std_logic;
end rams_18;

signal ram : ram_type;
begin
process (clk)
begin
if en = ’1’ then -- optional enable
if we = ’1’ then -- write enable

ram(conv_integer(addr)) <= di;
end if;
if rst = ’1’ then -- optional reset

do <= (others => ’0’);
else
do <= ram(conv_integer(addr)) ;
end if;
end if;
end if;
end process;
end syn;

Block RAM With Reset Verilog Coding Example

//
// Block RAM with Reset
//
module v_rams_18 (clk, en, we, rst, addr, di, do);
input clk;
input en;
input we;
input rst;
input [5:0] addr;
input [15:0] di;
output [15:0] do;
reg [15:0] ram [63:0];
reg [15:0] do;

begin
if (en) // optional enable
begin
if (we) // write enable
ram[addr] <= di;
if (rst) // optional reset

do <= 16’h0000;
else
do <= ram[addr];
end
end
endmodule
Block RAM With Optional Output Registers Diagram

Block RAM With Optional Output Registers Pin Descriptions

IO Pins Description
clk1, clk2 Positive-Edge Clock
we Write Enable
en1, en2 Clock Enable (active-High)
addr1 Primary Read Address
addr2 Dual Read Address
di Data Input
res1 Primary Output Port
res2 Dual Output Port
Block RAM With Optional Output Registers VHDL Coding Example

--
-- Block RAM with Optional Output Registers
--
library IEEE;
library IEEE;
entity rams_19 is
port (clk1, clk2 : in std_logic;
we, en1, en2 : in std_logic;
addr1 : in std_logic_vector(5 downto 0);
res1 : out std_logic_vector(15 downto 0);
res2 : out std_logic_vector(15 downto 0));
end rams_19;
architecture beh of rams_19 is

signal ram : ram_type;
signal do1 : std_logic_vector(15 downto 0);
signal do2 : std_logic_vector(15 downto 0);
begin
process (clk1)
begin
if rising_edge(clk1) then
ram(conv_integer(addr1)) <= di;
end if;
do1 <= ram(conv_integer(addr1));
end if;
end process;
process (clk2)
begin
do2 <= ram(conv_integer(addr2));
end if;
end process;
process (clk1)
begin
if en1 = ’1’ then
res1 <= do1;
end if;
end if;
end process;

process (clk2)
begin
if en2 = ’1’ then
res2 <= do2;
end if;
end if;
end process;
end beh;
Block RAM With Optional Output Registers Verilog Coding Example

//
// Block RAM with Optional Output Registers
//
module v_rams_19 (clk1, clk2, we, en1, en2, addr1, addr2, di, res1, res2);
input clk1;
input clk2;
input we, en1, en2;
input [5:0] addr1;
input [5:0] addr2;
input [15:0] di;
output [15:0] res1;
output [15:0] res2;
reg [15:0] res1;
reg [15:0] res2;
reg [15:0] RAM [63:0];
reg [15:0] do1;
reg [15:0] do2;
always @(posedge clk1)

begin
if (we == 1’b1)
RAM[addr1] <= di;
do1 <= RAM[addr1];
end

begin
do2 <= RAM[addr2];
end

begin
if (en1 == 1’b1)
res1 <= do1;
end

begin
if (en2 == 1’b1)
res2 <= do2;
end
endmodule


Block and distributed RAM initial contents can be specified by initialization of the signal
describing the memory array in your HDL code. Do this directly in your HDL code, or
specify a file containing the initialization data.
XST supports RAM initialization in both VHDL and Verilog.
The following coding examples show how to initialize RAM directly in Hardware
Description Language (HDL) code.
RAM Initial Contents VHDL Coding Example (Hexadecimal)

To specify RAM initial contents, initialize the signal describing the memory array in the
VHDL code as shown in the following coding example.
...
type ram_type is array (0 to 63) of std_logic_vector(19 downto 0);
signal RAM : ram_type :=
(
X"0200A", X"00300", X"08101", X"04000", X"08601", X"0233A",
X"00300", X"08602", X"02310", X"0203B", X"08300", X"04002",
X"08201", X"00500", X"04001", X"02500", X"00340", X"00241",
X"04002", X"08300", X"08201", X"00500", X"08101", X"00602",
X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021",
X"00301", X"00102", X"02222", X"04001", X"00342", X"0232B",
X"00900", X"00302", X"00102", X"04002", X"00900", X"08201",
X"02023", X"00303", X"02433", X"00301", X"04004", X"00301",
X"00102", X"02137", X"02036", X"00301", X"00102", X"02237",
X"04004", X"00304", X"04040", X"02500", X"02500", X"02500",
X"0030D", X"02341", X"08201", X"0400D");
...
process (clk)
begin
end if;
ra <= a;
end if;
end process;
...
do <= RAM(conv_integer(ra));
Initializing Block RAM Verilog Coding Example (Hexadecimal)

To specify RAM initial contents, initialize the signal describing the memory array in
your Verilog code using initial statements as shown in the following coding example.
...
reg [19:0] ram [63:0];
initial begin
ram[63] = 20’h0200A; ram[62] = 20’h00300; ram[61] = 20’h08101;
ram[60] = 20’h04000; ram[59] = 20’h08601; ram[58] = 20’h0233A;
...
ram[2] = 20’h02341; ram[1] = 20’h08201; ram[0] = 20’h0400D;
end
...
begin
if (we)
ram[addr] <= di;
do <= ram[addr];
end

RAM Initial Contents VHDL Coding Example (Binary)

RAM initial contents can be specified in hexadecimal, as shown in RAM Initial Contents
VHDL Coding Example (Hexadecimal), or in binary as shown in the following coding
example.
...
type ram_type is array (0 to SIZE-1) of std_logic_vector(15 downto 0);
signal RAM : ram_type :=
(
"0111100100000101",
"0000010110111101",
"1100001101010000",
...
"0000100101110011");
Initializing Block RAM Verilog Coding Example (Binary)
RAM initial contents can be specified in hexadecimal, as shown in Initializing Block RAM
Verilog Coding Example (Hexadecimal), or in binary as shown in the following coding
example.
...
reg [15:0] ram [63:0];
initial begin
ram[63] = 16’b0111100100000101;
ram[62] = 16’b0000010110111101;
ram[61] = 16’b1100001101010000;
...
ram[0] = 16’b0000100101110011;
end
...

Single-Port BRAM Initial Contents VHDL Coding Example

--
-- Initializing Block RAM (Single-Port BRAM)
--
library ieee;
entity rams_20a is
we : in std_logic;
end rams_20a;

signal RAM : ram_type:= (X"0200A", X"00300", X"08101", X"04000", X"08601", X"0233A",
X"00300", X"08602", X"02310", X"0203B", X"08300", X"04002",
X"08201", X"00500", X"04001", X"02500", X"00340", X"00241",
X"04002", X"08300", X"08201", X"00500", X"08101", X"00602",
X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021",
X"00301", X"00102", X"02222", X"04001", X"00342", X"0232B",
X"00900", X"00302", X"00102", X"04002", X"00900", X"08201",
X"02023", X"00303", X"02433", X"00301", X"04004", X"00301",
X"00102", X"02137", X"02036", X"00301", X"00102", X"02237",
X"04004", X"00304", X"04040", X"02500", X"02500", X"02500",
X"0030D", X"02341", X"08201", X"0400D");
begin
process (clk)
begin
end if;
end if;
end process;
end syn;

Single-Port BRAM Initial Contents Verilog Coding Example

//
// Initializing Block RAM (Single-Port BRAM)
//
module v_rams_20a (clk, we, addr, di, do);
input clk;
input we;
input [5:0] addr;
input [19:0] di;
output [19:0] do;
reg [19:0] ram [63:0];
reg [19:0] do;
initial begin
ram[63] = 20’h0200A; ram[62] = 20’h00300; ram[61] = 20’h08101;
ram[60] = 20’h04000; ram[59] = 20’h08601; ram[58] = 20’h0233A;
ram[57] = 20’h00300; ram[56] = 20’h08602; ram[55] = 20’h02310;
ram[54] = 20’h0203B; ram[53] = 20’h08300; ram[52] = 20’h04002;
ram[51] = 20’h08201; ram[50] = 20’h00500; ram[49] = 20’h04001;
ram[48] = 20’h02500; ram[47] = 20’h00340; ram[46] = 20’h00241;
ram[45] = 20’h04002; ram[44] = 20’h08300; ram[43] = 20’h08201;
ram[42] = 20’h00500; ram[41] = 20’h08101; ram[40] = 20’h00602;
ram[39] = 20’h04003; ram[38] = 20’h0241E; ram[37] = 20’h00301;
ram[36] = 20’h00102; ram[35] = 20’h02122; ram[34] = 20’h02021;
ram[33] = 20’h00301; ram[32] = 20’h00102; ram[31] = 20’h02222;
ram[30] = 20’h04001; ram[29] = 20’h00342; ram[28] = 20’h0232B;

ram[27] = 20’h00900; ram[26] = 20’h00302; ram[25] = 20’h00102;
ram[24] = 20’h04002; ram[23] = 20’h00900; ram[22] = 20’h08201;
ram[21] = 20’h02023; ram[20] = 20’h00303; ram[19] = 20’h02433;
ram[18] = 20’h00301; ram[17] = 20’h04004; ram[16] = 20’h00301;
ram[15] = 20’h00102; ram[14] = 20’h02137; ram[13] = 20’h02036;
ram[12] = 20’h00301; ram[11] = 20’h00102; ram[10] = 20’h02237;
ram[9] = 20’h04004; ram[8] = 20’h00304; ram[7] = 20’h04040;
ram[6] = 20’h02500; ram[5] = 20’h02500; ram[4] = 20’h02500;
ram[3] = 20’h0030D; ram[2] = 20’h02341; ram[1] = 20’h08201;
ram[0] = 20’h0400D;
end

begin
if (we)
ram[addr] <= di;
do <= ram[addr];
end
endmodule

Dual-Port RAM Initial Contents VHDL Coding Example

--
-- Initializing Block RAM (Dual-Port BRAM)
--
library ieee;
entity rams_20b is
port (clk1 : in std_logic;
clk2 : in std_logic;
we : in std_logic;
end rams_20b;

signal RAM : ram_type:= (255 downto 100 => X"B8B8", 99 downto 0 => X"8282");
begin
process (clk1)
begin
RAM(conv_integer(addr1)) <= di;
end if;
do1 <= RAM(conv_integer(addr1));
end if;
end process;
process (clk2)
begin
do2 <= RAM(conv_integer(addr2));
end if;
end process;
end syn;

Dual-Port RAM Initial Contents Verilog Coding Example

//
// Initializing Block RAM (Dual-Port BRAM)
//
module v_rams_20b (clk1, clk2, we, addr1, addr2, di, do1, do2);
input clk1, clk2;
input we;
input [7:0] addr1, addr2;
input [15:0] di;
output [15:0] do1, do2;
reg [15:0] ram [255:0];

reg [15:0] do1, do2;
integer index;
initial begin
for (index = 0 ; index <= 99 ; index = index + 1) begin
ram[index] = 16’h8282;
end
for (index= 100 ; index <= 255 ; index = index + 1) begin

ram[index] = 16’hB8B8;
end
end

begin
if (we)
ram[addr1] <= di;
do1 <= ram[addr1];
end

begin
do2 <= ram[addr2];
end
endmodule

The following coding examples show how to initialize RAM from an external file.
To initialize RAM from values contained in an external file, use a read function in the
VHDL code.
VHDL File Type Support.
Set up the initialization file as follows.
• Use each line of the initialization file to represent the initial contents of a given
row in the RAM.
• RAM contents can be represented in binary or hexadecimal.
• There should be as many lines in the file as there are rows in the RAM array.
Following is an example of the contents of a file initializing an 8 x 32-bit RAM with
binary values:
00001111000011110000111100001111
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100
00001111000011110000111100001111

01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100
Initializing Block RAM (External Data File)

RAM initial values may be stored in an external data file that is accessed from within
the HDL code. The data file must be pure binary or hexadecimal content with no
comments or other information.
binary values. For both examples, the data file referenced is called rams_20c.data.
00001111000011110000111100001111
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100
00001111000011110000111100001111
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100

Initializing Block RAM (External Data File) VHDL Coding Example

In the following coding example, the loop that generates the initial value is controlled by
testing that we are in the RAM address range. The following coding examples show
initializing Block RAM from an external data file.
--
-- Initializing Block RAM from external data file
--
library ieee;
use std.textio.all;
entity rams_20c is
we : in std_logic;
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0));
end rams_20c;
architecture syn of rams_20c is
type RamType is array(0 to 63) of bit_vector(31 downto 0);
impure function InitRamFromFile (RamFileName : in string) return RamType is

FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable RAM : RamType;
begin
for I in RamType’range loop
readline (RamFile, RamFileLine);
read (RamFileLine, RAM(I));
end loop;
return RAM;
end function;
signal RAM : RamType := InitRamFromFile("rams_20c.data");
begin
process (clk)
begin
RAM(conv_integer(addr)) <= to_bitvector(din);
end if;
dout <= to_stdlogicvector(RAM(conv_integer(addr)));
end if;
end process;
end syn;
If there are not enough lines in the external data file, XST issues the following message.
ERROR:Xst - raminitfile1.vhd line 40: Line <RamFileLine has not
enough elements for target <RAM<63>>.
Initializing Block RAM (External Data File) Verilog Coding Example

To initialize RAM from values contained in an external file, use a $readmemb or
$readmemh system task in your Verilog code.
XST Behavioral Verilog Language Support


• Arrange each line of the initialization file to represent the initial contents of a given
row in the RAM
• Use $readmemb for binary and $readmemh for hexadecimal representation.
To avoid the possible difference between XST and simulator behavior, Xilinx®
recommends that you use index parameters in these system tasks. See the following
coding example.
$readmemb("rams_20c.data",ram, 0, 7);
Create as many lines in the file as there are rows in the RAM array.
//
// Initializing Block RAM from external data file
//
module v_rams_20c (clk, we, addr, din, dout);

input clk;
input we;
input [5:0] addr;
input [31:0] din;
output [31:0] dout;
reg [31:0] ram [0:63];

reg [31:0] dout;
initial
begin
end

begin
if (we)
ram[addr] <= din;
dout <= ram[addr];
end
endmodule


The following coding examples show how to initialize RAM from an external file.
To initialize RAM from values contained in an external file, use a read function in the
VHDL code.
VHDL File Type Support.
• Use each line of the initialization file to represent the initial contents of a given
row in the RAM.
• There should be as many lines in the file as there are rows in the RAM array.
binary values:
00001111000011110000111100001111
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100
00001111000011110000111100001111
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100
Initializing Block RAM (External Data File)

RAM initial values may be stored in an external data file that is accessed from within
the HDL code. The data file must be pure binary or hexadecimal content with no
comments or other information.
binary values. For both examples, the data file referenced is called rams_20c.data.
00001111000011110000111100001111
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100
00001111000011110000111100001111
01001010001000001100000010000100
00000000001111100000000001000001
11111101010000011100010000100100

Initializing Block RAM (External Data File) VHDL Coding Example

In the following coding example, the loop that generates the initial value is controlled by
testing that we are in the RAM address range. The following coding examples show
initializing Block RAM from an external data file.
--
-- Initializing Block RAM from external data file
--
library ieee;
use std.textio.all;
entity rams_20c is
we : in std_logic;
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0));
end rams_20c;
type RamType is array(0 to 63) of bit_vector(31 downto 0);
impure function InitRamFromFile (RamFileName : in string) return RamType is

FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable RAM : RamType;
begin
for I in RamType’range loop
readline (RamFile, RamFileLine);
read (RamFileLine, RAM(I));
end loop;
return RAM;
end function;
signal RAM : RamType := InitRamFromFile("rams_20c.data");
begin
process (clk)
begin
RAM(conv_integer(addr)) <= to_bitvector(din);
end if;
dout <= to_stdlogicvector(RAM(conv_integer(addr)));
end if;
end process;
end syn;
If there are not enough lines in the external data file, XST issues the following message.
ERROR:Xst - raminitfile1.vhd line 40: Line <RamFileLine has not
enough elements for target <RAM<63>>.
Initializing Block RAM (External Data File) Verilog Coding Example

To initialize RAM from values contained in an external file, use a $readmemb or
$readmemh system task in your Verilog code.


• Arrange each line of the initialization file to represent the initial contents of a given
row in the RAM
• Use $readmemb for binary and $readmemh for hexadecimal representation.
To avoid the possible difference between XST and simulator behavior, Xilinx®
recommends that you use index parameters in these system tasks. See the following
coding example.
Create as many lines in the file as there are rows in the RAM array.
//
// Initializing Block RAM from external data file
//
module v_rams_20c (clk, we, addr, din, dout);

input clk;
input we;
input [5:0] addr;
input [31:0] din;
output [31:0] dout;
reg [31:0] ram [0:63];

reg [31:0] dout;
initial
begin
end

begin
if (we)
ram[addr] <= din;
dout <= ram[addr];
end
endmodule

ROMs Using Block RAM Resources HDL Coding Techniques

This section discusses ROMs Using Block RAM Resources HDL Coding Techniques,
and includes:
• About ROMs Using Block RAM Resources
• ROMs Using Block RAM Resources Log File
• ROMs Using Block RAM Resources Related Constraints
• ROMs Using Block RAM Resources Coding Examples
About ROMs Using Block RAM Resources

XST can use block RAM resources to implement ROMs with synchronous outputs or
address inputs. These ROMs are implemented as single-port or dual-port block RAMs
depending on the HDL description.
XST can infer block ROM across hierarchies if Keep Hierarchy (KEEP_HIERARCHY) is
set to no. In this case, ROM and the data output or address register can be described in
separate hierarchy blocks. This inference is performed during Advanced HDL Synthesis.
Using block RAM resources to implement ROMs is controlled by the ROM Style
(ROM_STYLE) constraint.
For more information about ROM Style (ROM_STYLE), see:
For more information about ROM implementation, see:
ROMs Using Block RAM Resources Log File

Following is a ROMs Using Block RAM Resources Log File Example.
ROMs Using Block RAM Resources Log File Example

=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <rams_21a>.
Related source file is "rams_21a.vhd".
Found 64x20-bit ROM for signal <$varindex0000> created at line 38.
Found 20-bit register for signal <data>.
Summary:
inferred 1 ROM(s).
Unit <rams_21a> synthesized.
=========================================================================
Macro Statistics
# ROMs : 1
64x20-bit ROM : 1
# Registers : 1
20-bit register : 1
=========================================================================
=========================================================================
=========================================================================
INFO:Xst - Unit <rams_21a> : The ROM <Mrom__varindex0000> will be implemented
as a read-only BLOCK RAM, absorbing the register: <data>.
-----------------------------------------------------------------------
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 64-word x 20-bit (6.9%) | |

| clkA | connected to signal <clk> | rise |

| enA | connected to signal <en> | high |
| weA | connected to internal node | high |
| addrA | connected to signal <addr> | |
| diA | connected to internal node | |
| doA | connected to signal <data> | |
-----------------------------------------------------------------------
=========================================================================
Macro Statistics
# RAMs : 1
64x20-bit single-port block RAM : 1
=========================================================================
ROMs Using Block RAM Resources Related Constraints

ROM Style (ROM_STYLE)
ROMs Using Block RAM Resources Coding Examples

ROM With Registered Output Diagram
ROM With Registered Output Pin Descriptions

IO Pins Description
en Synchronous Enable (active-High)
addr Read Address
data Data Output
ROM With Registered Output VHDL Coding Example One

--
-- ROMs Using Block RAM Resources.
-- VHDL code for a ROM with registered output (template 1)
--
library ieee;
entity rams_21a is
en : in std_logic;
data : out std_logic_vector(19 downto 0));
end rams_21a;
type rom_type is array (63 downto 0) of std_logic_vector (19 downto 0);

signal ROM : rom_type:= (X"0200A", X"00300", X"08101", X"04000", X"08601", X"0233A",
X"00300", X"08602", X"02310", X"0203B", X"08300", X"04002",

X"08201", X"00500", X"04001", X"02500", X"00340", X"00241",

X"04002", X"08300", X"08201", X"00500", X"08101", X"00602",
X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021",
X"00301", X"00102", X"02222", X"04001", X"00342", X"0232B",
X"00900", X"00302", X"00102", X"04002", X"00900", X"08201",
X"02023", X"00303", X"02433", X"00301", X"04004", X"00301",
X"00102", X"02137", X"02036", X"00301", X"00102", X"02237",
X"04004", X"00304", X"04040", X"02500", X"02500", X"02500",
X"0030D", X"02341", X"08201", X"0400D");
begin
process (clk)
begin
data <= ROM(conv_integer(addr));
end if;
end if;
end process;
end syn;
ROM With Registered Output VHDL Coding Example Two

--
-- VHDL code for a ROM with registered output (template 2)
--
library ieee;
entity rams_21b is
en : in std_logic;
end rams_21b;

X"00300", X"08602", X"02310", X"0203B", X"08300", X"04002",
X"08201", X"00500", X"04001", X"02500", X"00340", X"00241",
X"04002", X"08300", X"08201", X"00500", X"08101", X"00602",
X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021",
X"00301", X"00102", X"02222", X"04001", X"00342", X"0232B",
X"00900", X"00302", X"00102", X"04002", X"00900", X"08201",
X"02023", X"00303", X"02433", X"00301", X"04004", X"00301",
X"00102", X"02137", X"02036", X"00301", X"00102", X"02237",
X"04004", X"00304", X"04040", X"02500", X"02500", X"02500",
X"0030D", X"02341", X"08201", X"0400D");
signal rdata : std_logic_vector(19 downto 0);

begin
rdata <= ROM(conv_integer(addr));
process (clk)
begin
data <= rdata;
end if;
end if;
end process;
end syn;

ROM With Registered Output Verilog Coding Example One

//
// ROMs Using Block RAM Resources.
// Verilog code for a ROM with registered output (template 1)
//
module v_rams_21a (clk, en, addr, data);
input clk;
input en;
input [5:0] addr;
output reg [19:0] data;

if (en)
case(addr)
6’b000000: data <= 20’h0200A; 6’b100000: data <= 20’h02222;
6’b000001: data <= 20’h00300; 6’b100001: data <= 20’h04001;
6’b000010: data <= 20’h08101; 6’b100010: data <= 20’h00342;
6’b000011: data <= 20’h04000; 6’b100011: data <= 20’h0232B;
6’b000100: data <= 20’h08601; 6’b100100: data <= 20’h00900;
6’b000101: data <= 20’h0233A; 6’b100101: data <= 20’h00302;
6’b000110: data <= 20’h00300; 6’b100110: data <= 20’h00102;
6’b000111: data <= 20’h08602; 6’b100111: data <= 20’h04002;
6’b001000: data <= 20’h02310; 6’b101000: data <= 20’h00900;
6’b001001: data <= 20’h0203B; 6’b101001: data <= 20’h08201;
6’b001010: data <= 20’h08300; 6’b101010: data <= 20’h02023;
6’b001011: data <= 20’h04002; 6’b101011: data <= 20’h00303;
6’b001100: data <= 20’h08201; 6’b101100: data <= 20’h02433;
6’b001101: data <= 20’h00500; 6’b101101: data <= 20’h00301;
6’b001110: data <= 20’h04001; 6’b101110: data <= 20’h04004;
6’b001111: data <= 20’h02500; 6’b101111: data <= 20’h00301;
6’b010000: data <= 20’h00340; 6’b110000: data <= 20’h00102;
6’b010001: data <= 20’h00241; 6’b110001: data <= 20’h02137;
6’b010010: data <= 20’h04002; 6’b110010: data <= 20’h02036;
6’b010011: data <= 20’h08300; 6’b110011: data <= 20’h00301;
6’b010100: data <= 20’h08201; 6’b110100: data <= 20’h00102;
6’b010101: data <= 20’h00500; 6’b110101: data <= 20’h02237;
6’b010110: data <= 20’h08101; 6’b110110: data <= 20’h04004;
6’b010111: data <= 20’h00602; 6’b110111: data <= 20’h00304;
6’b011000: data <= 20’h04003; 6’b111000: data <= 20’h04040;
6’b011001: data <= 20’h0241E; 6’b111001: data <= 20’h02500;
6’b011010: data <= 20’h00301; 6’b111010: data <= 20’h02500;
6’b011011: data <= 20’h00102; 6’b111011: data <= 20’h02500;
6’b011100: data <= 20’h02122; 6’b111100: data <= 20’h0030D;
6’b011101: data <= 20’h02021; 6’b111101: data <= 20’h02341;
6’b011110: data <= 20’h00301; 6’b111110: data <= 20’h08201;
6’b011111: data <= 20’h00102; 6’b111111: data <= 20’h0400D;
endcase
end
endmodule
ROM With Registered Output Verilog Coding Example Two

//
// Verilog code for a ROM with registered output (template 2)
//
module v_rams_21b (clk, en, addr, data);
input clk;
input en;
input [5:0] addr;
reg [19:0] rdata;
always @(addr) begin

case(addr)

6’b000000: rdata <= 20’h0200A; 6’b100000: rdata <= 20’h02222;

6’b000001: rdata <= 20’h00300; 6’b100001: rdata <= 20’h04001;
6’b000010: rdata <= 20’h08101; 6’b100010: rdata <= 20’h00342;
6’b000011: rdata <= 20’h04000; 6’b100011: rdata <= 20’h0232B;
6’b000100: rdata <= 20’h08601; 6’b100100: rdata <= 20’h00900;
6’b000101: rdata <= 20’h0233A; 6’b100101: rdata <= 20’h00302;
6’b000110: rdata <= 20’h00300; 6’b100110: rdata <= 20’h00102;
6’b000111: rdata <= 20’h08602; 6’b100111: rdata <= 20’h04002;
6’b001000: rdata <= 20’h02310; 6’b101000: rdata <= 20’h00900;
6’b001001: rdata <= 20’h0203B; 6’b101001: rdata <= 20’h08201;
6’b001010: rdata <= 20’h08300; 6’b101010: rdata <= 20’h02023;
6’b001011: rdata <= 20’h04002; 6’b101011: rdata <= 20’h00303;
6’b001100: rdata <= 20’h08201; 6’b101100: rdata <= 20’h02433;
6’b001101: rdata <= 20’h00500; 6’b101101: rdata <= 20’h00301;
6’b001110: rdata <= 20’h04001; 6’b101110: rdata <= 20’h04004;
6’b001111: rdata <= 20’h02500; 6’b101111: rdata <= 20’h00301;
6’b010000: rdata <= 20’h00340; 6’b110000: rdata <= 20’h00102;
6’b010001: rdata <= 20’h00241; 6’b110001: rdata <= 20’h02137;
6’b010010: rdata <= 20’h04002; 6’b110010: rdata <= 20’h02036;
6’b010011: rdata <= 20’h08300; 6’b110011: rdata <= 20’h00301;
6’b010100: rdata <= 20’h08201; 6’b110100: rdata <= 20’h00102;
6’b010101: rdata <= 20’h00500; 6’b110101: rdata <= 20’h02237;
6’b010110: rdata <= 20’h08101; 6’b110110: rdata <= 20’h04004;
6’b010111: rdata <= 20’h00602; 6’b110111: rdata <= 20’h00304;
6’b011000: rdata <= 20’h04003; 6’b111000: rdata <= 20’h04040;
6’b011001: rdata <= 20’h0241E; 6’b111001: rdata <= 20’h02500;
6’b011010: rdata <= 20’h00301; 6’b111010: rdata <= 20’h02500;
6’b011011: rdata <= 20’h00102; 6’b111011: rdata <= 20’h02500;
6’b011100: rdata <= 20’h02122; 6’b111100: rdata <= 20’h0030D;
6’b011101: rdata <= 20’h02021; 6’b111101: rdata <= 20’h02341;
6’b011110: rdata <= 20’h00301; 6’b111110: rdata <= 20’h08201;
6’b011111: rdata <= 20’h00102; 6’b111111: rdata <= 20’h0400D;
endcase
end

if (en)
data <= rdata;
end
endmodule
ROM With Registered Address Diagram
ROM With Registered Address Pin Descriptions

IO Pins Description
en Synchronous Enable (active-High)
addr Read Address
data Data Output

ROM With Registered Address VHDL Coding Example

--
-- VHDL code for a ROM with registered address
--
library ieee;
entity rams_21c is
en : in std_logic;
end rams_21c;

X"00300", X"08602", X"02310", X"0203B", X"08300", X"04002",
X"08201", X"00500", X"04001", X"02500", X"00340", X"00241",
X"04002", X"08300", X"08201", X"00500", X"08101", X"00602",
X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021",
X"00301", X"00102", X"02222", X"04001", X"00342", X"0232B",
X"00900", X"00302", X"00102", X"04002", X"00900", X"08201",
X"02023", X"00303", X"02433", X"00301", X"04004", X"00301",
X"00102", X"02137", X"02036", X"00301", X"00102", X"02237",
X"04004", X"00304", X"04040", X"02500", X"02500", X"02500",
X"0030D", X"02341", X"08201", X"0400D");
signal raddr : std_logic_vector(5 downto 0);

begin
process (clk)
begin
raddr <= addr;
end if;
end if;
end process;
data <= ROM(conv_integer(raddr));
end syn;

ROM With Registered Address Verilog Coding Example

//
// Verilog code for a ROM with registered address
//
module v_rams_21c (clk, en, addr, data);
input clk;
input en;
input [5:0] addr;
reg [5:0] raddr;

if (en)
raddr <= addr;
end
always @(raddr) begin

case(raddr)
6’b000000: data <= 20’h0200A; 6’b100000: data <= 20’h02222;
6’b000001: data <= 20’h00300; 6’b100001: data <= 20’h04001;
6’b000010: data <= 20’h08101; 6’b100010: data <= 20’h00342;
6’b000011: data <= 20’h04000; 6’b100011: data <= 20’h0232B;
6’b000100: data <= 20’h08601; 6’b100100: data <= 20’h00900;
6’b000101: data <= 20’h0233A; 6’b100101: data <= 20’h00302;
6’b000110: data <= 20’h00300; 6’b100110: data <= 20’h00102;
6’b000111: data <= 20’h08602; 6’b100111: data <= 20’h04002;
6’b001000: data <= 20’h02310; 6’b101000: data <= 20’h00900;
6’b001001: data <= 20’h0203B; 6’b101001: data <= 20’h08201;
6’b001010: data <= 20’h08300; 6’b101010: data <= 20’h02023;
6’b001011: data <= 20’h04002; 6’b101011: data <= 20’h00303;
6’b001100: data <= 20’h08201; 6’b101100: data <= 20’h02433;
6’b001101: data <= 20’h00500; 6’b101101: data <= 20’h00301;
6’b001110: data <= 20’h04001; 6’b101110: data <= 20’h04004;
6’b001111: data <= 20’h02500; 6’b101111: data <= 20’h00301;
6’b010000: data <= 20’h00340; 6’b110000: data <= 20’h00102;
6’b010001: data <= 20’h00241; 6’b110001: data <= 20’h02137;
6’b010010: data <= 20’h04002; 6’b110010: data <= 20’h02036;
6’b010011: data <= 20’h08300; 6’b110011: data <= 20’h00301;
6’b010100: data <= 20’h08201; 6’b110100: data <= 20’h00102;
6’b010101: data <= 20’h00500; 6’b110101: data <= 20’h02237;
6’b010110: data <= 20’h08101; 6’b110110: data <= 20’h04004;
6’b010111: data <= 20’h00602; 6’b110111: data <= 20’h00304;
6’b011000: data <= 20’h04003; 6’b111000: data <= 20’h04040;
6’b011001: data <= 20’h0241E; 6’b111001: data <= 20’h02500;
6’b011010: data <= 20’h00301; 6’b111010: data <= 20’h02500;
6’b011011: data <= 20’h00102; 6’b111011: data <= 20’h02500;
6’b011100: data <= 20’h02122; 6’b111100: data <= 20’h0030D;
6’b011101: data <= 20’h02021; 6’b111101: data <= 20’h02341;
6’b011110: data <= 20’h00301; 6’b111110: data <= 20’h08201;
6’b011111: data <= 20’h00102; 6’b111111: data <= 20’h0400D;
endcase
end
endmodule

Pipelined Distributed RAM HDL Coding Techniques

This section discusses Pipelined Distributed RAM HDL Coding Techniques, and
includes:
• About Pipelined Distributed RAM
• Pipelined Distributed RAM Log File
• Pipelined Distributed RAM Related Constraints
• Pipelined Distributed RAM Coding Examples
About Pipelined Distributed RAM

In order to increase the speed of designs, XST can infer pipelined distributed RAM.
By interspersing registers between the stages of distributed RAM, pipelining can
significantly increase the overall frequency of your design. The effect of pipelining
is similar to Flip-Flop Retiming.
To insert pipeline stages:
1. Describe the necessary registers in your Hardware Description Language (HDL)
code
2. Place them after any distributed RAM
3. Set RAM Style (RAM_STYLE) to:
pipe_distributed
In order to reach the maximum distributed RAM speed, XST uses the maximum number
of available registers when:
• It detects valid registers for pipelining, and
• RAM_STYLE is set to:
pipe_distributed
In order to obtain the best frequency, XST automatically calculates the maximum
number of registers for each RAM.
During the Advanced HDL Synthesis step, the XST HDL Advisor advises you to specify
the optimum number of register stages if:
• You have not specified sufficient register stages, and
• RAM_STYLE is coded directly on a signal
XST implements the unused stages as shift registers if:
• The number of registers placed after the multiplier exceeds the maximum required,
and
• Shift register extraction is activated
XST cannot pipeline RAM if registers contain asynchronous set/reset signals. XST can
pipeline RAM if registers contain synchronous reset signals.
Pipelined Distributed RAM Log File

Following is a Pipelined Distributed RAM Log File Example.

Pipelined Distributed RAM Log File Example

====================================================================
* HDL Synthesis *
====================================================================
Synthesizing Unit <rams_22>.
Related source file is "rams_22.vhd".
Found 64x4-bit single-port RAM for signal <RAM>.
Found 4-bit register for signal <do>.
Summary:
inferred 1 RAM(s).
Unit <rams_22> synthesized.
=========================================================================
Macro Statistics
# RAMs : 1
64x4-bit single-port RAM : 1
# Registers : 1
4-bit register : 1
=========================================================================
====================================================================
====================================================================
INFO:Xst - Unit <rams_22> : The RAM <Mram_RAM> will be implemented as a
distributed RAM, absorbing the following register(s): <do>.
-------------------------------------------------------------
| clock | connected to signal <clk> | rise |
| write enable | connected to signal <we> | high |
| address | connected to signal <addr> | |
| data in | connected to signal <di> | |
| data out | connected to internal node | |
| ram_style | distributed | |
-------------------------------------------------------------
Synthesizing (advanced) Unit <rams_22>.

Found pipelined ram on signal <_varindex0000>:
- 1 pipeline level(s) found in a register on signal <_varindex0000>.
Pushing register(s) into the ram macro.
INFO:Xst:2390 - HDL ADVISOR - You can improve the performance of

the ram Mram_RAM by adding 1 register level(s) on output signal _varindex0000.
Unit <rams_22> synthesized (advanced).
=========================================================================
Macro Statistics
# RAMs : 1
64x4-bit registered single-port distributed RAM : 1
=========================================================================
Pipelined Distributed RAM Related Constraints


Pipelined Distributed RAM Coding Examples

Pipelined Distributed RAM Diagram
Pipelined Distributed RAM Pin Descriptions

IO Pins Description
di Data Input
do Data Output
Pipelined Distributed RAM VHDL Coding Example

--
-- Pipeline distributed RAMs
--
library ieee;
entity rams_22 is
we : in std_logic;
end rams_22;

signal pipe_reg: std_logic_vector(3 downto 0);
attribute ram_style: string;

attribute ram_style of RAM: signal is "pipe_distributed";
begin
process (clk)
begin
else
pipe_reg <= RAM( conv_integer(addr));

end if;
do <= pipe_reg;
end if;
end process;
end syn;
Pipelined Distributed RAM Verilog Coding Example

//
// Pipeline distributed RAMs
//
input clk;
input we;
input [8:0] addr;
input [3:0] di;
output [3:0] do;
(*ram_style="pipe_distributed"*)
reg [3:0] RAM [511:0];
reg [3:0] do;
reg [3:0] pipe_reg;

begin
if (we)
RAM[addr] <= di;
else
pipe_reg <= RAM[addr];
do <= pipe_reg;
end
endmodule

FSM HDL Coding Techniques

This section discusses Finite State Machine (FSM) HDL Coding Techniques, and includes:
• About FSM Components
• Describing an FSM Component
• State Encoding Techniques
• RAM-Based FSM Synthesis
• Safe FSM Implementation
• FSM Log File
• FSM Related Constraints
• FSM Coding Examples
About FSM Components

The Xilinx Synthesis Technology (XST) software:
• Includes a large set of templates to describe Finite State Machine (FSM) components
• Can apply several state encoding techniques to obtain better performance or less area
• Can re-encode your initial encoding
• Can handle only synchronous state machines
To disable FSM extraction, use Automatic FSM Extraction (FSM_EXTRACT).
Describing an FSM Component

There are many ways to describe a Finite State Machine (FSM) component. A traditional
FSM representation incorporates Mealy and Moore machines, as shown in the following
diagram. XST supports both models.
FSM Representation Incorporating Mealy and Moore Machines

Diagram
Describing FSM Components with Process and Always

For HDL, process (VHDL) and always blocks (Verilog) are the best ways to describe
FSM components. Xilinx® uses process to refer to both VHDL processes and Verilog
always blocks.

You may have several processes (1, 2 or 3) in your description, depending upon how you
consider and decompose the different parts of the preceding model. Following is an
example of the Moore Machine with Asynchronous Reset, RESET.
• 4 states
– s1
– s2
– s3
– s4
• 5 transitions
• 1 input
x1com
• 1 output
outp
The above model is represented by the following bubble diagram.
Bubble Diagram
State Registers
For XST to successfully identify a Finite State Machine (FSM), descriptions of the state
register should include either:
• A power-up state
The power-up state must use proper VHDL or Verilog signal initialization.
• An operational reset
The operational reset can be asynchronous or synchronous.
For coding examples on how to write Asynchronous and Synchronous initialization
signals, see:
In VHDL, the type of a state register can be a different type, such as:
• integer
• bit_vector
• std_logic_vector
But it is common and convenient to define an enumerated type containing all possible
state values and to declare your state register with that type.

In Verilog, the type of state register can be an integer or a set of defined parameters. In
the following Verilog examples the state assignments could have been made as follows:
parameter [3:0]
s1 = 4’b0001,
s2 = 4’b0010,
s3 = 4’b0100,
s4 = 4’b1000;
reg [3:0] state;
These parameters can be modified to represent different state encoding schemes.
Next State Equations

Next state equations can be described directly in the sequential process or in a distinct
combinatorial process. The simplest coding example is based on a case statement. If
using a separate combinatorial process, its sensitivity list should contain the state signal
and all FSM inputs.
Unreachable States
XST can detect unreachable states in an FSM. It lists them in the log file in the HDL
Synthesis step.
Outputs and Inputs

Non-registered outputs are described either in the combinatorial process or in concurrent
assignments. Registered outputs must be assigned within the sequential process.
Registered inputs are described using internal signals, which are assigned in the
sequential process.
State Encoding Techniques

XST supports the following state encoding techniques:
• Auto State Encoding
• One-Hot State Encoding
• Gray State Encoding
• Compact State Encoding
• Johnson State Encoding
• Sequential State Encoding
• Speed1 State Encoding
• User State Encoding
Auto State Encoding

In Auto State Encoding, XST tries to select the best suited encoding algorithm for each
Finite State Machine (FSM).

One-Hot State Encoding

One-Hot State Encoding:
• Is the default encoding scheme.
• Associates one code bit and one flip-flop to each state. At a given clock cycle during
operation, one and only one bit of the state variable is asserted. Only two bits toggle
during a transition between two states.
• Is appropriate with most FPGA targets where a large number of flip-flops are
available.
• Is a good alternative when trying to optimize speed or to reduce power dissipation.
Gray State Encoding

Gray State Encoding:
• Guarantees that only one bit switches between two consecutive states.
• Is appropriate for controllers exhibiting long paths without branching.
• Minimizes hazards and glitches.
• Gives good results when implementing the state register with T flip-flops.
Compact State Encoding

Compact State Encoding:
• Minimizes the number of bits in the state variables and flip-flops.
• Is based on hypercube immersion.
• Is appropriate when trying to optimize area.
Johnson State Encoding

Like Gray State Encoding, Johnson State Encoding shows benefits with state machines
containing long paths with no branching.
Sequential State Encoding

Sequential State Encoding:
• Identifies long paths and applies successive radix two codes to the states on these
paths.
• Minimizes next state equations.
Speed1 State Encoding

Speed1 State Encoding is oriented for speed optimization. The number of bits for a state
register depends on the particular FSM, but generally it is greater than the number
of FSM states.
User State Encoding

In User State Encoding, XST uses the original encoding specified in the HDL file. For
example, if you use enumerated types for a state register, use Enumerated Encoding
(ENUM_ENCODING) to assign a specific binary value to each state.

RAM-Based FSM Synthesis

Large Finite State Machine (FSM) components can be made more compact and faster by
implementing them in the block RAM resources provided in Virtex® devices and later
technologies. FSM Style (FSM_STYLE) directs XST to use block RAM resources for FSMs.
Values for FSM Style (FSM_STYLE) are:
• lut (default)
XST maps the FSM using LUTs.
• bram
XST maps the FSM onto block RAM.
Invoke FSM Style (FSM_STYLE) as follows:
Select LUT or Block RAM as instructed in the HDL Options topics of the ISE Design
Suite Help.
• Command line
Use the -fsm_style command line option.
• Hardware Description Language (HDL) code
Use FSM Style (FSM_STYLE)
If it cannot implement a state machine on block RAM, XST:
• Issues a warning in the Advanced HDL Synthesis step of the log file.
• Automatically implements the state machine using LUTs.
For example, if FSM has an asynchronous reset, it cannot be implemented using block
RAM. In this case XST informs you:
...
===============================================================
===============================================================
WARNING:Xst - Unable to fit FSM <FSM_0> in BRAM (reset is

asynchronous).
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <current_state>
with one-hot encoding.
...
Safe FSM Implementation

XST can add logic to a Finite State Machine (FSM) implementation that will let a state
machine recover from an invalid state. If during its execution, a state machine enters an
invalid state, the logic added by XST brings it back to a known state, called a recovery
state. This is known as Safe Implementation mode.
To activate Safe FSM implementation:
• In ISE® Design Suite, select Safe Implementation as instructed in the HDL Options
topic of ISE Design Suite Help, or
• Apply Safe Implementation (SAFE_IMPLEMENTATION) to the hierarchical block
or signal that represents the state register.
By default, XST automatically selects a reset state as the recovery state. If the
FSM does not have an initialization signal, XST selects a power-up state as the
recovery state. To manually define the recovery state, apply Safe Recovery State
(SAFE_RECOVERY_STATE).

FSM Log File

The XST log file reports the full information of recognized Finite State Machine (FSM)
components during the Macro Recognition step. If you allow XST to choose the best
encoding algorithm for your FSMs, it reports the algorithm it chose for each FSM. As
soon as encoding is selected, XST reports the original and final FSM encoding. If the
target is an FPGA device, XST reports this encoding at the HDL Synthesis step. If the
target is a CPLD device, then XST reports this encoding at the Low Level Optimization
step.
FSM Log File Example

...
Synthesizing Unit <fsm_1>.
Related source file is "/state_machines_1.vhd".
Found finite state machine <FSM_0> for signal <state>.
------------------------------------------------------
| States | 4 |
| Transitions | 5 |
| Inputs | 1 |
| Outputs | 4 |
| Clock | clk (rising_edge) |
| Reset | reset (positive) |
| Reset type | asynchronous |
| Reset State | s1 |
| Power Up State | s1 |
| Encoding | automatic |
| Implementation | LUT |
------------------------------------------------------
Found 1-bit register for signal <outp>.
Summary:
inferred 1 Finite State Machine(s).
Unit <fsm_1> synthesized.
========================================================
Macro Statistics
# Registers : 1
1-bit register : 1
========================================================
========================================================
========================================================
Advanced Registered AddSub inference ...

Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <state/FSM_0> on signal <state[1:2]>
with gray encoding.
-------------------
State | Encoding
-------------------
s1 | 00
s2 | 01
s3 | 11
s4 | 10

-------------------
=======================================================
Macro Statistics
# FSMs : 1
=======================================================
FSM Related Constraints

• Automatic FSM Extraction (FSM_EXTRACT)
• FSM Style (FSM_STYLE)
• FSM Encoding Algorithm (FSM_ENCODING)
• Safe Implementation (SAFE_IMPLEMENTATION)
• Safe Recovery State (SAFE_RECOVERY_STATE)
FSM Coding Examples

FSM With One Process Pin Descriptions

IO Pins Description
reset Asynchronous Reset (active-High)
x1 FSM Input
outp FSM Output
FSM With One Process VHDL Coding Example
--
-- State Machine with a single process.
--
library IEEE;
entity fsm_1 is
port ( clk, reset, x1 : IN std_logic;
outp : OUT std_logic);
end entity;
architecture beh1 of fsm_1 is

type state_type is (s1,s2,s3,s4);
signal state: state_type ;
begin
process (clk,reset)
begin
if (reset =’1’) then
state <=s1;
outp<=’1’;
elsif (clk=’1’ and clk’event) then

case state is
when s1 => if x1=’1’ then
state <= s2;
outp <= ’1’;
else
state <= s3;
outp <= ’0’;
end if;
when s2 => state <= s4; outp <= ’0’;
end case;
end if;
end process;
end beh1;
FSM With Single Always Block Verilog Coding Example
//
// State Machine with a single always block.
//
module v_fsm_1 (clk, reset, x1, outp);

input clk, reset, x1;
output outp;
reg outp;
reg [1:0] state;
parameter s1 = 2’b00; parameter s2 = 2’b01;

initial begin
state = 2’b00;
end
always@(posedge clk or posedge reset)

begin
if (reset)
begin
state <= s1; outp <= 1’b1;
end
else
begin
case (state)
s1: begin
if (x1==1’b1)
begin
state <= s2;
outp <= 1’b1;
end
else
begin
state <= s3;
outp <= 1’b0;
end
end
s2: begin

end
s3: begin
end
s4: begin
end
endcase
end
end
endmodule
FSM With Two Processes
To eliminate a register from the outputs, remove all assignments outp <=… from
the Clock synchronization section. This can be done by introducing two processes as
shown below.
FSM With Two Processes Diagram
FSM With Two Processes Pin Descriptions

IO Pins Description
x1 FSM Input
outp FSM Output
FSM With Two Processes VHDL Coding Example

--
-- State Machine with two processes.
--
library IEEE;
entity fsm_2 is
end entity;

signal state: state_type ;
begin

process1: process (clk,reset)

begin
if (reset =’1’) then state <=s1;
elsif (clk=’1’ and clk’Event) then
case state is
state <= s2;
else
state <= s3;
end if;
when s2 => state <= s4;
end case;
end if;
end process process1;
process2 : process (state)

begin
case state is
when s1 => outp <= ’1’;
when s2 => outp <= ’1’;
when s3 => outp <= ’0’;
when s4 => outp <= ’0’;
end case;
end beh1;
FSM With Two Always Blocks Verilog Coding Example
//
// State Machine with two always blocks.
//

output outp;
reg outp;
reg [1:0] state;

initial begin
state = 2’b00;
end
always @(posedge clk or posedge reset)

begin
if (reset)
state <= s1;
else
begin
case (state)
s1: if (x1==1’b1)
state <= s2;
else
state <= s3;

s2: state <= s4;

s3: state <= s4;
s4: state <= s1;
endcase
end
end
always @(state)
begin
case (state)
s1: outp = 1’b1;
s2: outp = 1’b1;
s3: outp = 1’b0;
s4: outp = 1’b0;
endcase
end
endmodule
You can also separate the NEXT State function from the state register.
FSM With Three Processes Diagram
FSM With Three Processes Pin Descriptions

IO Pins Description
x1 FSM Input
outp FSM Output
FSM With Three Processes VHDL Coding Example

--
-- State Machine with three processes.
--
library IEEE;
entity fsm_3 is
end entity;

signal state, next_state: state_type ;

begin
process1: process (clk,reset)

begin
if (reset =’1’) then
state <=s1;
elsif (clk=’1’ and clk’Event) then
state <= next_state;
end if;
process2 : process (state, x1)

begin
case state is
next_state <= s2;
else
next_state <= s3;
end if;
when s2 => next_state <= s4;
end case;
process3 : process (state)

begin
case state is
when s1 => outp <= ’1’;
when s2 => outp <= ’1’;
when s3 => outp <= ’0’;
when s4 => outp <= ’0’;
end case;
end beh1;

FSM With Three Always Blocks Verilog Coding Example

//
// State Machine with three always blocks.
//

output outp;
reg outp;
reg [1:0] state;
reg [1:0] next_state;

initial begin
state = 2’b00;
end
always @(posedge clk or posedge reset)

begin
if (reset) state <= s1;
else state <= next_state;
end
always @(state or x1)

begin
case (state)
s1: if (x1==1’b1)
next_state = s2;
else
next_state = s3;
s2: next_state = s4;
endcase
end
always @(state)
begin
case (state)
s1: outp = 1’b1;
s2: outp = 1’b1;
s3: outp = 1’b0;
s4: outp = 1’b0;
endcase
end
endmodule

Black Boxes HDL Coding Techniques

This section discusses Black Boxes HDL Coding Techniques, and includes:
• About Black Boxes
• Black Box Log File
• Black Box Related Constraints
• Black Box Coding Examples
About Black Boxes

Your design may contain Electronic Data Interchange Format (EDIF) or NGC files
generated by:
• Synthesis tools
• Schematic text editors
• Any other design entry mechanism
These modules must be instantiated in your code in order to be connected to the rest of
your design. To do so in XST, use Black Box instantiation in the VHDL or Verilog code.
The netlist is propagated to the final top-level netlist without being processed by XST.
XST enables you to attach specific constraints to these Black Box instantiations, which
are passed to the NGC file.
In addition, you may have a design block for which you have an Register Transfer Level
(RTL) model, as well as your own implementation of this block in the form of an EDIF
netlist. The RTL model is valid for simulation purposes only. Use BoxType (BOX_TYPE)
to direct XST to skip synthesis of this RTL code and create a Black Box. The EDIF netlist
is linked to the synthesized design during NGDBuild.
Once you make a design a Black Box, each instance of that design is a Black Box. While
you can attach constraints to the instance, XST ignores any constraint attached to the
original design.
• XST General Constraints
• Constraints Guide
Black Box Log File

Since XST recognizes Black Boxes before macro inference, the Black Box log file differs
from the log files generated for other macros.
Black Box Log File Example

...
Analyzing Entity <black_b> (Architecture <archi>).
WARNING:Xst:766 - black_box_1.vhd (Line 15).

Generating a Black Box for component <my_block>.
Entity <black_b> analyzed. Unit <black_b> generated
....
Black Box Related Constraints

BoxType (BOX_TYPE)
BoxType was introduced for device primitive instantiation in XST. Before using
BoxType, see:

Device Primitive Support
Black Box Coding Examples

Black Box VHDL Coding Example

--
-- Black Box
--
library ieee;
entity black_box_1 is
port(DI_1, DI_2 : in std_logic;
DOUT : out std_logic);
end black_box_1;
architecture archi of black_box_1 is
component my_block
port (I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
begin
inst: my_block port map (I1=>DI_1,I2=>DI_2,O=>DOUT);
end archi;
Black Box Verilog Coding Example
//
// Black Box
//
module v_my_block (in1, in2, dout);

input in1, in2;
output dout;
endmodule
module v_black_box_1 (DI_1, DI_2, DOUT);

input DI_1, DI_2;
output DOUT;
v_my_block inst (
.in1(DI_1),
.in2(DI_2),
.dout(DOUT));
endmodule

For more information on component instantiation, see your VHDL and Verilog language
reference manuals.

Chapter 4

This chapter discusses XST FPGA Optimization, and includes:
• FPGA Synthesis and Optimization
• FPGA Specific Synthesis Options
• Macro Generation
• DSP48 Block Resources
• Mapping Logic Onto Block RAM
• Flip-Flop Retiming
• Partitions
• Speed Optimization Under Area Constraint
• FPGA Optimization Report
• Implementation Constraints
• FPGA Device Primitive Support
• Cores Processing
• Specifying INIT and RLOC
• Using PCI™ Flow With XST
FPGA Synthesis and Optimization

XST performs the following steps during FPGA synthesis and optimization:
• Mapping and optimization on an entity by entity or module by module basis
• Global optimization on the complete design
The output is an NGC file.

Chapter 4: XST FPGA Optimization
FPGA Specific Synthesis Options

XST supports the following options to fine-tune FPGA synthesis to meet user constraints:
• Extract BUFGCE (BUFGCE)
• Cores Search Directories (-sd)
• Decoder Extraction (DECODER_EXTRACT)
• Global Optimization Goal (-glob_opt)
• Keep Hierarchy (KEEP_HIERARCHY)
• Logical Shifter Extraction (SHIFT_EXTRACT)
• Map Logic on BRAM (BRAM_MAP)
• Max Fanout (MAX_FANOUT)
• Move First Stage (MOVE_FIRST_STAGE)
• Move Last Stage (MOVE_LAST_STAGE)
• Number of Global Clock Buffers (-bufg)
• Optimize Instantiated Primitives (OPTIMIZE_PRIMITIVES)
• Priority Encoder Extraction (PRIORITY_EXTRACT)
• Signal Encoding (SIGNAL_ENCODING)
• Slice Packing (-slice_packing)
• Use Carry Chain (USE_CARRY_CHAIN)
• Write Timing Constraints (-write_timing_constraints)
• XOR Collapsing (XOR_COLLAPSE)
XST FPGA Constraints (Non-Timing)
Macro Generation
The FPGA Device Macro Generator module provides the XST HDL Flow with a catalog
of functions. These functions are identified by the inference engine from the Hardware
Description Language (HDL) description. Their characteristics are handed to the Macro
Generator for optimal implementation.
The set of inferred functions ranges in complexity from simple arithmetic operators
(such as adders, accumulators, counters and multiplexers), to more complex building
blocks (such as multipliers, shift registers and memories).
Inferred functions are optimized to deliver the highest levels of performance and
efficiency for the selected Virtex® architecture or Spartan® architecture, and then
integrated into the rest of the design. In addition, the generated functions are optimized
through their borders depending on the design context.
This section categorizes, by function, all available macros and briefly describes
technology resources used in the building and optimization phase.

Macro Generation can be controlled through attributes. These attributes are listed in
each subsection.
XST uses dedicated carry chain logic to implement many macros. In some situations
carry chain logic may result in less than ideal optimization. Use Carry Chain
(USE_CARRY_CHAIN) deactivates this feature.
Arithmetic Functions in Macro Generation

For Arithmetic Functions, XST provides the following elements:
• Adders, Subtractors and Adder/Subtractors
• Cascadable Binary Counters
• Accumulators
• Incrementers, Decrementers and Incrementer/Decrementers
• Signed and Unsigned Multipliers
XST uses fast carry logic (MUXCY) to provide fast arithmetic carry capability for
high-speed arithmetic functions. The sum logic formed from two XOR gates is
implemented using LUTs and the dedicated carry-XORs (XORCY). In addition, XST
benefits from a dedicated carry-ANDs (MULTAND) resource for high-speed multiplier
implementation.
Loadable Functions in Macro Generation

For Loadable functions XST provides the following elements:
• Loadable Up, Down and Up/Down Binary Counters
• Loadable Up, Down and Up/Down Accumulators
XST can provide synchronously loadable, cascadable binary counters and accumulators
inferred in the HDL flow. Fast carry logic is used to cascade the different stages of
the macros. Synchronous loading and count functions are packed in the same LUT
primitive for optimal implementation.
For Up/Down counters and accumulators, XST uses dedicated carry-ANDs to improve
performance.
Multiplexers in Macro Generation

For multiplexers, the Macro Generator provides the following two architectures:
• MUXFx based multiplexers
• Dedicated Carry-MUXs based multiplexers
For Virtex®-4 devices, XST can implement multiplexers using the primitives shown in
the following table.
Multiplexer CLB Primitive
16:1 single CLB MUXF7
32:1 across two CLBs MUXF8

To better control the implementation of the inferred multiplexer, XST offers a way
to select the generation of either the MUXF5/MUXF6 or Dedicated Carry-MUXs
architectures. The attribute MUX_STYLE (Mux Style) specifies that an inferred
multiplexer be implemented on a MUXFx based architecture if the value is MUXF, or a
Dedicated Carry-MUXs based architecture if the value is MUXCY.
You can apply this attribute to either a signal that defines the multiplexer or the instance
name of the multiplexer. This attribute can also be global.
The attribute MUX_EXTRACT (Mux Extraction) with, respectively, the value no or force
can be used to disable or force the inference of the multiplexer.
You still may have MUXFx elements in the final netlist even if multiplexer inference is
disabled using the MUX_EXTRACT (Mux Extraction) constraint. These elements come
from the general mapping procedure of Boolean equations.
Priority Encoders in Macro Generation

The if/elsif structure described in Priority Encoders HDL Coding Techniques is
implemented with a 1-of-n priority encoder.
XST uses the MUXCY primitive to chain the conditions of the priority encoder, which
results in its high-speed implementation.
Use Priority Encoder Extraction (PRIORITY_EXTRACT) to enable or disable priority
encoder inference.
XST does not generally infer (and therefore does not generate) a large number of
priority encoders. To enable priority encoders, use Priority Encoder Extraction
(PRIORITY_EXTRACT) with the force option.
Decoders in Macro Generation

A decoder is a demultiplexer whose inputs are all constant with distinct one-hot (or
one-cold) coded values. An n-bit or 1-of-m decoder is mainly characterized by an m-bit
data output and an n-bit selection input, such that:
n**(2-1) < m <= n**2
Once XST has inferred the decoder, the implementation uses the MUXF5 or MUXCY
primitive depending on the size of the decoder.
Use Decoder Extraction (DECODER_EXTRACT) to enable or disable decoder inference.
RAMs in Macro Generation

Two types of RAM are available during inference and generation:
• Distributed RAM
If the RAM is asynchronous READ, Distributed RAM is inferred and generated.
• Block RAM (default)
If the RAM is synchronous READ, block RAM is inferred. In this case, XST can
implement block RAM or distributed RAM.
Primitives Used by XST

This section applies to the following devices:
• Virtex®-4
• Spartan®-3
For these devices, XST uses the primitives shown in the following table.

RAM Clock Edge Primitives

Single-Port Synchronous Distributed Distributed Single-Port RAM with RAM16X1S, RAM16X2S, RAM16X4S,
RAM positive clock edge RAM16X8S, RAM32X1S, RAM32X2S,
RAM32X4S, RAM32X8S, RAM64X1S,
RAM64X2S, RAM128X1S
Single-Port Synchronous Distributed Distributed Single-Port RAM with RAM16X1S_1, RAM32X1S_1,
RAM negative clock edge RAM64X1S_1, RAM128X1S_1
Dual-Port Synchronous Distributed Distributed Dual-Port RAM with RAM16X1D, RAM32X1D, RAM64X1D
RAM positive clock edge
Dual-Port Synchronous Distributed Distributed Dual-Port RAM with RAM16X1D_1, RAM32X1D_1,
RAM negative clock edge RAM64X1D_1
Single-Port Synchronous Block RAM N/A RAMB4_Sn
Dual-Port Synchronous Block RAM N/A RAMB4_Sm_Sn
Controlling Implementation of Inferred RAM

To better control the implementation of the inferred RAM, XST offers a way to control
RAM inference, and to select the generation of distributed RAM or block RAMs (if
possible).
The RAM Style (RAM_STYLE) attribute specifies that an inferred RAM be generated
using:
• Block RAM if the value is block
• Distributed RAM if the value is distributed
Apply the RAM Style (RAM_STYLE) attribute to:
• A signal that defines the RAM, or
• The instance name of the RAM
The RAM Style (RAM_STYLE) attribute can also be global.
If the RAM resources are limited, XST can generate additional RAMs using registers.
To generate additional RAMs using registers, use RAM Extraction (RAM_EXTRACT)
with the value set to no.
ROMs in Macro Generation

This section discusses ROMs in Macro Generation, and includes:
• Inferring ROM When Assigned Contexts are Constants
• Inferring ROM from an Array
• Types of ROM Available During Inference and Generation
• Type of Synchronous ROM Inferred by XST
• Applying RAM Style

Inferring ROM When Assigned Contexts are Constants

A ROM can be inferred when all assigned contexts in a case or if...else statement are
constants. Macro inference considers only ROMs of at least 16 words with no width
restriction. For example, the following Hardware Description Language (HDL) equation
can be implemented with a ROM of 16 words of 4 bits:
data = if address = 0000 then 0010
if address = 0001 then 1100
...
Inferring ROM from an Array

A ROM can also be inferred from an array composed entirely of constants, as shown in
the following coding example.
type ROM_TYPE is array(15 downto 0)of std_logic_vector(3 downto 0);
constant ROM : rom_type := ("0010", "1100", "1011", ..., "0001");
...
data <= ROM(conv_integer(address));
ROM Extraction (ROM_EXTRACT) can be used to disable the inference of ROMs.

• To enable ROM inference, set the value to yes.
• To disable ROM inference, set the value to no.
The default is yes.
Types of ROM Available During Inference and Generation

Two types of ROM are available during inference and generation:
• Distributed ROM
Distributed ROMs are generated by using the optimal tree structure of LUT, MUXF5,
MUXF6, MUXF7 and MUXF8 primitives, which allows compact implementation
of large inferred ROMs.
• Block ROM
Block ROMs are generated by using block RAM resources. When a synchronous
ROM is identified, it can be inferred either as a distributed ROM plus a register, or it
can be inferred using block RAM resources.
Type of Synchronous ROM Inferred by XST

ROM Style (ROM_STYLE) specifies which type of synchronous ROM XST infers as
shown in the following table.
Option XST Behavior
block Infers the ROM using block RAM resources, provided the ROM fits entirely on a single block of
RAM.
distributed Infers a distributed ROM plus register.
auto (default) Determines the most efficient method to use, and infers the ROM accordingly.
Applying RAM Style

You can apply RAM Style (RAM_STYLE) as a VHDL attribute or a Verilog meta
comment to:
• An individual signal
• The entity or module of the ROM

RAM Style (RAM_STYLE) can also be applied globally from:

• ISE® Design Suite in:
Process > Process Properties
• The command line

This section discusses DSP48 Block Resources, and includes:
• Disabling Automatic DSP Resource Management
• Asynchronous Set/Reset Signals
• Interconnected Macros

XST can automatically implement the following macros on a DSP48 block:
• Accumulators
• Multipliers
• Multiply adder/subtractors
• Multiply accumulate (MAC)
XST also supports the registered versions of these macros.
Macro implementation on DSP48 blocks is controlled by Use DSP48 (USE_DSP48) with
a default value of auto.
In auto mode, XST attempts to implement accumulators, multipliers, multiply
adder/subtractors and MACs on DSP48 resources. XST does not implement
adders/subtractors on DSP48 resources in auto mode. To push adder/subtractors into a
DSP48, set Use DSP48 (USE_DSP48) to yes.
XST performs automatic resource control in auto mode for all macros. Use the DSP
Utilization Ratio (DSP_UTILIZATION_RATIO) constraint in this mode to control
available DSP48 resources for the synthesis. By default, XST tries to utilize all available
DSP48 resources as much as possible.
Disabling Automatic DSP Resource Management

If the number of user-specified DSP slices exceeds the number of available DSP resources
on the target FPGA device, XST issues a warning, and uses only available DSP resources
on the chip for synthesis. Disable automatic DSP resource management to see the
number of DSPs that XST can potentially infer for a specific design. To disable automatic
DSP resource management, set value = -1.

Use Keep (KEEP) to shape a macro in a specific way. For example, if your design has a
multiplier with two register levels on each input, place Keep (KEEP) constraints on the
outputs of these registers to exclude the first register stage from the DSP48.

Asynchronous Set/Reset Signals

DSP48 blocks do not support registers with Asynchronous Set/Reset signals. Since such
registers cannot be absorbed by DSP48, this may lead to sub-optimal performance. The
Asynchronous to Synchronous (ASYNC_TO_SYNC) constraint allows you to replace
Asynchronous Set/Reset signals with Synchronous signals throughout the entire design.
This allows absorption of registers by DSP48, thereby improving quality of results.
Replacing Asynchronous Set/Reset signals by Synchronous signals makes the generated
NGC netlist NOT equivalent to the initial RTL description. You must ensure that
the synthesized design satisfies the initial specification. For more information, see
Asynchronous to Synchronous (ASYNC_TO_SYNC).
For more information on individual macro processing, see:
Interconnected Macros
If your design contains several interconnected macros, where each macro can be
implemented on DSP48, XST attempts to interconnect DSP48 blocks using fast
BCIN/BCOUT and PCIN/PCOUT connections. Such situations are typical in filter and
complex multiplier descriptions.
XST can build complex DSP macros and DSP48 chains across the hierarchy when Keep
Hierarchy (KEEP_HIERARCHY) is set to no. This is the default in ISE® Design Suite.


If your design does not fit into the target device, you can place some of the design logic
into unused block RAM:
1. Put the part of the RTL description to be placed into block RAM in a separate
hierarchical block.
2. Attach a BRAM_MAP (Map Logic on BRAM) constraint to the separate hierarchical
block, either directly in Hardware Description Language (HDL) code, or in the XST
Constraint File (XCF).
XST cannot automatically decide which logic can be placed in block RAM.
Logic placed into a separate block must satisfy the following criteria:
• All outputs are registered.
• The block contains only one level of registers, which are output registers.
• All output registers have the same control signals.
• The output registers have a Synchronous Reset signal.
• The block does not contain multisources or tristate buses.
• Keep (KEEP) is not allowed on intermediate signals.
XST attempts to map the logic onto block RAM during the Advanced Synthesis step.
If any of the listed requirements are not satisfied, XST does not map the logic onto
block RAM, and issues a warning. If the logic cannot be placed in a single block RAM
primitive, XST spreads it over several block RAMs.
Mapping Logic Onto Block RAM Log File Example One

...
=============================================================
* HDL Synthesis *
=============================================================
e is "bram_map_1.vhd".
Found 4-bit register for signal <RES>.
Found 4-bit adder for signal <$n0001> created at line 29.
Summary:
Unit <logic_bram_1> synthesized.
=============================================================
=============================================================
...
Entity <logic_bram_1> mapped on BRAM.
...
=============================================================
Macro Statistics
# Block RAMs : 1
256x4-bit single-port block RAM : 1
=============================================================
...

Mapping Logic Onto Block RAM Log File Example Two

...
=============================================================
=============================================================
...
INFO:Xst:1789 - Unable to map block <no_logic_bram> on BRAM.
Output FF <RES> must have a synchronous reset.
8-Bit Adders With Constant in a Single Block Ram Primitive VHDL Coding
Example
--
-- The following example places 8-bit adders with
-- constant in a single block RAM primitive
--
library ieee;
entity logic_bram_1 is
port (clk, rst : in std_logic;
A,B : in unsigned (3 downto 0);
RES : out unsigned (3 downto 0));
attribute bram_map: string;

attribute bram_map of logic_bram_1: entity is "yes";
end logic_bram_1;
architecture beh of logic_bram_1 is

begin
process (clk)
begin
if (rst = ’1’) then
RES <= "0000";
else
RES <= A + B + "0001";
end if;
end if;
end process;
end beh;

8-Bit Adders With Constant in a Single Block Ram Primitive Verilog Coding
Example
//
// The following example places 8-bit adders with
// constant in a single block RAM primitive
//
(* bram_map="yes" *)
module v_logic_bram_1 (clk, rst, A, B, RES);
input clk, rst;

input [3:0] A, B;
output [3:0] RES;
reg [3:0] RES;

begin
if (rst)
RES <= 4’b0000;
else
RES <= A + B + 8’b0001;
end
endmodule

Asynchronous Reset VHDL Coding Example

--
-- In the following example, an asynchronous reset is used and
-- so, the logic is not mapped onto block RAM
--
library ieee;
entity logic_bram_2 is
port (clk, rst : in std_logic;
A,B : in unsigned (3 downto 0);
RES : out unsigned (3 downto 0));
attribute bram_map : string;

attribute bram_map of logic_bram_2 : entity is "yes";
end logic_bram_2;
architecture beh of logic_bram_2 is

begin
process (clk, rst)

begin
if (rst=’1’) then
RES <= "0000";
elsif (clk’event and clk=’1’) then
RES <= A + B + "0001";
end if;
end process;
end beh;
Asynchronous Reset Verilog Coding Example
//
// In the following example, an asynchronous reset is used and
// so, the logic is not mapped onto block RAM
//
(* bram_map="yes" *)
module v_logic_bram_2 (clk, rst, A, B, RES);
input clk, rst;

input [3:0] A, B;
output [3:0] RES;
reg [3:0] RES;
always @(posedge clk or posedge rst)

begin
if (rst)
RES <= 4’b0000;
else
RES <= A + B + 8’b0001;
end
endmodule

Flip-Flop Retiming
This section discusses Flip-Flop Retiming, and includes:
• About Flip-Flop Retiming
• Global Optimization
• Flip-Flop Retiming Messages
• Limitations of Flip-Flop Retiming
• Controlling Flip-Flop Retiming
About Flip-Flop Retiming

Flip-flop retiming consists of moving flip-flops and latches across logic for the purpose
of improving timing, thus increasing clock frequency.
Flip-flop retiming can be either forward or backward:
• Forward retiming moves a set of flip-flops that are the input of a LUT to a single
flip-flop at its output.
• Backward retiming moves a flip-flop that is at the output of a LUT to a set of
flip-flops at its input.
Flip-flop retiming can:
• Significantly increase the number of flip-flops
• Remove some flip-flops
Nevertheless, the behavior of the designs remains the same. Only timing delays are
modified.
Global Optimization
Flip-flop retiming is part of global optimization. It respects the same constraints as
all other optimization techniques. Since retiming is incremental, a flip-flop that is the
result of a retiming can be moved again in the same direction (forward or backward)
if it results in better timing. The only limit for the retiming occurs when the timing
constraints are satisfied, or if no more improvements in timing can be obtained.
Flip-Flop Retiming Messages

For each flip-flop moved, a message is printed specifying:
• The original and new flip-flop names
• Whether it is a forward or backward retiming
Limitations of Flip-Flop Retiming

Flip-flop retiming has the following limitations:
• Flip-flop retiming is not applied to flip-flops that have the IOB=TRUE property.
• Flip-flops are not moved forward if the flip-flop or the output signal has the Keep
(KEEP) property.
• Flip-flops are not moved backward if the input signal has the Keep (KEEP) property.
• Instantiated flip-flops are moved only if the Optimize Instantiated Primitives
constraint or command line option is set to yes.
• Flip-Flops are moved across instantiated primitives only if the Optimize Instantiated
Primitives command line option or constraint is set to yes.
• Flip-flops with both a set and a reset are not moved.

Controlling Flip-Flop Retiming

Use the following constraints to control flip-flop retiming:
Partitions
XST now supports Partitions in place of Incremental Synthesis. Incremental Synthesis is
no longer supported. The incremental_synthesis and resynthesize constraints are no
longer supported. For more information on Partitions, see the ISE® Design Suite Help.
Speed Optimization Under Area Constraint

XST performs timing optimization under the area constraint. This option is named:
• LUT-FF Pairs Utilization Ratio
Virtex®-5 devices
• Slice (LUT-FF Pairs) Utilization Ratio (SLICE_UTILIZATION_RATIO)”
All other FPGA devices
Define in ISE® Design Suite with:
Process > Process Properties > XST Synthesis Options.
By default this constraint is set to 100% of the selected device size.
This constraint has influence at low level synthesis only It does not control inference.
If this constraint is specified, XST makes an area estimation. If the specified constraint
is met, XST continues timing optimization trying not to exceed the constraint. If the
design is larger than requested, XST tries to reduce the area first. If the area constraint
is met, XST begins timing optimization.
Example One (100%)

In the following example the area constraint was specified as 100% and initial estimation
shows that in fact it occupies 102% of the selected device. XST begins optimization and
reaches 95%.
...
================================================================
*
* Low Level Synthesis
*
================================================================
Found area constraint ratio of 100 (+ 5) on block tge,

actual ratio is 102.
Optimizing block <tge> to meet ratio 100 (+ 5) of 1536
slices :
Area constraint is met for block <tge>, final ratio is 95.
================================================================

Example Two (70%)

If the area constraint cannot be met, XST ignores it during timing optimization and runs
low level synthesis to achieve the best frequency. In the following example, the target
area constraint is set to 70%. Since XST was unable to satisfy the target area constraint,
XST issues the following warning:
...
================================================================
*
*
================================================================
Found area constraint ratio of 70 (+ 5) on block fpga_hm,
actual ratio is 64.
Optimizing block <fpga_hm> to meet ratio 70 (+ 5) of 1536
slices :
WARNING:Xst - Area constraint could not be met for block <tge>,
final ratio is 94
...
================================================================
...
Note (+5) stands for the max margin of the area constraint. If the area constraint is
not met, but the difference between the requested area and obtained area during area
optimization is less or equal then 5%, then XST runs timing optimization taking into
account the achieved area, not exceeding it.
Example Three (55%)

In the following example, the area was specified as 55%. XST achieved only 60%. But
taking into account that the difference between requested and achieved area is not more
than 5%, XST considers that the area constraint was met.
...
================================================================
*
*
================================================================
Found area constraint ratio of 55 (+ 5) on block fpga_hm,
actual ratio is 64.
Optimizing block <fpga_hm> to meet ratio 55 (+ 5) of 1536
slices :
Area constraint is met for block <fpga_hm>, final ratio is 60.
================================================================
...
In some situations, it is important to disable automatic resource management. To do so,
specify -1 as the value for SLICE_UTILIZATION_RATIO.
Slice (LUT-FF Pairs) Utilization Ratio (SLICE_UTILIZATION_RATIO) can be attached to
a specific block of a design. You can specify an absolute number of slices (or FF-LUT
pairs) as a percentage of the total number.

FPGA Device Optimization Report Section

This section discusses FPGA Device Optimization Report Section, and includes:
• About FPGA Device Optimization Report Section
• Cell Usage Report
• Timing Report
About FPGA Device Optimization Report Section

During design optimization, XST reports:
• Potential removal of equivalent flip-flops
Two flip-flops (latches) are equivalent when they have the same data and control
pins.
• Register replication
Register replication is used to:
– Improve timing performance
– Satisfy MAX_FANOUT constraints
Use Register Duplication (REGISTER_DUPLICATION) to turn off register
replication.
FPGA Device Optimization Report Section Example

Starting low level synthesis ...
Optimizing unit <down4cnt> ...
Optimizing unit <doc_readwrite> ...
...
Optimizing unit <doc> ...
Building and optimizing final netlist ...
The FF/Latch <doc_readwrite/state_D2> in Unit <doc> is
equivalent to the following 2 FFs/Latches,
which will be removed : <doc_readwrite/state_P2>
<doc_readwrite/state_M2>Register
doc_reset_I_reset_out has been replicated 2 time(s)
Register wr_l has been replicated 2 time(s)
Cell Usage Report

The Cell Usage section of the Final Report gives the count of all the primitives used in
the design. The primitives are classified in the following groups:
• BELS Cell Usage
• Flip-Flops and Latches Cell Usage
• RAMS Cell Usage
• SHIFTERS Cell Usage
• Tristates Cell Usage
• Clock Buffers Cell Usage
• IO Buffers Cell Usage
• LOGICAL Cell Usage
• OTHER Cell Usage

BELS Cell Usage

The BELS group in the Cell Usage section of the Final Report contains all the logical cells
that are basic elements of the targeted FPGA device family, for example:
• LUTs
• MUXCY
• MUXF5
• MUXF6
• MUXF7
• MUXF8
Flip-Flops and Latches Cell Usage

The Flip-Flops and Latches group in the Cell Usage section of the Final Report contains
all the flip-flops and latches that are primitives of the targeted FPGA device family, for
example:
• FDR
• FDRE
• LD
RAMS Cell Usage

The RAMS group in the Cell Usage section of the Final Report contains all the RAMs.
SHIFTERS Cell Usage

The SHIFTERS group in the Cell Usage section of the Final Report contains all the shift
registers that use the Virtex® device primitive:
• TSRL16
• SRL16_1
• SRL16E
• SRL16E_1
• SRLC
Tristates Cell Usage

The Tristates group in the Cell Usage section of the Final Report contains all the tristate
primitives:
BUFT
Clock Buffers Cell Usage

The Clock Buffers group in the Cell Usage section of the Final Report contains all the
clock buffers:
• BUFG
• BUFGP
• BUFGDLL

IO Buffers Cell Usage

The IO Buffers group in the Cell Usage section of the Final Report contains all the
standard I/O buffers (except the clock buffer):
• IBUF
• OBUF
• IOBUF
• OBUFT
• IBUF_GTL ...
LOGICAL Cell Usage

The LOGICAL group in the Cell Usage section of the Final Report contains all the logical
cells primitives that are not basic elements:
• AND2
• OR2 ...
OTHER Cell Usage

The OTHER group in the Cell Usage section of the Final Report contains all the cells that
have not been classified in the previous groups.
Cell Usage Report Example

==================================================
...
Cell Usage :
# BELS : 70
# LUT2 : 34
# LUT3 : 3
# LUT4 : 34
# FlipFlops/Latches : 9
# FDC : 8
# FDP : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 24
# IBUF : 16
# OBUF : 8
==================================================
Where XST estimates the number of slices and gives, for example, the number of
flip-flops, IOBs, and BRAMS. This report closely resembles the report produced by MAP.
Short tables give information about:
• The number of clocks in the design, how each clock is buffered, and how many
loads it has
• The number of asynchronous set/reset signals in the design, how each signal is
buffered, and how many loads it has

Timing Report
This section discusses Timing Report, and includes:
• About Timing Report
• Timing Report Timing Summary Section
• Timing Report Timing Detail Section
• Timing Report Paths and Ports
About Timing Report

At the end of synthesis, XST reports the timing information for the design. The Timing
Report shows the information for all four possible domains of a netlist:
• register to register
• input to register
• register to outpad
• inpad to outpad

Timing Report Example

These timing numbers are only a synthesis estimate. For accurate timing information,
see the TRACE report generated after place-and-route.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLK | BUFGP | 11 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:

----------------------------------------
-------------------------------------+-------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-------------------------------------+-------------------------------+-------+
rstint(MACHINE/current_state_Out01:O)| NONE(sixty/lsbcount/qoutsig_3)| 4 |
RESET | IBUF | 3 |
sixty/msbclr(sixty/msbclr:O) | NONE(sixty/msbcount/qoutsig_3)| 4 |
-------------------------------------+-------------------------------+-------+
Timing Summary:
---------------
Speed Grade: -12
Minimum period: 2.644ns (Maximum Frequency: 378.165MHz)

Minimum input arrival time before clock: 2.148ns
Maximum output required time after clock: 4.803ns
Maximum combinational path delay: 4.473ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock ’CLK’
Clock period: 2.644ns (frequency: 378.165MHz)
Total number of paths / destination ports: 77 / 11
-------------------------------------------------------------------------
Delay: 2.644ns (Levels of Logic = 3)
Source: MACHINE/current_state_FFd3 (FF)
Destination: sixty/msbcount/qoutsig_3 (FF)
Source Clock: CLK rising
Destination Clock: CLK rising
Data Path: MACHINE/current_state_FFd3 to sixty/msbcount/qoutsig_3

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 8 0.272 0.642 MACHINE/current_state_FFd3 (MACHINE/current_state_FFd3)
LUT3:I0->O 3 0.147 0.541 Ker81 (clkenable)
LUT4_D:I1->O 1 0.147 0.451 sixty/msbce (sixty/msbce)
LUT3:I2->O 1 0.147 0.000 sixty/msbcount/qoutsig_3_rstpot (N43)
FDC:D 0.297 sixty/msbcount/qoutsig_3
----------------------------------------
Total 2.644ns (1.010ns logic, 1.634ns route)
(38.2% logic, 61.8% route)

Timing Report Timing Summary Section

The Timing Summary section of the Timing Report summarizes the timing paths for all
four domains:
• The path from any clock to any clock in the design:
• The maximum path from all primary inputs to the sequential elements:
• The maximum path from the sequential elements to all primary outputs:
Maximum output required time before clock: 14.220ns
• The maximum path from inputs to outputs:
Maximum combinational path delay: 10.899ns
If there is no path in the domain, No path found is printed instead of the value.
Timing Report Timing Detail Section

The Timing Detail section of the Timing Report describes the most critical path in detail
for each region:
• Start point of the path
• End point of the path
• Maximum delay of the path
• Slack
The start and end points can be:
• Clock (with the phase: rising/falling), or
• Port
Path from Clock ’sysclk’ rising to Clock ’sysclk’ rising : 7.523ns (Slack: -7.523ns)
The detailed path shows:
• Cell type
• Input and output of this gate
• Fanout at the output
• Gate delay
• Net delay estimate
• Name of the instance.
When entering a hierarchical block, begin scope is printed. When exiting a hierarchical
block, end scope is printed.
The preceding report corresponds to the following schematic.

Timing Report Schematic
Timing Report Paths and Ports

The Timing Report section shows the number of analyzed paths and ports. If XST is
run with timing constraints, it also shows the number of failed paths and ports. The
number of analyzed and failed paths shows how many timing problems there are in
the design. The number of analyzed and failed ports may show how they are spread in
the design. The number of ports in a timing report represent the number of destination
elements for a timing constraint.
For example, if you use the following timing constraints:
TIMESPEC "TSidentifier"=FROM "source_group" TO "dest_group" value
units;
then the number of ports corresponds to the number of elements in the destination
group.
For a given timing constraint, XST may report that the number of failed paths is 100,
but that the number of failed destination ports is only two flip-flops. In that case, it is
sufficient to analyze the design description for these two flip-flops only in order to
detect the changes necessary to meet timing.
Implementation Constraints
XST writes all implementation constraints generated from Hardware Description
Language (HDL) or constraint file attributes (such as LOC) into the output NGC file.
Keep (KEEP) properties are generated during buffer insertion for maximum fanout
control or for optimization.

FPGA Device Primitive Support

This section discusses FPGA Device Primitive Support, and includes:
• About FPGA Device Primitive Support
• Generating Primitives Through Attributes
• Primitives and Black Boxes
• VHDL and Verilog Device Primitives Libraries
• Reporting of Instantiated Device Primitives
• Primitives Related Constraints
• Primitives Coding Examples
• Using the UniMacro Library
About FPGA Device Primitive Support

XST enables you to instantiate device primitives directly in VHDL or Verilog code.
Primitives such as the following can be manually inserted in a Hardware Description
Language (HDL) design through instantiation:
• MUXCY_L
• LUT4_L
• CLKDLL
• RAMB4_S1_S16
• IBUFG_PCI33_5
• NAND3b2
These primitives:
• Are compiled in the UNISIM library
• Are not optimized by XST by default
• Are available in the final NGC file
Use Optimize Instantiated Primitives synthesis to optimize instantiated primitives and
obtain better results. Timing information is available for most of the primitives, allowing
XST to perform efficient timing-driven optimization.
In order to simplify instantiation of complex primitives as RAMs, XST supports an
additional library called UniMacro.
For more information, see the Libraries Guides.

Generating Primitives Through Attributes

Some primitives can be generated through attributes:
• Buffer Type (BUFFER_TYPE)
Can be assigned to the primary input or internal signal to force the use of the
following:
– BUFGDLL
– IBUFG
– BUFR
– BUFGP
The same constraints can be used to disable buffer insertion.
• I/O Standard (IOSTANDARD)
Can be used to assign an I/O standard to an I/O primitive.
For example, the following assigns PCI33_5 I/O standard to the I/O port:
// synthesis attribute IOSTANDARD of in1 is PCI33_5
Primitives and Black Boxes

The primitive support is based on the concept of the black box. For information on the
basics of black box support, see Safe FSM Implementation.
There is a significant difference between black box and primitive support. Assume you
have a design with a submodule called MUXF5. In general, the MUXF5 can be your own
functional block or a Xilinx® device primitive. To avoid confusion about how XST
interprets this module, attach BoxType (BOX_TYPE) to the component declaration of
MUXF5.
If BoxType (BOX_TYPE) is attached to the MUXF5 with a value of:
• primitive, or black_box
XST tries to interpret this module as a Xilinx device primitive and use its parameters,
for instance, in critical path estimation.
• user_black_box
XST processes it as a regular user black box.
If the name of the user black box is the same as that of a Xilinx device primitive, XST
renames it to a unique name and issues a warning. For example, MUX5 could be
renamed to MUX51 as shown in the following log file example.
...
================================================================
================================================================
WARNING:Xst:79 - Model ’muxf5’ has different characteristics in

destination library
WARNING:Xst:80 - Model name has been changed to ’muxf51’
...
If BoxType (BOX_TYPE) is not attached to the MUXF5, XST processes this block as a
user hierarchical block. If the name of the user black box is the same as that of a Xilinx
device primitive, XST renames it to a unique name and issues a warning.

VHDL and Verilog Device Primitives Libraries

XST provides dedicated libraries, both in VHDL and Verilog, simplifying instantiation of
Xilinx® device primitives in your HDL source code These libraries contain the complete
set of Xilinx device primitives declarations with a BoxType (BOX_TYPE) constraint
attached to each component.
Device Libraries
In VHDL, declare library UNISIM with its package vcomponents in your source code:
library unisim;
use unisim.vcomponents.all;
The source code of this package can be found in the following file of the XST installation:
vhdl\src\ unisims\unisims_vcomp.vhd
In Verilog, the UNISIM library is precompiled. XST automatically links it with your
design.
Primitive Instantiation Guidelines

Use UPPERCASE for generic (VHDL) and parameter (Verilog) values when instantiating
primitives. For example the ODDR element has the following component declaration
in the UNISIM library:
component ODDR
generic
(DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT : bit := ’0’;
SRTYPE : string := "SYNC");
port(Q : out std_ulogic;

C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
When you instantiate this primitive in your code, the values of DDR_CLK_EDGE and
SRTYPE generics must be in UPPERCASE. If not, XST issues a warning stating that
unknown values are used.
Some primitives, such as LUT1, enable you to use an INIT during instantiation. The two
ways to pass an INIT to the final netlist are:
• Attach an INIT attribute to the instantiated primitive.
• Pass the INIT with the generics mechanism (VHDL), or the parameters mechanism
(Verilog). Xilinx recommends this method, since it allows you to use the same code
for synthesis and simulation.
Reporting of Instantiated Device Primitives

XST does not issue any message concerning instantiation of instantiated device
primitives during HDL synthesis because the BoxType (BOX_TYPE) attribute with its
value, primitive, is attached to each primitive in the UNISIM library.

XST issues a warning as shown in the log file example below if:
• You instantiate a block (non primitive) in your design
AND
• The block has no contents (no logic description)
OR
• The block has a logic description
AND
• You attach a BoxType (BOX_TYPE) constraint to it with a value of user_black_box.
Log File Example

...
Analyzing Entity <black_b> (Architecture <archi>).
WARNING : (VHDL_0103). c:\jm\des.vhd (Line 23).
Generating a Black Box for component <my_block>.
Entity <black_b> analyzed. Unit <black_b> generated.
...
Primitives Related Constraints

• BoxType (BOX_TYPE)
• The PAR constraints that can be passed from HDL to NGC without processing
Primitives Coding Examples

Passing an INIT Value Via the INIT Constraint VHDL Coding Example
--
-- Passing an INIT value via the INIT constraint.
--
library ieee;
library unisim;
entity primitive_1 is
port(I0,I1 : in std_logic;
O : out std_logic);
end primitive_1;
architecture beh of primitive_1 is
attribute INIT: string;

attribute INIT of inst: label is "1";
begin
inst: LUT2 port map (I0=>I0,I1=>I1,O=>O);
end beh;

Passing an INIT Value Via the INIT Constraint Verilog Coding Example
//
// Passing an INIT value via the INIT constraint.
//
module v_primitive_1 (I0,I1,O);

input I0,I1;
output O;
(* INIT="1" *)
LUT2 inst (.I0(I0), .I1(I1), .O(O));
endmodule
Passing an INIT Value Via the Generics Mechanism VHDL Coding Example
--
-- Passing an INIT value via the generics mechanism.
--
library ieee;
library unisim;
entity primitive_2 is
port(I0,I1 : in std_logic;
O : out std_logic);
end primitive_2;
architecture beh of primitive_2 is

begin
inst: LUT2 generic map (INIT=>"1")

port map (I0=>I0,I1=>I1,O=>O);
end beh;
Passing an INIT Value Via the Parameters Mechanism Verilog Coding
Example
//
// Passing an INIT value via the parameters mechanism.
//

input I0,I1;
output O;
LUT2 #(4’h1) inst (.I0(I0), .I1(I1), .O(O));
endmodule

Passing an INIT Value Via the Defparam Mechanism Verilog Coding

Example
//
// Passing an INIT value via the defparam mechanism.
//

input I0,I1;
output O;
LUT2 inst (.I0(I0), .I1(I1), .O(O));

defparam inst.INIT = 4’h1;
endmodule
Using the UniMacro Library

This section discusses Using the UniMacro Library, and includes:
• About Using the UniMacro Library
• UniMacro Library Device Support
• Using the UniMacro Library in VHDL
• Using the UniMacro Library in Verilog
About Using the UniMacro Library

In order to simplify instantiation of such complex primitives as RAMs, XST supports an
additional library called UniMacro.
For more information, see the Libraries Guides.
UniMacro Library Device Support

The UniMacro library supports the following devices:
• Virtex®-4
• Virtex-5 and newer
Using the UniMacro Library in VHDL

In VHDL, declare the library unimacro with its package vcomponents in your source
code:
library unimacro;
use unimacro.vcomponents.all;
The source code of this package is located in the following file in the XST installation:
vhdl\src\unisims\unisims_vcomp.vhd
Using the UniMacro Library in Verilog

In Verilog, the UniMacro library is precompiled. XST automatically links it with your
design.

Cores Processing
If a design contains cores represented by an Electronic Data Interchange Format (EDIF)
or an NGC file, XST can automatically read them for timing estimation and area
utilization control. Use ISE® Design Suite Process > Process Properties > Synthesis
Options > Read Cores to enable or disable this feature. Using the read_cores option of
the run command from the command line, you can also specify optimize. This enables
cores processing, and allows XST to integrate the core netlist into the overall design. XST
reads cores by default.
If Read Cores is disabled, XST estimates Maximum Combinational Path Delay as 6.639ns
(critical path goes through a simple AND function) and an area of one slice.
If Read Cores is enabled, XST issues the following messages during Low Level Synthesis:
...
============================================================
*
*
============================================================
Launcher: Executing edif2ngd -noa "my_add.edn" "my_add.ngo"

INFO:NgdBuild - Release 6.1i - edif2ngd G.21
INFO:NgdBuild - Copyright (c) 1995-2003 Xilinx, Inc.
All rights reserved.
Writing the design to "my_add.ngo"...
Loading core <my_add> for timing and area information
for instance <inst>.
============================================================
...
Estimation of Maximum Combinational Path Delay is 8.281ns with an area of five slices.
By default, XST reads Electronic Data Interchange Format (EDIF) and NGC cores from
the current (project) directory. If the cores are not in the project directory, specify the
directory in which the cores are located with Cores Search Directories (-sd).

Coding Example
In the following VHDL coding example, the block my_add is an adder, which is
represented as a black box in the design whose netlist was generated by the CORE
Generator™ software.
library ieee;
entity read_cores is
port(
A, B : in std_logic_vector (7 downto 0);
a1, b1 : in std_logic;
SUM : out std_logic_vector (7 downto 0);
res : out std_logic);
end read_cores;
architecture beh of read_cores is

component my_add
port (
S : out std_logic_vector (7 downto 0));
end component;
begin
res <= a1 and b1;
inst: my_add port map (A => A, B => B, S => SUM);
end beh;


Use the UNISIM library to directly instantiate LUT components in your Hardware
Description Language (HDL) code. To specify a function that a particular LUT must
execute, apply an INIT constraint to the instance of the LUT. To place an instantiated
LUT or register in a particular slice of the chip, attach an RLOC constraint to the same
instance.
It is not always convenient to calculate INIT functions and different methods that can be
used to achieve this. Instead, you can describe the function that you want to map onto a
single LUT in your VHDL or Verilog code in a separate block.
Attaching a Map Entity on a Single LUT (LUT_MAP) constraint to this block indicates to
XST that this block must be mapped on a single LUT. XST automatically calculates the
INIT value for the LUT and preserves this LUT during optimization.
XST automatically recognizes the XC_MAP constraint supported by Synopsys.
Passing an INIT Value Via the LUT_MAP Constraint Coding Examples

The following coding examples show how to pass an INIT value using the LUT_MAP
constraint.
In these examples, the top block contains the instantiation of two AND gates, described
in and_one and and_two blocks. XST generates two LUT2s and does not merge them.
Map Entity on a Single LUT (LUT_MAP)

Passing an INIT Value Via the LUT_MAP Constraint VHDL Coding Example
--
-- Mapping on LUTs via LUT_MAP constraint
--
library ieee;
entity and_one is
port (A, B : in std_logic;
REZ : out std_logic);
attribute LUT_MAP: string;

attribute LUT_MAP of and_one: entity is "yes";
end and_one;
architecture beh of and_one is

begin
REZ <= A and B;
end beh;
--------------------------------------------------
library ieee;
entity and_two is
port(A, B : in std_logic;
attribute LUT_MAP: string;

attribute LUT_MAP of and_two: entity is "yes";
end and_two;
architecture beh of and_two is

begin
REZ <= A or B;
end beh;
--------------------------------------------------
library ieee;
entity inits_rlocs_1 is
port(A,B,C : in std_logic;
end inits_rlocs_1;
architecture beh of inits_rlocs_1 is
component and_one
end component;
component and_two
end component;
signal tmp: std_logic;

begin
inst_and_one: and_one port map (A => A, B => B, REZ => tmp);
inst_and_two: and_two port map (A => tmp, B => C, REZ => REZ);
end beh;

Passing an INIT Value Via the LUT_MAP Constraint Verilog Coding Example
//
// Mapping on LUTs via LUT_MAP constraint
//
(* LUT_MAP="yes" *)
module v_and_one (A, B, REZ);
input A, B;
output REZ;
and and_inst(REZ, A, B);
endmodule
// --------------------------------------------------
(* LUT_MAP="yes" *)
module v_and_two (A, B, REZ);
input A, B;
output REZ;
or or_inst(REZ, A, B);
endmodule
// --------------------------------------------------
module v_inits_rlocs_1 (A, B, C, REZ);

input A, B, C;
output REZ;
wire tmp;
v_and_one inst_and_one (A, B, tmp);

v_and_two inst_and_two (tmp, C, REZ);
endmodule
Specifying INIT Value for a Flip-Flop Coding Examples

If a function cannot be mapped on a single LUT, XST issues an error message and
interrupts synthesis. To define an INIT value for a flip-flop or a shift register, described
at RTL level, assign its initial value in the signal declaration stage. This value is not
ignored during synthesis and is propagated to the final netlist as an INIT constraint
attached to the flip-flop or shift register.
In the following coding examples, a 4-bit register is inferred for signal tmp.
An INIT value equal 1011 is attached to the inferred register and propagated to the
final netlist.

Specifying INIT Value for a Flip-Flop VHDL Coding Example

--
-- Specification on an INIT value for a flip-flop,
-- described at RTL level
--
library ieee;
port (CLK : in std_logic;
DI : in std_logic_vector(3 downto 0);
DO : out std_logic_vector(3 downto 0));
end inits_rlocs_2;
architecture beh of inits_rlocs_2 is signal

tmp: std_logic_vector(3 downto 0):="1011";
begin
process (CLK)
begin
tmp <= DI;
end if;
end process;
DO <= tmp;
end beh;
Specifying INIT Value for a Flip-Flop Verilog Coding Example

//
// Specification on an INIT value for a flip-flop,
// described at RTL level
//
module v_inits_rlocs_2 (clk, di, do);

input clk;
input [3:0] di;
output [3:0] do;
reg [3:0] tmp;
initial begin
tmp = 4’b1011;
end

begin
tmp <= di;
end
assign do = tmp;
endmodule

Specifying INIT and RLOC Values for a Flip-Flop Coding Examples

To infer a register and place it in a specific location of a chip, attach an RLOC constraint
to the tmp signal as shown in the following coding examples.
XST propagates it to the final netlist. XST supports this feature is supported for:
• Registers, and
• Inferred block RAM if it can be implemented on a single block RAM primitive
Specifying INIT and RLOC Values for a Flip-Flop VHDL Coding Example
--
-- Specification on an INIT and RLOC values for a flip-flop,
-- described at RTL level
--
library ieee;
port (CLK : in std_logic;
DI : in std_logic_vector(3 downto 0);
DO : out std_logic_vector(3 downto 0));
end inits_rlocs_3;
architecture beh of inits_rlocs_3 is

signal tmp: std_logic_vector(3 downto 0):="1011";
attribute RLOC: string;

attribute RLOC of tmp: signal is "X3Y0 X2Y0 X1Y0 X0Y0";
begin
process (CLK)
begin
tmp <= DI;
end if;
end process;
DO <= tmp;
end beh;

Specifying INIT and RLOC Values for a Flip-Flop Verilog Coding Example
//
// Specification on an INIT and RLOC values for a flip-flop,
// described at RTL level
//
module v_inits_rlocs_3 (clk, di, do);

input clk;
input [3:0] di;
output [3:0] do;
(* RLOC="X3Y0 X2Y0 X1Y0 X0Y0" *)
reg [3:0] tmp;
initial begin
tmp = 4’b1011;
end

begin
tmp <= di;
end
assign do = tmp;
endmodule

Using PCI Flow With XST

This section discusses Using PCI™ Flow With XST, and includes:
• Rules for Using PCI Flow With XST
• Preventing Logic and Flip-Flop Replication
• Disabling Read Cores
Rules for Using PCI Flow With XST

Follow these rules to satisfy placement constraints and meet timing requirements when
using PCI flow with XST.
• For VHDL, ensure that the names in the generated netlist are all in UPPER case.
The default case is lower.
Specify the case in ISE® Design Suite in:
Process > Process Properties > Synthesis Options > Case
• For Verilog, ensure that Case is set to maintain.
The default case is maintain.
Specify the case in ISE Design Suite in:
• Preserve the hierarchy of the design.
Specify the Keep Hierarchy (KEEP_HIERARCHY) setting in ISE Design Suite in:
Process > Process Properties > Synthesis Options > Keep Hierarchy
• Preserve equivalent flip-flops.
XST removes equivalent flip-flops by default.
Specify the Equivalent Register Removal (EQUIVALENT_REGISTER_REMOVAL)
setting in ISE Design Suite in:
Process > Process Properties > Xilinx® Specific Options > Equivalent Register
Removal
Preventing Logic and Flip-Flop Replication

To prevent logic and flip-flop replication caused by a high fanout flip-flop set/reset
signal:
• Set a high maximum fanout value for the entire design in ISE® Design Suite in:
Process > Process Properties > Synthesis Options > Max Fanout, or
• Use Max Fanout (MAX_FANOUT) to set a high maximum fanout value for the
initialization signal connected to the RST port of the PCI™ core.
Example:
max_fanout=2048
Disabling Read Cores

Disabling Read Cores prevents XST from automatically reading PCI™ cores for timing
and area estimation. In reading PCI cores, XST may perform logic optimization that
does not allow the design to meet timing requirements, or which might lead to errors
during MAP. By default, XST reads cores for timing and area estimation. To disable
Read Cores, uncheck it in ISE® Design Suite in:
Process > Process Properties > Synthesis Options > Read Cores

Chapter 5
XST CPLD Optimization

This chapter discusses XST CPLD Optimization, and includes:
• CPLD Synthesis Options
• Implementation Details for Macro Generation
• CPLD Synthesis Log File Analysis
• CPLD Synthesis Constraints
• Improving Results in CPLD Synthesis
CPLD Synthesis Options

This section discusses the XST options related only to CPLD synthesis that can be set
ISE® Design Suite in:
Process > Process Properties
XST generates an NGC file ready for the CPLD fitter.
The general flow of XST for CPLD synthesis is:
1. Hardware Description Language (HDL) synthesis of VHDL or Verilog designs
2. Macro inference
3. Module optimization
4. NGC file generation
CPLD Synthesis Supported Devices

XST supports CPLD synthesis for the following devices:
• CoolRunner™ XPLA3
• CoolRunner-II
• XC9500
• XC9500XL
The synthesis for CoolRunner XPLA3 device families and XC9500XL device families
includes clock enable processing. You can allow or invalidate the clock enable signal.
When invalidated, it is replaced by equivalent logic.
The selection of the macros that use the clock enable (counters, for instance) depends
on the device type. A counter with clock enable is accepted for the CoolRunner XPLA3
device families and XC9500XL device families, but rejected (replaced by equivalent
logic) for XC9500 devices.
Setting CPLD Synthesis Options

Set the following CPLD synthesis options in ISE® Design Suite in:

Chapter 5: XST CPLD Optimization
Process > Process Properties > Synthesis Options

• Macro Preserve (-pld_mp)
• XOR Preserve (-pld_xp)
• Clock Enable (-pld_ce)
• WYSIWYG (-wysiwyg)
• No Reduce (NOREDUCE)
XST CPLD Constraints (Non-Timing)
Implementation Details for Macro Generation

XST processes the following macros:
• Adders
• Subtractors
• Add/sub
• Multipliers
• Comparators
• Multiplexers
• Counters
• Logical shifters
• Registers (flip-flops and latches)
• XORs
The macro generation is decided by the Macro Preserve command line option, which
can take two values:
• yes
Macro generation is allowed.
• no
Macro generation is inhibited.
The general macro generation flow is:
1. Hardware Description Language (HDL) infers macros and submits them to the
low-level synthesizer.
2. Low-level synthesizer accepts or rejects the macros depending on the resources
required for the macro implementations.
An accepted macro is generated by an internal macro generator. A rejected macro is
replaced by equivalent logic generated by the HDL synthesizer. A rejected macro may
be decomposed by the HDL synthesizer into component blocks so that one component
may be a new macro requiring fewer resources than the initial one, and another smaller
macro may be accepted by XST. For instance, a flip-flop macro with clock enable (CE)
cannot be accepted when mapping onto the XC9500. In this case the HDL synthesizer
submits two new macros:
• A flip-flop macro without clock enable signal
• A MUX macro implementing the clock enable function

A generated macro is optimized separately and then merged with surrounded logic
because optimization gives better results for larger components.
CPLD Synthesis Log File Analysis

XST messages related to CPLD synthesis are located after the following message:
Low Level Synthesis

The XST log file contains:

• Tracing of progressive unit optimizations
Optimizing unit unit_name ...
• Information, warnings or fatal messages related to unit optimization:
– When equation shaping is applied (XC9500 devices only):
Collapsing ...
– Removing equivalent flip-flops
Register ff1 equivalent to ff2 has been removed
– User constraints fulfilled by XST:
implementation constraint: constraint_name[=value]: signal_name
• Final results statistics
Final Results
Top Level Output file name : file_name
Output format : ngc
Optimization goal : {area | speed}
Target Technology : {9500 | 9500xl | 9500xv | xpla3 | xbr | cr2s}
Keep Hierarchy : {yes | soft | no}
Macro Preserve : {yes | no}
XOR Preserve : {yes | no}
Design Statistics
NGC Instances: nb_of_instances
I/Os: nb_of_io_ports
Macro Statistics
# FSMs: nb_of_FSMs
# Registers: nb_of_registers
# Tristates: nb_of_tristates
# Comparators: nb_of_comparators
n-bit comparator {equal | not equal | greater| less | greatequal | lessequal}:
nb_of_n_bit_comparators
# Multiplexers: nb_of_multiplexers
n-bit m-to-1 multiplexer :
nb_of_n_bit_m_to_1_multiplexers
# Adders/Subtractors: nb_of_adds_subs
n-bit adder: nb_of_n_bit_adds
n-bit subtractor: nb_of_n_bit_subs
# Multipliers: nb_of_multipliers
# Logic Shifters: nb_of_logic_shifters
# Counters: nb_of_counters
n-bit {up | down | updown} counter: nb_of_n_bit_counters
# XORs: nb_of_xors
Cell Usage :
# BELS: nb_of_bels
# AND...: nb_of_and ...
# OR...: nb_of_or ...
# INV: nb_of_inv
# XOR2: nb_of_xor2
# GND: nb_of_gnd # VCC: nb_of_vcc
# FlipFlops/Latches: nb_of_ff_latch
# FD...: nb_of_fd ...
# LD...: nb_of_ld ...
# Tri-States: nb_of_tristates
# BUFE: nb_of_bufe
# BUFT: nb_of_buft
# IO Buffers: nb_of_iobuffers
# IBUF: nb_of_ibuf
# OBUF: nb_of_obuf
# IOBUF: nb_of_iobuf
# OBUFE: nb_of_obufe
# OBUFT: nb_of_obuft # Others: nb_of_others

CPLD Synthesis Constraints

The constraints (attributes) specified in the Hardware Description Language (HDL)
design or in the constraint files are written by XST into the NGC file as signal properties.
Improving Results in CPLD Synthesis

XST produces optimized netlists for the CPLD fitter, which:
• Fits them in specified devices
• Creates the download programmable files
The CPLD low-level optimization of XST consists of:
• Logic minimization
• Subfunction collapsing
• Logic factorization
• Logic decomposition
Optimization results in an NGC netlist corresponding to Boolean equations. The CPLD
fitter reassembles these equations to fit the best of the macrocell capacities. A special
XST optimization process, known as equation shaping, is applied for XC9500 and
XC9500XL devices when the following options are selected:
• Keep Hierarchy
No
• Optimization Effort
2 or High
• Macro Preserve
No
The equation shaping processing also includes a critical path optimization algorithm.
This algorithm tries to reduce the number of levels of critical paths.
Xilinx® recommends CPLD fitter multilevel optimization because of the special
optimizations done by the fitter:
• D to T flip-flop conversion
• De Morgan Boolean expression selection
Obtaining Better Frequency

The frequency depends on the number of logic levels (logic depth). To reduce the
number of levels, Xilinx® recommends the following options:
• Optimization Effort
Set Optimization Effort to 2 or High.
This value implies the calling of the collapsing algorithm, which tries to reduce the
number of levels without increasing the complexity beyond certain limits.
• Optimization Goal
Set Optimization Goal to Speed.
The priority is the reduction of number of levels.
Obtaining the best frequency depends on the CPLD fitter optimization. Xilinx
recommends running the multi-level optimization of the CPLD fitter with different
values for the -pterms options, beginning with 20 and finishing with 50 with a step of 5.
Statistically the value 30 gives the best results for frequency.

The following tries, in this order, may give successively better results for frequency:
• Obtaining Better Frequency Try 1
The CPU time increases from Try 1 to Try 4.
Obtaining Better Frequency Try 1

Select only optimization effort 2 and speed optimization. The other options have default
values.
• Optimization effort
2 or High
Speed

Flatten the user hierarchy. In this case optimization has a global view of the design,
and the depth reduction may be better.
1/Normal or 2/High
Speed
• Keep Hierarchy
no

Merge the macros with surrounded logic. The design flattening is increased.
1 or Normal
Speed
• Keep Hierarchy
no
• Macro Preserve
no

Apply the equation shaping algorithm. Options to be selected:
2 or High
• Macro Preserve
no
• Keep Hierarchy
no

Fitting a Large Design

A design may not fit in the target device because it exceeds the number of device
macrocells or device P-Term capacity. In that event, you may:
• Select an Area Optimization for XST, or
• Use the WYSIWYG Command Line Option
Select an Area Optimization for XST

When you select an area optimization for XST, statistically the best area results are
obtained with the following options:
1 (Normal) or 2 (High)
area
• Default values for other options
Use the WYSIWYG Command Line Option

Another option for fitting a large design is to use the WYSIWYG (-wysiwyg) command
line option with the following setting:
-wysiwyg yes
The WYSIWYG command line option may be useful when:
• The design cannot be simplified by default optimization strategies, and
• The complexity (in number of P-Terms) is near the device capacity.
Default optimizations, by trying to reduce the number of logic levels, may create larger
equations. This increases the number of P-Terms and prevents the design from fitting.
Unlike those optimizations, the WYSIWYG (-wysiwyg) command line option enables an
approach that does not increase the number of P-Terms, ideally allowing the design to fit.

Chapter 6

This chapter gives general information about XST Design Constraints, and includes:
• About XST Design Constraints
• Mechanisms for Specifying Constraints
• Global and Local Constraint Settings
• Rules for Applying Constraints
• Setting Global Constraints and Options
• VHDL Attribute Syntax
• Verilog-2001 Attributes
• XST Constraint File (XCF)
• Constraints Priority
• XST Specific Non-Timing Options
• XST Command Line Only Options
For information about specific XST design constraints, see:
• XST General Constraints
• XST HDL Constraints
• XST FPGA Constraints (Non-Timing)
• XST CPLD Constraints (Non-Timing)
• XST Timing Constraints
• XST Implementation Constraints
• XST-Supported Third Party Constraints
About XST Design Constraints

Constraints help you meet your design goals and obtain the best implementation of
your circuit. Constraints control various aspects of synthesis, as well as placement and
routing. Synthesis algorithms and heuristics automatically provide optimal results
in most situations. If synthesis fails to initially achieve optimal results, use available
constraints to try other synthesis alternatives.

Chapter 6: XST Design Constraints
Mechanisms for Specifying Constraints

The following mechanisms are available to specify constraints:
• Options provide global control of most synthesis aspects. They can be set either in:
– ISE® Design Suite in Process > Properties > Synthesis Options, or
– by the run command from the command line
• In VHDL, attributes can be directly inserted into the VHDL code and attached to
individual elements of the design to control both synthesis, and placement and
routing.
• In Verilog, constraints can be added as:
– Verilog attributes (preferred)
– Verilog meta comments
• Constraints can be specified in a separate constraint file.
Global and Local Constraint Settings

Global synthesis settings are typically defined in ISE® Design Suite in Process >
Properties > Synthesis Options, or from the command line. VHDL and Verilog
attributes and Verilog meta comments can be inserted in your source code to specify
different choices for individual parts of the design.
The local specification of a constraint overrides its global setting. Similarly, if a constraint
is set both on a node (or an instance) and on the enclosing design unit, the former takes
precedence for the considered node (or instance).
Rules for Applying Constraints

Follow these general rules when applying constraints:
• Several constraints can be applied on signals. In this case, the constraint must be
placed in the block where the signal is declared and used.
• If a constraint can be applied on an entity (VHDL), then it can also be applied on
the component declaration. The ability to apply constraints on components is not
explicitly stated for each individual constraint, since it is a general XST rule.
• Some third party synthesis tools allow you to apply constraints on architectures.
XST allows constraints on architectures only for those third party constraints
automatically supported by XST.

Setting Global Constraints and Options

This section discusses Setting Global Constraints and Options, and includes:
• Setting Synthesis Options
• Setting HDL Options
• Setting Xilinx Specific Options
• Setting Other XST Command Line Options
• Custom Compile File List
This section explains how to set global constraints and options in ISE® Design Suite
in Process > Process Properties.
For a description of each constraint that applies generally (that is, to FPGA devices,
CPLD devices, VHDL, and Verilog) see the Constraints Guide.
Except for Value fields with check boxes, there is a pulldown arrow or browse button in
each Value field. The arrow is not visible until you click in the Value field.
Setting Synthesis Options

To set Hardware Description Language (HDL) synthesis options from ISE® Design Suite:
1. Select a source file from the Source File window.
2. Right-click Synthesize - XST in the Process window.
3. Select Properties.
4. Select Synthesis Options.
5. Depending on the device type you have selected (FPGA or CPLD devices), one of
two dialog boxes opens.
6. Select any of the following synthesis options:
• Optimization Goal (OPT_MODE)
• Optimization Effort (OPT_LEVEL)
• Use Synthesis Constraints File (-iuc)
• Synthesis Constraint File (-uc)
• Library Search Order (-lso)
• Generate RTL Schematic (-rtlview)
• Verilog 2001 (-verilog2001)

Select Edit > Preferences > Processes > Property Display Level > Advanced to view the
following options:
• Cross Clock Analysis (-cross_clock_analysis)
• Hierarchy Separator (-hierarchy_separator)
• Bus Delimiter (-bus_delimiter)
• Case (-case)
• Work Directory (-xsthdpdir)
• HDL Library Mapping File (-xsthdpini)
• Verilog Include Directories (-vlgincdir)
• Slice (LUT-FF Pairs) Utilization Ratio (SLICE_UTILIZATION_RATIO)
Setting HDL Options

This section discusses Setting HDL Options, and includes:
• How to Set HDL Options
• Setting HDL Options for FPGA Devices
• Setting HDL Options for CPLD Devices
How to Set HDL Options

To set Hardware Description Language (HDL) options for FPGA devices and CPLD
devices in ISE® Design Suite select:
Process > Process Properties > Synthesize - XST > HDL Options

Setting HDL Options for FPGA Devices

The following HDL Options can be set for FPGA devices:
• Case Implementation Style (-vlgcase)
To view FSM Style, select Edit > Preferences > Processes > Property Display Level
> Advanced
• Shift Register Extraction (SHREG_EXTRACT)
• Resource Sharing (RESOURCE_SHARING)
For later devices, Multiplier Style is renamed as follows:
– Use DSP48
Virtex®-4 devices
– Use DSP Block
Virtex-5 devices and Spartan®-3A DSP devices
Setting HDL Options for CPLD Devices

The following HDL Options can be set for CPLD devices:
Setting Xilinx Specific Options

This section discusses Setting Xilinx® Specific Options, and includes:
• How to Set Xilinx Specific Options
• Setting Xilinx Specific Options for FPGA Devices
• Setting Xilinx Specific Options for CPLD Devices

How to Set Xilinx Specific Options

To set Xilinx specific options in ISE® Design Suite, select:
Process > Process Properties > Synthesis Options > Xilinx Specific Options
Setting Xilinx Specific Options for FPGA Devices

The following Xilinx specific options can be set for FPGA devices:
• Add I/O Buffers (-iobuf)
• LUT Combining (LC)
• Reduce Control Sets (REDUCE_CONTROL_SETS)
• Convert Tristates to Logic (TRISTATE2LOGIC)
Convert Tristate to Logic appears only when working with devices with internal
tristate resources.
• Use Clock Enable (USE_CLOCK_ENABLE)
• Use Synchronous Set (USE_SYNC_SET)
• Use Synchronous Reset (USE_SYNC_RESET)
Select Edit > Preferences > Processes > Property Display Level > Advanced in ISE
Design Suite to display the following options:
• Number of Regional Clock Buffers (-bufr)
Setting Xilinx Specific Options for CPLD Devices

The following Xilinx specific options can be set for CPLD devices:
Setting Other XST Command Line Options

This section discusses Setting Other XST Command Line Options, and includes:
• Setting Options in ISE Design Suite
• Tips for Setting Options
• Options Precedence
• Illegal or Unrecognized Options

Setting Options in ISE Design Suite

Set other XST command line options in ISE® Design Suite in:
Process > Process Properties > Other XST Command Line Options
This is an advanced property.
Tips for Setting Options

When setting XST command line options:
• Use the syntax described in XST Command Line Mode.
• Separate multiple options with a space.
Options Precedence
While this property is intended for options not listed in Process > Process Properties, if
an option already listed is entered, precedence is given to that option.
Illegal or Unrecognized Options

Illegal or unrecognized options cause XST to stop processing and generate a message
such as:
ERROR:Xst:1363 - Option "-verilog2002" is not available
for command run.
Custom Compile File List

Use the Custom Compile File List property to change the order in which XST processes
source files are processed. With this property, you select a user-defined compile list file
that XST uses to determine the order in which it processes libraries and design files.
Otherwise, XST uses an automatically generated list.
List all design files and their libraries in the order in which they are to be compiled,
from top to bottom. Type each file and library pair on its own line, with a semicolon
separating the library from the file as follows:
library_name; file_name [library_name;file_name] ...
Example:
work;stopwatch.vhd
work;statmach.vhd
...
Since this property is not connected to Simulation Properties > Custom Compile File
List, a different compile list file is used for synthesis than for simulation.

VHDL Attribute Syntax

You can describe constraints with VHDL attributes in the VHDL code.
Declare as follows:
attribute AttributeName : Type;
Syntax Example One

attribute RLOC : string ;
The attribute type defines the type of the attribute value. The only allowed type for XST
is string. An attribute can be declared in an entity or architecture. If declared in the
entity, it is visible both in the entity and the architecture body. If the attribute is declared
in the architecture, it cannot be used in the entity declaration.
Specify as follows:
attribute AttributeName of ObjectList : ObjectType is AttributeValue ;
Syntax Example Two

attribute RLOC of u123 : label is R11C1.S0 ; attribute bufg of my_signal: signal is sr;
Accepted Object Types

The object list is a comma separated list of identifiers. Accepted object types are:
• entity
• component
• label
• signal
• variable
• type
General Rules
• If a constraint can be applied on an entity (VHDL), then it can also be applied on
the component declaration. The ability to apply constraints on components is not
explicitly stated for each individual constraint, since it is a general XST rule.
• Some third party synthesis tools allow you to apply constraints on architectures.
XST allows constraints on architectures only for those third party constraints
automatically supported by XST.
Verilog-2001 Attributes
XST supports Verilog-2001 attribute statements. Attributes are comments that pass
specific information to software tools such as synthesis tools. Verilog-2001 attributes
can be specified anywhere for operators or signals within module declarations and
instantiations. Other attribute declarations may be supported by the compiler, but
are ignored by XST.
Verilog-2001 Attributes Syntax

Verilog-2001 attributes are bounded by the asterisk character (*).
(* attribute_name = attribute_value *)

where
• attribute precedes the signal, module, or instance declaration to which it refers.
• attribute_value is a string. No integer or scalar values are allowed.
• attribute_value is between quotes.
• The default is 1.
• (* attribute_name *) is the same as (* attribute_name = "1" *).
Syntax Example One

(* clock_buffer = "IBUFG" *) input CLK;
Syntax Example Two

(* INIT = "0000" *) reg [3:0] d_out;
Syntax Example Three

always@(current_state or reset) begin (* parallel_case *) (* full_case *) case
(current_state) ...
Syntax Example Four

(* mult_style = "pipe_lut" *) MULT my_mult (a, b, c);
Verilog-2001 Limitations
Verilog-2001 attributes are not supported for:
• Signal declarations
• Statements
• Port connections
• Expression operators
Verilog-2001 Meta Comments

Constraints can also be specified in Verilog code using meta comments. The Verilog-2001
format is the preferred syntax, but the meta comment style is still supported. Use the
following syntax:
// synthesis attribute AttributeName [of] ObjectName [is] AttributeValue
Verilog-2001 Meta Comments Examples

// synthesis attribute RLOC of u123 is R11C1.S0
// synthesis attribute HU_SET u1 MY_SET
// synthesis attribute bufg of my_clock is "clk"
The following constraints use a different syntax:
• Parallel Case (PARALLEL_CASE)
• Full Case (FULL_CASE)
• Translate Off (TRANSLATE_OFF) and Translate On (TRANSLATE_ON)
Verilog Attributes and Meta Comments

XST Constraint File (XCF)

• Specifying Constraints in the XCF
• XCF Syntax and Utilization
• Native and Non-Native UCF Constraints Syntax
• XCF Syntax Limitations
Specifying Constraints in the XCF

XST constraints can be specified in the XST Constraint File (XCF).
The XCF has an extension of .xcf.
You can specify the XCF in:
ISE Design Suite Help
• Command Line Mode
To specify the XCF in command line mode, use Synthesis Constraint File (-uc) with
the run command.
XST Command Line Mode
XCF Syntax and Utilization

This section discusses XCF Syntax and Utilization, and includes:
• About XCF Syntax and Utilization
• Syntax
• Syntax Examples and Settings
• XST Synthesis Constraints
About XCF Syntax and Utilization

The XST Constraint File (XCF) syntax enables you to specify a specific constraint for:
• The entire device (globally), or
• Specific modules
The XCF syntax is basically the same as the User Constraints File (UCF) syntax for
applying constraints to nets or instances, but with an extension to the syntax to allow
constraints to be applied to specific levels of hierarchy. Use the keyword MODEL to define
the entity or module to which the constraint is applied. If a constraint is applied to an
entity or module, the constraint is applied to each instance of the entity or module.
Define constraints in ISE® Design Suite in Process > Process Properties, or the XST
run script, if running on the command line. Specify exceptions in the XCF file. The
constraints specified in the XCF file are applied only to the module listed, and not to
any submodules below it.
Syntax
To apply a constraint to the entire entity or module use the following syntax:

MODEL entityname constraintname = constraintvalue;
Syntax Examples and Settings

The following syntax examples and settings show how to use this constraint or
command line option with particular tools or methods. If a tool or method is not listed,
you cannot use this constraint or command line option with it.
XCF Syntax Example One

MODEL top mux_extract = false; MODEL my_design max_fanout = 256;
If the entity my_design is instantiated several times in the design, the max_fanout=256
constraint is applied to each instance of my_design.
To apply constraints to specific instances or signals within an entity or module, use the
INST or NET keywords. XST does not support constraints that are applied to VHDL
variables.
BEGIN MODEL entityname
INST instancename constraintname = constraintvalue;
NET signalname constraintname = constraintvalue;
END;
XCF Syntax Example Two

BEGIN MODEL crc32
INST stopwatch opt_mode = area ;
INST U2 ram_style = block ;
NET myclock clock_buffer = true ;
NET data_in iob = true ;
END;
XST Synthesis Constraints

For a complete list of XST synthesis constraints, see:
XST Specific Non-Timing Options
Native and Non-Native UCF Constraints Syntax

All constraints supported by XST can be divided into two groups:
• Native UCF Constraints
• Non-Native UCF Constraints
Native UCF Constraints

Only Timing and Area Group constraints use native User Constraints File (UCF) syntax.

Use native UCF syntax, including wildcards and hierarchical names, for native UCF
constraints such as:
• Period (PERIOD)
• Offset (OFFSET)
• Timing Name on a Net (TNM_NET)
• Timegroup (TIMEGRP)
• Timing Ignore (TIG)
• From-To (FROM-TO)
Restriction Do not use these constraints inside the BEGIN MODEL... END construct.
If you do, XST issues an error.
Non-Native UCF Constraints

For all non-native User Constraints File (UCF) constraints, use the MODEL or BEGIN
MODEL... END; constructs. This includes:
• Pure XST constraints such as:
– Automatic FSM Extraction (FSM_EXTRACT)
– RAM Style (RAM_STYLE)
• Implementation non-timing constraints such as:
– RLOC
– Keep (KEEP)
If you specify timing constraints in the XST Constraint File (XCF), Xilinx® recommends
that you use a forward slash (/) as a hierarchy separator instead of an underscore (_).
Hierarchy Separator (-hierarchy_separator)
XCF Syntax Limitations

XST Constraint File (XCF) syntax has the following limitations:
• Nested model statements are not supported.
• Instance or signal names listed between the BEGIN MODEL statement and the
END statement are only the ones visible inside the entity. Hierarchical instance or
signal names are not supported.
• Wildcards in instance and signal names are not supported, except in timing
constraints.
• Not all native User Constraints File (UCF) constraints are supported.
For more information, see the Constraints Guide.
Constraints Priority
Constraints priority depends on the file in which the constraint appears. A constraint in
a file accessed later in the design flow overrides a constraint in a file accessed earlier
in the design flow.
Priority is as follows, from highest to lowest:
1. Synthesis Constraint File
2. Hardware Description Language (HDL) file
3. ISE® Design Suite Process > Process Properties, or the command line


The following table shows:
• Allowed values for each constraint
• Type of objects to which they can be applied
• Usage restrictions
In many cases, a particular constraint can be applied globally to an entire entity or
model, or alternatively, it can be applied locally to individual signals, nets or instances.
Constraint Constraint VHDL Verilog XCF Target Command Command
Name Target Line Value
Value Target
BoxType primitive entity module model N/A N/A
black_box inst inst inst (in model)
user_black_box
Map Logic on yes entity module model N/A N/A
BRAM
no
Buffer Type bufgdll signal signal net (in model) N/A N/A
ibufg
bufg
bufgp
ibuf
bufr
none
Extract yes primary primary net (in model) -bufgce yes
BUFGCE
no clock clock no
signal signal default: no

Clock Signal yes clock clock clock N/A N/A
no signal signal signal
net (in model)
Decoder yes entity entity model -decoder yes
Extraction _extract
no signal signal net (in model) no
default: yes
Enumerated string type signal net (in model) N/A N/A
Encoding containing
space-separated
binary codes
Equivalent yes entity module model -equivalent yes
Register _register
Removal _removal
default: yes


Value Target
FSM Encoding auto entity module model -fsm auto
Algorithm _encoding
one-hot signal signal net (in model) one-hot
compact compact
sequential sequential
gray gray
johnson johnson
speed1 speed1
user user
default: auto
Automatic yes entity module model -fsm yes
FSM Extraction _extract
default: yes
FSM Style lut entity module model -fsm lut
_style
bram signal signal net (in model) bram
default: lut
Full Case N/A N/A case statement N/A N/A N/A
Pack I/O true signal signal net (in model) -iob true
Registers Into
IOBs false instance instance inst (in model) false
auto auto
default: auto
I/O Standard string signal signal net (in model) N/A N/A
For more instance instance inst (in model)
information,
see the
Constraints
Guide.
Keep true signal signal net (in model) N/A N/A
false
soft
Keep yes entity module model -keep yes default
Hierarchy _hierarchy (CPLD)
no
no default
soft
(FPGA)
soft
LOC string signal (primary signal (primary net (in model) N/A N/A
IO) IO)
inst (in model)
instance instance
Map Entity on yes entity module model N/A N/A
a Single LUT
no architecture


Value Target
Max Fanout integer entity module model -max integer
_fanout
signal signal net (in model) default: see
detailed
description
Move First yes entity module model -move yes
Stage _first
no primary primary primary clock _stage no
clock clock signal default: yes
signal signal net (in model)

Move Last yes entity module model -move yes
Stage _last
no primary primary primary clock _stage no
clock clock signal default: yes
signal signal net (in model

Multiplier auto entity module model -mult auto
Style _style
block signal signal net (in model) block
pipe_block pipe_block
kcm kcm
csd csd
lut lut
pipe_lut pipe_lut
default: auto
Mux Extraction yes entity module model -mux yes
_extract
force force
default: yes
Mux Style auto entity module model -mux auto
_style
muxf signal signal net (in model) muxf
muxcy muxcy
default: auto
No Reduce yes signal signal net (in model) N/A N/A
no
Optimization 1 entity module model -opt 1
Effort _level
2 2
default: 1
Optimization speed entity module model -opt speed
Goal _mode
area area
default: speed


Value Target
Optimize yes entity module model -optimize yes
Instantiated _primitives
Primitives no instance instance instance (in no
model)
default: no
Parallel Case N/A N/A case statement N/A N/A N/A
Power yes entity module model -power yes
Reduction
no no
default: no
Priority yes entity module model -priority yes
Encoder _extract
Extraction no signal signal net (in model) no
force force
default: yes
RAM yes entity module model -ram yes
Extraction _extract
default: yes
RAM Style auto entity module model -ram auto
_style
distributed distributed
pipe_distributed default: auto
block_power1
block_power2
Read Cores yes entity module model -read yes
_cores
no component label inst (in model) no
optimize optimize
default: yes
Register yes entity module modelnet (in -register yes
Balancing model)inst (in _balancing
no signal signal no
model)
forward FF FF forward
backward instance name instance name backward
primary clock default: no

signal
Register yes entity module model -register yes
Duplication _duplication
no signal net (in model) no
default: yes
Resource yes entity module model -resource yes
Sharing _sharing
default: yes


Value Target
ROM yes entity module model -rom yes
Extraction _extract
default: yes
ROM Style auto entity module model -rom auto
_style
distributed distributed
default: auto
Save yes signal signal net (in model) N/A N/A
no inst of inst of inst of
primitive primitive primitive (in
model)
Safe yes entity module model -safe yes
Implementation _implementation
default: no
Safe Recovery string signal signal net (in model) N/A N/A
State
Logical Shifter yes entity module model -shift yes
Extraction _extract
default: yes
Shift Register yes entity module model -shreg yes
Extraction extract
default: yes
Signal auto entity module model -signal auto
Encoding _encoding
one-hot signal signal net (in model) one-hot
user user
default: auto
Slice integer (range entity module model -slice integer (range
Utilization -1 to 100) _utilization -1 to 100)
Ratio _ratio
integer% integer%
(range -1 to (range -1 to
100) 100)
integer# integer#
default: 100
Slice integer (range entity module model -slice integer (range
Utilization 0 to 100) _utilization 0 to 100)
Ratio Delta _ratio
integer% _maxmargin integer%
(range 0 to 100) (range 0 to 100)
integer# integer#
default: 0


Value Target
Translate Off N/A local local N/A N/A N/A
and Translate
On no target no target
Convert yes entity modulesignal model -tristate2logic yes

Tristates to
Logic no signal net (in model) no
default: yes
Use Carry yes entity module model -use yes
Chain _carry
no signal signal net (in model) _chain no
default: yes
Use Clock auto entity module model -use auto
Enable _clock
yes signal signal net (in model) _enable yes
no FF FF inst (in model) no
instance instance default: auto
name name
Use DSP48 auto entity module model -use auto
_dsp48
yes signal signal net (in model) yes
no no
default: auto
Use auto entity module model -use auto
Synchronous _sync
Reset yes signal signal net (in model) _reset yes
name name
Use auto entity module model -use auto
Synchronous _sync
Set yes signal signal net (in model) _set yes
name name
XOR yes entity module model -xor yes
Collapsing _collapse
default: yes

XST Command Line Only Options

This section discusses XST Command Line Only Options, and includes:
• XST Specific Non-Timing Options Supported Only in the Command Line
• Invoking XST Timing Options
• XST Timing Constraints Supported Only in Process > Process Properties, or the
Command Line
• XST Timing Constraints Supported Only in the XCF
XST Specific Non-Timing Options Supported Only in the Command

Line
Constraint Name Command Line Command Value
VHDL Top Level Architecture -arch architecture_name
default: N/A
Asynchronous to Synchronous -async_to_sync yes
no
default: no
Automatic BRAM Packing -auto_bram_packing yes
no
default: no
BRAM Utilization Ratio -bram_utilization_ integer (range -1 to 100)
(BRAM_UTILIZATION_RATIO) ratio integer% (range -1 to 100)
integer#
default: 100
Maximum Global Clock Buffers -bufg Integer
default: max number of buffers in
target device
Maximum Regional Clock Buffers -bufr Integer
default: max number of buffers in
target device
Bus Delimiter -bus_delimiter <>
[]
{}
()
default: <>
Case -case upper
lower
maintain
default: maintain
Verilog Macros -define {name = value}
default: N/A


DSP Utilization Ratio -dsp_utilization_ratio integer (range -1 to 100)
(DSP_UTILIZATION_RATIO)
integer% (range -1 to 100)
integer#
default: 100
Duplication suffix -duplication_suffix string%dstring
default: _%d
VHDL Top-Level block -ent entity_name
(Valid only when old VHDL project default: N/A
format is used (-ifmt VHDL). Use
project format (-ifmt mixed) and - top
option to specify which top level block
to synthesize.)
Generics -generics {name = value}
default: N/A
HDL File Compilation Order -hdl_compilation_order auto
user
default: auto
Hierarchy Separator -hierarchy_separator _
/
default: /
Input Format -ifmt mixed
vhdl
verilog
default: mixed
Input/Project File Name -ifn file_name
default: N/A
Add I/O Buffers -iobuf yes
no
default: yes
Ignore User Constraints -iuc yes
no
default: no
Library Search Order -lso file_name.lso
default: N/A
LUT Combining -lc auto
area
off
default: off


Netlist Hierarchy -netlist_hierarchy as_optimized
rebuilt
default: as_optimized
Output File Format -ofmt ngc
default: ngc
Output File Name -ofn file_name
default: N/A
Target Device -p part-package-speed (For example:
xc5vfx30t-ff324-2)
default: N/A
Clock Enable -pld_ce yes
no
default: yes
Macro Preserve -pld_mp yes
no
default: yes
XOR Preserve -pld_xp yes
no
default: yes
Reduce Control Sets -reduce_control_sets auto
no
default: no
Generate RTL Schematic -rtlview yes
no
only
default: no
Cores Search Directories -sd directories
default: N/A
Slice Packing -slice_packing yes
no
default: yes
Top Level Block -top block_name
default: N/A
Synthesis Constraints File -uc file_name.xcf
default: N/A
Verilog 2001 -verilog2001 yes
no
default: yes


Case Implementation Style -vlgcase full
parallel
full-parallel
default: N/A
Verilog Include Directories -vlgincdir directories
default: N/A
Work Library -work_lib directory
default: work
wysiwyg -wysiwyg yes
no
default: no
Work Directory -xsthdpdir Directory
default: ./xst
HDL Library Mapping File -xsthdpini file_name.ini
default: N/A
Invoking XST Timing Options

Invoke XST timing options from:
• ISE® Design Suite in Process > Process Properties
• Command line
XST Timing Constraints Supported Only in Process > Process

Properties, or the Command Line
Option Process > Process Properties Values
(ISE® Design Suite)
glob_opt Global Optimization Goal allclocknetsinpad
_to_outpadoffset
_in_beforeoffset
_out_aftermax
_delay
default: allclocknets
cross_clock_analysis Cross Clock Analysis yes
no (default)
write_timing_constraints Write Timing Constraints yes
no (default)

XST Timing Constraints Supported Only in the XCF

The following XST timing constraints can be applied for synthesis only through the
XST Constraint File (XCF):
• Period (PERIOD)
• Offset (OFFSET)
• Timing Name (TNM)
• Timing Specifications (TIMESPEC)
• Timing Specification Identifier (TSidentifier)
These timing constraints influence synthesis optimization, and can be passed on to place
and route by selecting the Write Timing Constraints command line option.

Chapter 7
XST General Constraints

This chapter discusses the following constraints:
• BoxType (BOX_TYPE)
• Case (-case)
• Duplication Suffix (-duplication_suffix)
• Full Case (FULL_CASE)
• Generate RTL Schematic (-rtlview)
• Generics (-generics)
• HDL Library Mapping File (-xsthdpini)
• I/O Standard (IOSTANDARD)
• Keep (KEEP)
• Library Search Order (-lso)
• LOC
• Netlist Hierarchy (-netlist_hierarchy)
• Optimization Effort (OPT_LEVEL)
• Optimization Goal (OPT_MODE)
• RLOC
• Save (S / SAVE)
• Synthesis Constraint File (-uc)
• Use Synthesis Constraints File (-iuc)
• Verilog 2001 (-verilog2001)
• Verilog Include Directories (-vlgincdir)
• Verilog Macros (-define)
• Work Directory (-xsthdpdir)

Chapter 7: XST General Constraints
Add I/O Buffers (-iobuf)

The Add I/O Buffers (-iobuf) command line option:
• Enables or disables I/O buffer insertion.
• Can be used to synthesize a part of a design to be instantiated later on.
XST automatically inserts Input/Output Buffers into the design. If you manually
instantiate I/O Buffers for some or all the I/Os, XST inserts I/O Buffers only for the
remaining I/Os. If you do not want XST to insert I/O Buffers, set -iobuf to no.
Architecture Support
Architecture independent.
Applicable Elements
Applies to the entire design.
Propagation Rules
Applies to design primary IOs.
Syntax
-iobuf {yes|no|true|false|soft}
• yes (default)
Tells XST to generate IBUF and OBUF primitives and connected them to I/O ports
of the top-level module.
• no
Tells XST not to generate IBUF and OBUF primitives, and must be used when XST is
called to synthesize an internal module that is instantiated later in a larger design.
If I/O buffers are added to a design, this design cannot be used as a submodule
of another design.
• true
• false
• soft

XST Command Line

xst run -iobuf yes
Adds I/O buffers to the top level module of the design.
ISE® Design Suite

Process > Process Properties > Xilinx®-Specific Options > Add I/O Buffers

BoxType (BOX_TYPE)
The BoxType (BOX_TYPE) constraint is a synthesis constraint.
If BoxType is applied to at least a single instance of a block of a design, BoxType is
propagated to all other instances of the entire design. This feature was implemented
for Verilog and XST Constraint File (XCF) in order to have a VHDL-like support, where
BoxType can be applied to a component.
Applicable Elements
Applies to the following design elements:
• VHDL
component, entity
• Verilog
module, instance
model, instance
Propagation Rules
Applies to the design element to which it is attached.
Syntax
• primitive
• black_box
Equivalent to primitive. Will eventually become obsolete.
• user_black_box
XST reports inference of a black box in the log file unless primitive is specified.
These values instruct XST not to synthesize the behavior of a module.

VHDL
Declare as follows:
attribute box_type: string;
Specify as follows:
attribute box_type of {component_name|entity_name} : {component|entity} is
"{primitive|black_box|user_black_box}";
Verilog
Place immediately before the instantiation:

(* box_type = "{primitive|black_box|user_black_box}" *)

MODEL "entity_name" box_type = "{primitive|black_box|user_black_box}";

BEGIN MODEL" entity_name"
INST "instance_name"
box_type="{primitive|black_box|user_black_box}";
END;
Bus Delimiter (-bus_delimiter)

The Bus Delimiter (-bus_delimiter) command line option defines the format of signals
belonging to buses in the output netlist.
Applicable Elements
Applies to syntax.
Propagation Rules
Not applicable.
Syntax
-bus_delimiter {<>|[]|{}|()}
• <> (default)
• []
• {}
• ()

XST Command Line

xst run -bus_delimiter []
Defines bus delimiters globally as square braces ([]).
ISE® Design Suite

Process > Process Properties > Synthesis Options > Bus Delimiter

Case (-case)
The Case (-case) command line option determines if instance and net names are written
in the final netlist using all lowercase or uppercase letters, or if the case is maintained
from the source.
The case can be maintained for either Verilog or VHDL.
Applicable Elements
Applies to syntax.
Propagation Rules
Not applicable.
Syntax
-case {upper|lower|maintain}
• upper
• lower
• maintain (default)

XST Command Line

xst run -case upper
Defines case globally to uppercase.
ISE® Design Suite

Case Implementation Style (-vlgcase)

The Case Implementation Style (-vlgcase) command line option:
• Is valid for Verilog designs only.
• Instructs XST how to interpret Verilog case statements.
• Multiplexers HDL Coding Techniques
• FULL_CASE (Full Case)
• PARALLEL_CASE (Parallel Case)

Applicable Elements
Propagation Rules
Not applicable.
Syntax
-vlgcase {full|parallel|full-parallel}
• full
XST assumes that the case statements are complete, and avoids latch creation.
• parallel
XST assumes that the branches cannot occur in parallel, and does not use a priority
encoder.
• full-parallel
XST assumes that the case statements are complete, and that the branches cannot
occur in parallel, therefore saving latches and priority encoders.
By default, there is no value. If the option is not specified, XST implements the exact
behavior of the case statements.

XST Command Line

xst run -vlgcase full
Defines Case Implementation Style globally to full.
ISE® Design Suite

Process > Process Properties > HDL Options > Case Implementation Style
Duplication Suffix (-duplication_suffix)

The Duplication Suffix (-duplication_suffix) command line option controls how XST
names replicated flip-flops.
By default, when XST replicates a flip-flop, it creates a name for the new flip-flop by
taking the name of the original flip-flop and adding _n to the end of it, where n is an
index number.

For instance, if the original flip-flop name is my_ff, and this flip-flop was replicated
three times, XST generates flip-flops with the following names:
• my_ff_1
• my_ff_2
• my_ff_3
Duplication Suffix lets you change the string that is added to the original name.
Applicable Elements
Applies to files.
Propagation Rules
Not applicable.
Syntax
-duplication_suffix string%dstring
The default is %d.

XST Command Line Example One

xst run -duplication_suffix _dupreg_%d
If the flip-flop named my_ff is duplicated three times, this command tells XST to
generate the following names:
• my_ff_dupreg_1
• my_ff_dupreg_2
• my_ff_dupreg_3
XST Command Line Example Two

xst run -duplication_suffix _dup_%d_reg
The %d escape character can be placed anywhere in the suffix definition. If the
flip-flop named my_ff is duplicated three times, this command tells XST to generate
the following names:
• my_ff_dup_1_reg
• my_ff_dup_2_reg
• my_ff_dup_3_reg

ISE® Design Suite

Process > Process Properties > Synthesis Options > Property display level > Advanced
> Other XST Command Line Options
Full Case (FULL_CASE)

The Full Case (FULL_CASE) constraint:
• Indicates that all possible selector values have been expressed in a case, casex, or
casez statement.
• Prevents XST from creating additional hardware for those conditions not expressed.
Applicable Elements
Applies to case statements in Verilog meta comments.
Propagation Rules
Not applicable.
Syntax
-vlgcase [full|parallel|full-parallel]
• full
• parallel
• full-parallel

Verilog
The syntax is:
(* full_case *)
Since FULL_CASE does not contain a target reference, the attribute immediately
precedes the selector:
(* full_case *)
casex select
4’b1xxx: res = data1;
4’bx1xx: res = data2;
4’bxx1x: res = data3;
4’bxxx1: res = data4;
endcase

FULL_CASE is also available as a meta comment in the Verilog code. The syntax differs
from the standard meta comment syntax as shown in the following:
// synthesis full_case
Since FULL_CASE does not contain a target reference, the meta comment immediately
follows the selector:
casex select // synthesis full_case
endcase
XST Command Line
xst run -vlgcase [full|parallel|full-parallel]
ISE® Design Suite

Process > Process Properties > Synthesis Options > Full Case.
For Case Implementation Style, select full.
Generate RTL Schematic (-rtlview)

The Generate RTL Schematic (-rtlview) command line option tells XST to generate
a netlist file representing a Register Transfer Level (RTL) structure of the design. This
netlist can be viewed by the RTL and Technology Viewers.
The file containing the RTL view has an NGR file extension.
Applicable Elements
Applies to files.
Propagation Rules
Not applicable.
Syntax
-rtlview {yes|no|only}
• yes
Tells XST to generate an RTL view.
• no (default)
Tells XST not to generate the RTL view.
• only
Tells XST to stop the synthesis once the RTL view is generated.


XST Command Line

xst run -rtlview yes
Tells XST to generate a netlist file representing the RTL structure of the design.
ISE® Design Suite

Process > Process Properties > Synthesis Options > Generate RTL Schematic
Generics (-generics)
The Generics (-generics) command line option allows you to redefine generics (VHDL)
or parameters (Verilog) values defined in the top-level design block.
This allows you to easily modify the design configuration without any Hardware
Description Language (HDL) source modifications, such as for IP core generation and
testing flows. If the defined value does not correspond to the data type defined in the
VHDL or Verilog code, then XST tries to detect the situation and issues a warning,
ignoring the command line definition.
In some situations, XST may fail to detect a type mismatch. In that case, XST attempts to
apply this value by adopting it to the type defined in the VHDL or Verilog file without
any warning. Be sure that the value you specified corresponds to the type defined in
the VHDL or Verilog code. If a defined generic or parameter name does not exist in the
design, no message is given, and the definition is ignored.
Applicable Elements
Propagation Rules
Not applicable.
Syntax
-generics {name=valuename=value ...}
where
• name is the name of a generic or parameter of the top level design block
• value is the value of a generic or parameter of the top level design block
The default is an empty definition.

Follow these rules:

• Place the values inside curly braces ({...}).
• Separate the values with spaces.
• XST can accept as values only constants of scalar types. Composite data types
(arrays or records) are supported only in the following situations:
– string
– std_logic_vector
– std_ulogic_vector
– signed, unsigned
– bit_vector
• There are no spaces between the prefix and the corresponding value.

XST Command Line

xst run -generics {company="Xilinx" width=5 init_vector=b100101}
This command sets:
• company to Xilinx®
• width to 5
• init_vector to b100101
ISE® Design Suite

Process > Process Properties > Synthesis Options > Generics, Parameters
HDL Library Mapping File (-xsthdpini)

The HDL Library Mapping File (-xsthdpini) command line option defines the library
mapping.
XST maintains two library mapping files:
• The pre-installed (default) INI file, which is installed during the Xilinx® software
installation
• The user file, which you may define for your own projects
The pre-installed (default) INI file:
• Is named xhdp.ini.
• Is located in %XILINX%\vhdl\xst.
• Contains information about the locations of the standard VHDL and UNISIM
libraries.
• Should not be modified
Note You can copy the syntax for your own library mapping file
A library mapping file looks like the following:

-- Default lib mapping for XST std=$XILINX/vhdl/xst/std

ieee=$XILINX/vhdl/xst/unisim unisim=$XILINX/vhdl/xst/unisim
aim=$XILINX/vhdl/xst/aim pls=$XILINX/vhdl/xst/pls
Use this file format to define where each of your own libraries must be placed. By
default, all compiled VHDL flies are stored in the xst subdirectory of the ISE Design
Suite project directory.
The library mapping file contains a list of libraries, one per line with the following
information:
• The library name
• The directory in which the library is compiled
You can give this library mapping file any name you wish, but it is best to keep the
.ini classification.
The format for each line is:
library_name=path_to_compiled_directory
Use a double dash (--) to start a comment line.
Applicable Elements
Applies to files.
Propagation Rules
Not applicable.
Syntax
-xsthdpini file_name
You can specify only one library mapping file.

XST Command Line

xst set -xsthdpini c:/data/my_libraries/my.ini file_name
Specifies c:/data/my_libraries/my.ini as the file that will point to all of your
libraries.
You must run this set command before any run commands.
Following is an MY.INI example text:
work1=H:\Users\conf\my_lib\work1 work2=C:\mylib\work2

ISE® Design Suite

To set the library mapping file location in ISE Design Suite:
1. Select Process > Process Properties > Synthesis Options
2. From the Property display level list, select Advanced
3. Set the HDL INI File property.

The Hierarchy Separator (-hierarchy_separator) command line option defines the
hierarchy separator character that is used in name generation when the design hierarchy
is flattened.
If a design contains a sub-block with instance INST1, and this sub-block contains a net
called TMP_NET, then the hierarchy is flattened and the hierarchy separator character
is / (forward slash). The name TMP_NET becomes INST1_TMP_NET. If the hierarchy
separator character is / (forward slash), the net name is INST1/TMP_NET.
Using / (forward slash) as a hierarchy separator is useful in design debugging because
the / (forward slash) separator makes it much easier to identify a name if it is hierarchical.
Applicable Elements
Applies to files.
Propagation Rules
Not applicable.
Syntax
-hierarchy_separator {/ | _}
The two supported characters are:
• _ (underscore)
• / (forward slash)
The default is / (forward slash) for newly created projects.

XST Command Line

xst run -hierarchy_separator _
Sets the hierarchy separator to “_” (underscore)

ISE® Design Suite

1. Select Process > Process Properties > Synthesis Options.
3. Set the Hierarchy Separator property.
I/O Standard (IOSTANDARD)

The I/O Standard (IOSTANDARD) constraint assigns an I/O standard to an I/O
primitive.
For more information about this constraint, see the Constraints Guide.
Keep (KEEP)
Keep (Keep ) is an advanced mapping constraint.
When a design is mapped, some nets may be absorbed into logic blocks. When a net
is absorbed into a block, it can no longer be seen in the physical design database. This
may happen, for example, if the components connected to each side of a net are mapped
into the same logic block. The net may then be absorbed into the block containing the
components. Keep prevents this from happening.
In addition to true and false values supported by the implementation flow, XST supports
a soft value. If this value is specified XST preserves the designated net as in the case of
the true value, but does not attach the Keep constraint in the final netlist to this net.
Keep preserves the existence of the signal in the final netlist, but not its structure. For
example, if your design has a 2-bit multiplexer selector and you attach Keep to it, this
signal is preserved in the final netlist. But the multiplexer could be automatically
re-encoded by XST using one-hot encoding. As a consequence, this signal in the final
netlist is four bits wide instead of the original two. To preserve the structure of the signal,
in addition to Keep , you must also use Enumerated Encoding (ENUM_ENCODING)’
Keep Hierarchy (KEEP_HIERARCHY)

The Keep Hierarchy (KEEP_HIERARCHY) constraint is a synthesis and implementation
constraint.
If hierarchy is maintained during synthesis, the implementation tools use Keep
Hierarchy to preserve the hierarchy throughout implementation, and allow a simulation
netlist to be created with the desired hierarchy.
XST can flatten the design to obtain better results by optimizing entity or module
boundaries. You can set Keep Hierarchy to true so that the generated netlist is
hierarchical and respects the hierarchy and interface of any entity or module in your
design.
Keep Hierarchy is related to the hierarchical blocks (VHDL entities, Verilog modules)
specified in the Hardware Description Language (HDL) design, and does not concern
the macros inferred by the HDL synthesizer.
In general, a Hardware Description Language (HDL) design is a collection of hierarchical
blocks. Preserving the hierarchy gives the advantage of fast processing because the
optimization is done on separate pieces of reduced complexity. Nevertheless, very
often, merging the hierarchy blocks improves the fitting results (fewer PTerms and
device macrocells, better frequency) because the optimization processes (collapsing,
factorization) are applied globally on the entire logic.

In the following figure, if Keep Hierarchy is set to the entity or module I2, the hierarchy
of I2 is in the final netlist, but its contents I4, I5 are flattened inside I2. I1, I3, I6, and I7
are also flattened.
Keep Hierarchy Diagram
Applicable Elements
Applies to logical blocks, including blocks of hierarchy or symbols.
Propagation Rules
Applies to the entity or module to which it is attached.
Syntax
-keep_hierarchy {yes|no|soft}
• yes
• no
• true
Allows the preservation of the design hierarchy, as described in the HDL project. If
this value is applied to synthesis, it is also propagated to implementation.
The default is true for CPLD devices.
• false
Hierarchical blocks are merged in the top level module.
The default is false for FPGA devices.
• soft
Allows the preservation of the design hierarchy in synthesis, but KEEP_HIERARCHY
is not propagated to implementation.


Schematic Syntax Example

• Attach to the entity or module symbol.
• Attribute Name
KEEP_HIERARCHY
• Attribute Values
See Syntax section above.
VHDL
Declare as follows:
attribute keep_hierarchy : string;
Specify as follows:
attribute keep_hierarchy of architecture_name: architecture is "{yes|no|true|false|soft}";
Verilog
Place immediately before the module declaration or instantiation:
(* keep_hierarchy = "{yes|no|true|false|soft}" *)
XCF
MODEL "entity_name" keep_hierarchy={yes|no|true|false|soft};
XST Command Line

xst run -keep_hierarchy {yes|no|soft}
ISE® Design Suite

Process > Process Properties > Synthesis Options > Keep Hierarchy
Library Search Order (-lso)

The Library Search Order (-lso) command line option specifies the location of the
library search order file.
Library Search Order (LSO) Files in Mixed Language Projects
Applicable Elements
Applies to files.

Propagation Rules
Not applicable.
Syntax
-lso file_name.lso
There is no default file name. If not specified, XST uses the default search order.

XST Command Line

xst elaborate -lso c:/data/my_libraries/my.lso
Specifies c:/data/my_libraries/my.lso as the file that sets your library search
order.
ISE® Design Suite

To specify the library search order file in ISE Design Suite:
3. Set the Library Search Order property.
LOC
The LOC constraint defines where a design element can be placed within an FPGA or
CPLD device.
Netlist Hierarchy (-netlist_hierarchy)

The Netlist Hierarchy (-netlist_hierarchy) command line option:
• Controls the form in which the final NGC netlist is generated.
• Allows you to write the hierarchical netlist even if the optimization was done on a
partially or fully flattened design.
Applies to all FPGA devices. Does not apply to CPLD devices.
Applicable Elements
Propagation Rules
Not applicable.

Syntax
-netlist_hierarchy {as_optimized|rebuilt}
• as_optimized (default)
XST takes into account the Keep Hierarchy (KEEP_HIERARCHY) constraint, and
generates the NGC netlist in the form in which it was optimized. In this mode, some
hierarchical blocks can be flattened, and some can maintain hierarchy boundaries.
• rebuilt
XST writes a hierarchical NGC netlist, regardless of the Keep Hierarchy
(KEEP_HIERARCHY) constraint.

XST Command Line

-netlist_hierarchy {as_optimized|rebuilt}
ISE® Design Suite

3. Set the Netlist Hierarchy property.
Optimization Effort (OPT_LEVEL)

The Optimization Effort (OPT_LEVEL) constraint defines the synthesis optimization
effort level.
Applicable Elements
Applies to the entire design, or to an entity or module.
Propagation Rules
Applies to the entity, component, module, or signal to which it is attached.

Syntax
-opt_level {1|2}
• 1 (normal optimization) (default)
Use 1 (normal optimization) for very fast processing, especially for hierarchical
designs. In speed optimization mode, Xilinx® recommends using 1 (normal
optimization) for the majority of designs.
• 2 (higher optimization)
While 2 (higher optimization) is more time consuming, it sometimes gives better
results in the number of slices/macrocells or maximum frequency. Selecting 2
(higher optimization) usually results in increased synthesis run times, and does not
always bring optimization gain.

VHDL
Declare as follows:
attribute opt_level: string;
Specify as follows:
attribute opt_level of entity_name: entity is "{1|2}";
Verilog
(* opt_level = "{1|2}" *)
XCF
MODEL "entity_name" opt_level={1|2};
XST Command Line

xst run -opt_level {1|2}
ISE® Design Suite

Process > Process Properties > Synthesis Options > Optimization Effort
Optimization Goal (OPT_MODE)

The Optimization Goal (OPT_MODE) constraint defines the synthesis optimization
strategy.
Applicable Elements
Applies to the entire design, or to an entity or module.

Propagation Rules
Syntax
-opt_mode {area|speed}
• speed (default)
The priority of speed is to reduce the number of logic levels and therefore to
increase frequency.
• area
The priority of area is to reduce the total amount of logic used for design
implementation and therefore improve design fitting.

VHDL
Declare as follows:
attribute opt_mode: string;
Specify as follows:
attribute opt_mode of entity_name: entity is "{speed|area}";
Verilog
(* opt_mode = "{speed|area}" *)
XCF
MODEL "entity_name" opt_mode={speed|area};
XST Command Line

xst run -opt_mode {area|speed}
ISE® Design Suite

Process > Process Properties > Synthesis Options > Optimization Goal
Parallel Case (PARALLEL_CASE)

The Parallel Case (PARALLEL_CASE) constraint:
• Forces a case statement to be synthesized as a parallel multiplexer.
• Prevents the case statement from being transformed into a prioritized if...elsif
cascade.
Multiplexers HDL Coding Techniques.

Applicable Elements
Applies to case statements in Verilog meta comments only.
Propagation Rules
Not applicable.
Syntax
-vlgcase {full|parallel|full-parallel}
• full
• parallel
• full-parallel

Verilog
(* parallel_case *)
Since PARALLEL_CASE does not contain a target reference, the attribute immediately
precedes the selector.
(* parallel_case *)
casex select
endcase
PARALLEL_CASE is also available as a meta comment in the Verilog code. The syntax
differs from the standard meta comment syntax as shown in the following:
// synthesis parallel_case
Since PARALLEL_CASE does not contain a target reference, the meta comment
immediately follows the selector:
casex select // synthesis parallel_case
endcase
XST Command Line
xst run -vlgcase {full|parallel|full-parallel}

RLOC (RLOC)
The RLOC (RLOC) constraint:
• Is a basic mapping and placement constraint.
• Groups logic elements into discrete sets.
• Allows you to define the location of any element within the set relative to other
elements in the set, regardless of eventual placement in the overall design.

Verilog
Assuming an SRL16 instance named srl1 to be placed at location R9C0.S0, you may
specify the following in the Verilog code:
// synthesis attribute RLOC of srl1 : "R9C0.S0";
XCF
You may specify the same attribute in the XST Constraint File (XCF) as follows:
BEGIN MODEL ENTNAME
INST sr11 RLOC=R9C0.SO;
END;
The binary equivalent of the following line is written to the output NGC file:
INST srl1 RLOC=R9C0.S0;
Save (S)
The Save (S) constraint is an advanced mapping constraint.
When the design is mapped, some nets may be absorbed into logic blocks, and some
elements such as LUTs can be optimized away. When a net is absorbed into a block, or a
block is optimized away, it can no longer be seen in the physical design database. Save
(S) prevents this from happening. Several optimization techniques such as nets or blocks
replication and register balancing are also disabled by the Save (S) constraint.
If Save (S) is applied to a net, XST preserves the net with all elements directly connected
to it in the final netlist. This includes nets connected to these elements.
If Save (S) is applied to a block such as a LUT, XST preserves the LUT with all signals
connected to it.

Synthesis Constraint File (-uc)

The Synthesis Constraint File (-uc) command line option specifies the synthesis
constraint file for XST to use.
The XST Constraint File (XCF) has an extension of .xcf. If the extension is not .xcf,
XST errors out and stops processing.
XST Constraint File (XCF)
Applicable Elements
Applies to files.
Propagation Rules
Not applicable.
Syntax
-uc filename
filename is the only value.

XST Command Line

xst run -uc my_constraints.xcf
Specifies my_constraints.xcf as the constraint file for this project.
ISE® Design Suite

Process > Process Properties > Synthesis Options > Synthesis Constraint File

Translate Off (TRANSLATE_OFF) and Translate On

(TRANSLATE_ON)
The Translate Off (TRANSLATE_OFF) and Translate On (TRANSLATE_ON)
constraints:
• Instruct XST to ignore portions of VHDL or Verilog code that are not relevant for
synthesis, such as simulation code.
• Are Synopsys directives that XST supports in Verilog. Automatic conversion is also
available in VHDL and Verilog
• Can be used with the following words
– synthesis
– Synopsys
– pragma
• Operate as follows:
– TRANSLATE_OFF marks the beginning of the section to be ignored.
– TRANSLATE_ON instructs XST to resume synthesis from that point.
Applicable Elements
Applies locally.
Propagation Rules
Instructs the synthesis tool to enable or disable portions of code
Syntax
The following sections show the syntax for this constraint.

VHDL
-- synthesis translate_off
...code not synthesized...
-- synthesis translate_on
Verilog
The Verilog syntax differs from the standard meta comment syntax presented earlier, as
shown in the following coding example.
// synthesis translate_off
...code not synthesized...
// synthesis translate_on

Ignore Synthesis Constraints File (–iuc)

Use the Ignore Synthesis Constraints File (–iuc) command line option to ignore the
constraint file specified with Synthesis Constraints File (-uc) during synthesis.
Applicable Elements
Applies to files.
Propagation Rules
Not applicable.
Syntax
-iuc {yes|no}
• yes
• no (default)

XST Command Line

xst run -iuc yes
ISE Design Suite

Caution! Ignore Synthesis Constraints File is shown as Synthesis Constraints File in
ISE® Design Suite. The constraint file is ignored if you uncheck this option. It is checked
by default (therefore resulting in a –iuc no command line switch), meaning that any
synthesis constraints file you specify is taken into account.
Process > Process Properties > Synthesis Options > Use Synthesis Constraints File
Verilog 2001 (-verilog2001)

The Verilog 2001 (-verilog2001) command line option enables or disables interpreting
Verilog source code by the Verilog 2001 standard.
By default Verilog source code is interpreted as the Verilog 2001 standard.

Applicable Elements
Applies to syntax.
Propagation Rules
Not applicable.
Syntax
-verilog2001 {yes|no}
• yes (default)
• no

XST Command Line

xst elaborate -verilog2001 no
XST does not interpret Verilog code according to the Verilog 2001 standard.
ISE® Design Suite

Process > Process Properties > Synthesis Options > Verilog 2001
Verilog Include Directories (-vlgincdir)

The Verilog Include Directories (-vlgincdir) command line option helps the parser find
files referenced by ‘include statements.
When an ‘include statement references a file, XST looks in different areas in this order:
• Relative to the current directory.
• Relative to the inc directories.
• Relative to the current file.
Note Verilog Include Directories should be used with ‘include
Applicable Elements
Applies to directories.
Propagation Rules
Not applicable.

Syntax
-vlgincdir { directory_path [directory_path]}
where
directory_path is the name of a directory
Names With Spaces in Command Line Mode.

XST Command Line

xst elaborate -vlgincdir c:/my_verilog
Adds c:/my_verilog to the list of directories in which XST looks for a file.
ISE® Design Suite

Process > Process Properties > Synthesis Options > Property display level > Advanced
> Verilog Include Directories
Verilog Macros (-define)

The Verilog Macros (-define) command line option:
• Allows you to define (or redefine) Verilog macros.
This allows you to easily modify the design configuration without modifying source
code, such as for IP core generation and testing flows. If the defined macro is not used in
the design, no message is given.
Applicable Elements
Propagation Rules
Not applicable.
Syntax
-define {name[=value] name[=value]}
where
• name is a macro name
• value is the macro text

The default is an empty definition.

Note
• Values for macros are not mandatory.
• Place the values inside curly braces ({...}).
• Separate the values with spaces.
• Macro text can be specified between quotation marks ("..."), or without them. If the
macro text contains spaces, you must use quotation marks ("...").
-define {macro1=Xilinx macro2="Xilinx Virtex4"}

XST Command Line

xst run -define macro1=Xilinx macro2="Xilinx Virtex4"
Defines two macros named macro1 and macro2.
ISE Design Suite

To define Verilog macros in ISE® Design Suite:
2. From the Property display level list, select Advanced.
3. Set the Verilog Macros property.
Do not use curly braces ({...}) when specifying values in ISE Design Suite.
Work Directory (-xsthdpdir)

Work Directory (-xsthdpdir) defines the location in which VHDL-compiled files must be
placed if the location is not defined by library mapping files.
To access Work Directory:
• In ISE® Design Suite, select:
Process > Process Properties > Synthesis Options > VHDL Working Directory
• In standalone mode, run the following command:
set -xsthdpdir directory
Assume for purposes of this example:
• Three different users are working on the same project.
• They share one standard, precompiled library, shlib.
• This library contains specific macro blocks for their project.
• Each user also maintains a local work library.
• User 3 places her local work library outside the project directory (for example, in
c:\temp).
• Users 1 and 2 share another library (lib12) between them, but not with User 3.
The settings required for the three users are as follows:

Example User One

Mapping file
schlib=z:\sharedlibs\shlib lib12=z:\userlibs\lib12
Example User Two

Mapping file
schlib=z:\sharedlibs\shlib lib12=z:\userlibs\lib12
Example User Three

Mapping file
schlib=z:\sharedlibs\shlib
User Three will also set:
XSTHDPDIR = c:\temp
Applicable Elements
Applies to directories.
Propagation Rules
Not applicable.

XST Command Line

Define Work Directory globally with set -xsthdpdirbefore running the run command:
set -xsthdpdir directory
Work Directory can accept a single path only. You must specify the directory. There
is no default.
ISE Design Suite

Process > Process Properties > Synthesis Options > VHDL Work Directory
To view Work Directory, select:
Edit > Preferences > Processes > Property Display Level > Advanced

Chapter 8
XST HDL Constraints

The following HDL constraints can be set globally in ISE® Design Suite in Process >
Process Properties > HDL Options:
• Automatic FSM Extraction (FSM_EXTRACT)
The following HDL constraints cannot be set in Process > Process Properties:
• Safe Recovery State (SAFE_RECOVERY_STATE)
• Signal Encoding (SIGNAL_ENCODING)

Chapter 8: XST HDL Constraints
Automatic FSM Extraction (FSM_EXTRACT)

The Automatic FSM Extraction (FSM_EXTRACT) constraint:
• Enables or disables Finite State Machine (FSM) extraction and specific synthesis
optimizations.
• Must be enabled in order to set values for FSM Encoding Algorithm
(FSM_ENCODING).
Applicable Elements
Applies to the entire design, or to an entity, component, module, or signal.
Propagation Rules
Syntax
-fsm_extract {yes|no}
• yes (default)
• no
• true (XCF only)
• false (XCF only)

VHDL
Declare as follows:
attribute fsm_extract: string;
Specify as follows:
attribute fsm_extract of {entity_name|signal_name} : {entity|signal} is "{yes|no}";
Verilog
Place immediately before the module or signal declaration:
(* fsm_extract = "{yes|no}" *)

MODEL "entity_name"fsm_extract={yes|no|true|false};


BEGIN MODEL "entity_name"
NET "signal_name "fsm_extract={yes|no|true|false};
END;
XST Command Line

xst run -fsm_extract {yes|no}
ISE® Design Suite

Process > Process Properties > HDL Options > FSM Encoding Algorithm
This option defines both –fsm_extract and FSM Style (FSM_STYLE).
• When FSM Encoding Algorithm (FSM_ENCODING) is set to none:
– -fsm_extract is set to no
– -fsm_encoding is irrelevant and is left unspecified
• When FSM Encoding Algorithm (FSM_ENCODING) is set to any other value:
– -fsm_extract is set to yes
– -fsm_encoding is set to the selected value
For more information about -fsm_encoding, see :

FSM Encoding Algorithm (FSM_ENCODING)
Enumerated Encoding (ENUM_ENCODING)

The Enumerated Encoding (ENUM_ENCODING) constraint:
• Applies a specific encoding to a VHDL enumerated type. The value is a string
containing space-separated binary codes.
• Can be specified only as a VHDL constraint on the considered enumerated type.
When describing a Finite State Machine (FSM) using an enumerated type for the state
register, you may specify a particular encoding scheme with ENUM_ENCODING.
In order for this encoding to be used by XST, set FSM Encoding Algorithm
(FSM_ENCODING) to user for the considered state register.
Applicable Elements
Applies to signals or types.
Because ENUM_ENCODING must preserve the external design interface, XST ignores
ENUM_ENCODING when it is used on a port.
Propagation Rules
Applies to the signal or type to which it is attached.

Syntax

VHDL
Specify as a VHDL constraint on the considered enumerated type:
...
...
architecture behavior of example is
type statetype is (ST0, ST1, ST2, ST3);
attribute enum_encoding : string;
attribute enum_encoding of statetype : type is "001 010 100 111";
signal state1 : statetype;
signal state2 : statetype;
begin
...
XCF
NET "signal_name" enum_encoding="string";
END;
Equivalent Register Removal

(EQUIVALENT_REGISTER_REMOVAL)
The Equivalent Register Removal (EQUIVALENT_REGISTER_REMOVAL) constraint
enables or disables removal of equivalent registers described at the RTL Level.
By default, XST does not remove equivalent flip-flops if they are instantiated from a
Xilinx® primitive library.
Flip-flop optimization includes removing:
• Equivalent flip-flops for FPGA and CPLD devices
• Flip-flops with constant inputs for CPLD devices
This processing increases the fitting success as a result of the logic simplification implied
by the flip-flops elimination.
Applicable Elements

Propagation Rules
Removes equivalent flip-flops and flip-flops with constant inputs.
Syntax
-equivalent_register_removal {yes|no}
• yes (default)
• no
• true (XCF only)
When the value is set to yes, flip-flop optimization is allowed.
When the value is set to no, flip-flop optimization is inhibited.
Tip The flip-flop optimization algorithm is time consuming. For fast processing, use no.

VHDL
Declare as follows:
attribute equivalent_register_removal: string;
Specify as follows:
attribute equivalent_register_removal of {entity_name|signal_name} : {signal|entity}
is "{yes |no}";
Verilog
(* equivalent_register_removal="{yes|no}" *)

MODEL "entity_name" equivalent_register_removal= {yes|no|true|false};

BEGIN MODEL " entity_name"
NET "signal_name" equivalent_register_removal= {yes|no|true|false};
END;
XST Command Line

xst run -equivalent_register_removal {yes|no}
ISE® Design Suite

Process > Process Properties > Xilinx®Specific Options > Equivalent Register Removal

FSM Encoding Algorithm (FSM_ENCODING)

The FSM Encoding Algorithm (FSM_ENCODING) constraint selects the Finite State
Machine (FSM) coding technique.
In order to select a value for the FSM Encoding Algorithm, Automatic FSM Extraction
(FSM_EXTRACT) must be enabled.
Applicable Elements
Propagation Rules
Syntax
-fsm_encoding {auto|one-hot|compact|sequential|gray|johnson|speed1|user}
• auto (default)
The best coding technique is automatically selected for each individual state
machine.
• one-hot
• compact
• sequential
• gray
• johnson
• speed1
• user

VHDL
Declare as follows:
attribute fsm_encoding: string;
Specify as follows:
attribute fsm_encoding of {entity_name|signal_name}: {entity|signal} is
"{auto|one-hot|compact|sequential|gray|johnson|speed1|user}";
Verilog
(* fsm_encoding = "{auto|one-hot|compact|sequential|gray|johnson|speed1|user}"
*)


MODEL "entity_name"
fsm_encoding={auto|one-hot|compact|sequential|gray|johnson|speed1|user} ;

NET "signal_name" fsm_encoding={auto
|one-hot|compact|sequential|gray|johnson|speed1|user };
END;
XST Command Line

run xst -fsm_encoding
{auto|one-hot|compact|sequential|gray|johnson|speed1|user}
ISE® Design Suite

Process > Process Properties > HDL Options > FSM Encoding Algorithm
These options are:
• If the FSM Encoding Algorithm menu is set to none, and -fsm_extract is set to no,
-fsm_encoding has no influence on the synthesis.
• In all other cases, -fsm_extract is set to yes and -fsm_encoding is set to the value
selected in the menu.
Automatic FSM Extraction (FSM_EXTRACT)
Mux Extraction (MUX_EXTRACT)

The Mux Extraction (MUX_EXTRACT) constraint enables or disables multiplexer macro
inference.
Applicable Elements
Propagation Rules

Syntax
-mux_extract {yes|no|force}
• yes (default)
• no
• force
• true (XCF only)
By default, multiplexer inference is enabled with the yes option. For each identified
multiplexer description, based on some internal decision rules, XST actually creates a
macro or optimizes it with the rest of the logic. The force value overrides those decision
rules, and forces XST to create the MUX macro.

VHDL
Declare as follows:
attribute mux_extract: string;
Specify as follows:
attribute mux_extract of {signal_name|entity_name}: {entity|signal} is "{yes|no|force}";
Verilog
(* mux_extract = "{yes|no|force}" *)

MODEL "entity_name" mux_extract={yes|no|true|false|force};

NET "signal_name" mux_extract={yes|no|true|false|force};
END;
XST Command Line

xst run -mux_extract {yes|no|force}
ISE® Design Suite

Process > Process Properties > HDL Options
Resource Sharing (RESOURCE_SHARING)

The Resource Sharing (RESOURCE_SHARING) constraint enables or disables resource
sharing of arithmetic operators.

Applicable Elements
Applies to the entire design, or to design elements.
Propagation Rules
Syntax
-resource_sharing {yes|no}
• yes (default)
• no
• force
• true (XCF only)

VHDL
Declare as follows:
attribute resource_sharing: string;
Specify as follows:
attribute resource_sharing of entity_name: entity is "{yes|no}";
Verilog
(* resource_sharing = "{yes|no}" *)

MODEL "entity_name" resource_sharing={yes|no|true|false};

NET "signal_name" resource_sharing={yes|no|true|false};
END;
XST Command Line

xst run -resource_sharing {yes|no}

ISE® Design Suite

HDL Options > Resource Sharing
Safe Implementation (SAFE_IMPLEMENTATION)

The Safe Implementation (SAFE_IMPLEMENTATION) constraint implements Finite
State Machine (FSM) components in Safe Implementation mode.
In Safe Implementation mode, XST generates additional logic that forces an FSM
to a valid state (recovery state) if the FSM enters an invalid state. By default, XST
automatically selects reset as the recovery state. If the FSM does not have an initialization
signal, XST selects power-up as the recovery state.
Define the recovery state manually with Safe Recovery State (SAFE_RECOVERY_STATE).
Applicable Elements
Applies to:
• An entire design through the XST command line
• A particular block (entity, architecture, component)
• A signal
Propagation Rules
Syntax
-safe_implementation {yes|no}
• yes
• no (default)

VHDL
Declare as follows:
attribute safe_implementation: string;
Specify as follows:
attribute safe_implementation of {entity_name|component_name|signal_name} :
{entity|component|signal} is "{yes|no}";
Verilog
(* safe_implementation = "{yes|no}" *)


MODEL "entity_name" safe_implementation={yes|no|true|false};

NET "signal_name" safe_implementation={yes|no|true|false};
END;
XST Command Line

xst run -safe_implementation {yes|no}
ISE® Design Suite

To activate Safe Implementation in:
• ISE Design Suite
Select Process > Process Properties > HDL Options > Safe Implementation
• Hardware Description Language (HDL)
Apply Safe Implementation to the hierarchical block or signal that represents the
state register in the FSM.
Signal Encoding (SIGNAL_ENCODING)

The Signal Encoding (SIGNAL_ENCODING) constraint selects the coding technique to
use for internal signals.
Applicable Elements
Propagation Rules
Syntax
-signal_encoding {auto|one-hot|user}
• auto (default)
The best coding technique is automatically selected for each individual signal.
• one-hot
Forces the encoding to a one-hot encoding.
• user
Forces XST to keep your encoding.


VHDL
Declare as follows:
attribute signal_encoding: string;
Specify as follows:
attribute signal_encoding of {component_name|signal_name|entity_name|label_name} :
{component|signal|entity|label} is "{auto|one-hot|user}";
Verilog
Place immediately before the signal declaration:
(* signal_encoding = "{auto|one-hot|user}" *)

MODEL "entity_name" signal_encoding = {auto|one-hot|user};

NET "signal_name" signal_encoding = {auto|one-hot|user};
END;
XST Command Line

xst run -signal_encoding {auto|one-hot|user}
Safe Recovery State (SAFE_RECOVERY_STATE)

The Safe Recovery State (SAFE_RECOVERY_STATE) constraint defines a recovery state
for use when a Finite State Machine (FSM) is implemented in Safe Implementation mode.
If the FSM enters an invalid state, XST uses additional logic to force the FSM to a
valid recovery state. By implementing FSM in safe mode, XST collects all code not
participating in the normal FSM behavior and treats it as illegal.
XST uses logic that returns the FSM synchronously to the:
• Known state
• Reset state
• Power up state
• State you specified using Safe Recovery State
Safe Implementation (SAFE_IMPLEMENTATION)

Applicable Elements
Applies to a signal representing a state register.
Propagation Rules
Applies to the signal to which it is attached.
Syntax

VHDL
Declare as follows:
attribute safe_recovery_state: string;
Specify as follows:
attribute safe_recovery_state of {signal_name}:signal is "<value>";
Verilog
(* safe_recovery_state = "<value>" *)
XCF
NET "signal_name" safe_recovery_state="<value>";
END;

Chapter 9
XST FPGA Constraints (Non-Timing)

Important! The constraints described in this chapter apply to FPGA devices only. They
do not apply to CPLD devices.
• Asynchronous to Synchronous (ASYNC_TO_SYNC)
• Buffer Type (BUFFER_TYPE)
• Convert Tristates to Logic (TRISTATE2LOGIC)
• Extract BUFGCE (BUFGCE)
• LUT Combining (LC)
• Power Reduction (POWER)
• Read Cores (READ_CORES)
• Map Entity on a Single LUT (LUT_MAP)
• Map Logic on BRAM (BRAM_MAP)
• Number of Regional Clock Buffers (-bufr)
• Reduce Control Sets (REDUCE_CONTROL_SETS)

Chapter 9: XST FPGA Constraints (Non-Timing)

• Shift Register Extraction (SHREG_EXTRACT)
• Slice Packing (-slice_packing)
• Slice (LUT-FF Pairs) Utilization Ratio (SLICE_UTILIZATION_RATIO)
• Slice (LUT-FF Pairs) Utilization Ratio Delta
(SLICE_UTILIZATION_RATIO_MAXMARGIN)
• Use Carry Chain (USE_CARRY_CHAIN)
• Use Clock Enable (USE_CLOCK_ENABLE)
• Use Synchronous Set (USE_SYNC_SET)
• Use Synchronous Reset (USE_SYNC_RESET)
Some constraints can be applied:
• globally to an entire entity or model, OR
• locally to individual signals, nets or instances
For valid constraint targets, see:
• XST Specific Non-Timing Options Supported Only in the Command Line

Asynchronous to Synchronous (ASYNC_TO_SYNC)

The Asynchronous to Synchronous (ASYNC_TO_SYNC) constraint:
• Allows you to replace Asynchronous Set/Reset signals with Synchronous signals
throughout the entire design.
• Allows absorption of registers by DSP48 and BRAMs, thereby improving quality
of results.
• May have a positive impact on power optimization.
Although XST can place Finite State Machine (FSM) components on BRAMs, in most
cases an FSM has an Asynchronous Set/Reset signal, which does not allow FSM
implementation on BRAMs. ASYNC_TO_SYNC allows you to more easily place FSMs
on BRAMs by eliminating the need to manually change the design.
Replacing Asynchronous Set/Reset signals by Synchronous signals makes the generated
NGC netlist NOT equivalent to the initial RTL description. You must ensure that the
synthesized design satisfies the initial specification. XST issues the following warning:
WARNING: You have requested that asynchronous control signals
of sequential elements be treated as if they were synchronous.
If you haven’t done so yet, please carefully review the related
documentation material. If you have opted to asynchronously
control flip-flop initialization, this feature allows you
to better explore the possibilities offered by the Xilinx
solution without having to go through a painful rewriting
effort. However, be well aware that the synthesis result, while
providing you with a good way to assess final device usage and
design performance, is not functionally equivalent to your HDL
description. As a result, you will not be able to validate
your design by comparison of pre-synthesis and post-synthesis
simulation results. Please also note that in general we strongly
recommend synchronous flip-flop initialization.
Applicable Elements
Propagation Rules
Not applicable.
Syntax
-async_to_sync {yes|no}
• yes
• no (default)


XST Command Line

xst run -async_to_sync yes
ISE® Design Suite

Process > Process Properties > HDL Options > Asynchronous to Synchronous
Automatic BRAM Packing (AUTO_BRAM_PACKING)

The Automatic BRAM Packing (AUTO_BRAM_PACKING) constraint allows you to
pack two small BRAMs in a single BRAM primitive as dual-port BRAM.
XST packs BRAMs together only if they are situated in the same hierarchical level.
Applicable Elements
Propagation Rules
Not applicable.
Syntax
-auto_bram_packing {yes|no}
• yes
• no (default)

XST Command Line

xst run -auto_bram_packing no
ISE® Design Suite

Process > Process Properties > Automatic BRAM Packing
BRAM Utilization Ratio (BRAM_UTILIZATION_RATIO)

The BRAM Utilization Ratio (BRAM_UTILIZATION_RATIO) constraint defines the
number of BRAM blocks that XST must not exceed during synthesis.
BRAMs in the design may come not only from BRAM inference processes, but from
instantiation and BRAM mapping optimizations. You may isolate an RTL description of
logic in a separate block, and then ask XST to map this logic to BRAM.


Instantiated BRAMs are the primary candidates for available BRAM resources. The
inferred RAMs are placed on the remaining BRAM resources. However, if the number
of instantiated BRAMs exceeds the number of available resources, XST does not modify
the instantiations and implement them as block RAMs. The same behavior occurs if
you force specific RAMs to be implemented as BRAMs. If there are no resources, XST
respects user constraints, even if the number of BRAM resources is exceeded.
If the number of user-specified BRAMs exceeds the number of available BRAM
resources on the target FPGA device, XST issues a warning, and uses only available
BRAM resources on the chip for synthesis. However, you may disable automatic BRAM
resource management by using value -1. This can be used to see the number of BRAMs
XST can potentially infer for a specific design.
You may experience significant synthesis time if the number of BRAMs in the design
significantly exceeds the number of available BRAMs on the target FPGA device
(hundreds of BRAMs). This may happen due to a significant increase in design
complexity when all non-fittable BRAMs are converted to distributed RAMs.
Applicable Elements
Propagation Rules
Not applicable.
Syntax
• %
• #

XST Command Line

xst run -bram_utilization_ratio<integer>[%][#]
where
<integer> range is [-1 to 100] when % is used or both % and # are omitted
The default is 100.
XST Command Line Syntax Example One

xst run -bram_utilization_ratio 50
where
50 means 50% of BRAM blocks in the target device

XST Command Line Syntax Example Two

xst run -bram_utilization_ratio 50%
where
50% means 50% of BRAM blocks in the target device
XST Command Line Syntax Example Three

xst run -bram_utilization_ratio 50#
where
50# means 50 BRAM blocks
There must be no space between the integer value and the percent (%) or pound (#)
characters.
In some situations, you can disable automatic BRAM resource management (for example,
to see how many BRAMs XST can potentially infer for a specific design). To disable
automatic resource management, specify -1 (or any negative value) as a constraint value.
ISE® Design Suite

Process > Process Properties > Synthesis Options > BRAM Utilization Ratio
In ISE Design Suite, you can define the value of BRAM Utilization Ratio only as a
percentage. The definition of the value in the form of absolute number of BRAMs is
not supported.
Buffer Type (BUFFER_TYPE)

The Buffer Type (BUFFER_TYPE) constraint selects the type of buffer to be inserted
on the input port or internal net.
XST supports the bufr value for Virtex®-4 devices and Virtex-5 devices only.
Applicable Elements
Applies to signals.
Propagation Rules
Syntax
• bufgdll
• ibufg
• bufgp
• ibuf
• bufr
• none


VHDL
Declare as follows:
attribute buffer_type: string;
Specify as follows:
attribute buffer_type of signal_name: signal is "
{bufgdll|ibufg|bufgp|ibuf|bufr|none}";
Verilog
(* buffer_type = "{bufgdll|ibufg|bufgp|ibuf|bufr|none}" *)
XCF
NET "signal_name" buffer_type={bufgdll|ibufg|bufgp|ibuf|bufr|none};
END;
Convert Tristates to Logic (TRISTATE2LOGIC)

Since some devices do not support internal tristates, XST automatically replaces tristates
with equivalent logic. Because the logic generated from tristates can be combined and
optimized with surrounding logic, tristate to logic replacement for other devices can
lead to better speed, and in some cases, better area optimization. But in general tristate
to logic replacement may lead to area increase. If the optimization goal is Area, you
should apply Convert Tristates to Logic set to no.

Limitations to Convert Tristates to Logic

Following are limitations to Convert Tristates to Logic:
• Only internal tristates are replaced by logic. The tristates of the top module
connected to output pads are preserved.
• Convert Tristates to Logic does not apply to technologies that do not have internal
tristates, such as Spartan®-3 devices or Virtex®-4 devices. In this case, the
conversion of tristates to logic is performed automatically. In some situations XST
is unable to make the replacement automatically, due to the fact that this may lead
to wrong design behavior or multi-source. This may happen when the hierarchy
is preserved or XST does not have full design visibility (for example, design is
synthesized on a block-by-block basis). In these cases, XST issues a warning at the
low level optimization step. Depending on the particular design situation, you
may continue the design flow and the replacement could be done by MAP, or you
can force the replacement by applying Convert Tristates to Logic set to yes on a
particular block or signal.
• The situations in which XST is unable to replace a tristate by logic are:
– The tristate is connected to a black box.
– The tristate is connected to the output of a block, and the hierarchy of the block
is preserved.
– The tristate is connected to a top-level output.
– Convert Tristates to Logic is set to no on the block where tristates are placed,
or on the signals to which tristates are connected.
Applicable Elements
Applies to:
• A signal
Propagation Rules
Syntax
-tristate2logic {yes|no}
• yes (default)
• no
• true (XCF only)


VHDL
Declare as follows:
attribute tristate2logic: string;
Specify as follows:
attribute tristate2logic of {entity_name|component_name|signal_name} :
{entity|component|signal} is "{yes|no}";
Verilog
(* tristate2logic = "{yes|no}" *)

MODEL "entity_name" tristate2logic={yes|no|true|false};

NET "signal_name" tristate2logic={yes|no|true|false};
END;
XST Command Line

xst run -tristate2logic {yes|no}
ISE® Design Suite

Process > Process Properties > Xilinx® Specific Options > Convert Tristates to Logic
Cores Search Directories (-sd)

The Cores Search Directories (-sd) command line option tells XST to look for cores in
directories other than the default.
By default XST searches for cores in the directory specified in the -ifn option.
Applicable Elements
Propagation Rules
Not applicable.
Syntax
-sd {directory_path [directory_path]]
The only value is directory_path. There is no default.


XST Command Line

xst run -sd c:/data/cores c:/ise/cores
Tells XST to search for cores in c:/data/cores and c:/ise/cores in addition to
the default directory.
Names With Spaces in Command Line Mode
ISE® Design Suite

Process > Process Properties > Synthesis Options > Cores Search Directory
Decoder Extraction (DECODER_EXTRACT)

The Decoder Extraction (DECODER_EXTRACT) constraint enables or disables decoder
macro inference.
Applicable Elements
Propagation Rules
When attached to a net or signal, Decoder Extraction applies to the attached signal.
When attached to an entity or module, Decoder Extraction is propagated to all applicable
elements in the hierarchy within the entity or module.
Syntax
-decoder_extract {yes|no}
• yes (default)
• no

VHDL
Declare as follows:

attribute decoder_extract: string;

Specify as follows:
attribute decoder_extract of {entity_name|signal_name} : {entity|signal} is "{yes|no}";
Verilog
(* decoder_extract "{yes|no}" *)

MODEL "entity_name" decoder_extract={yes|no|true|false};

NET "signal_name" decoder_extract={yes|no|true|false};
END;
XST Command Line

xst run -decoder_extract {yes|no}
ISE® Design Suite

Process > Process Properties > HDL Options > Decoder Extraction
DSP Utilization Ratio (DSP_UTILIZATION_RATIO)

The DSP Utilization Ratio (DSP_UTILIZATION_RATIO) constraint defines the number
of DSP slices (in absolute number or percent of slices) that XST must not exceed during
synthesis optimization.
The default is 100% of the target device.
DSP slices in the design may come not only from DSP inference processes, but also
from instantiation. Instantiated DSP slices are the primary candidates for available DSP
resources. The inferred DSPs are placed on the remaining DSP resources. If the number
of instantiated DSPs exceeds the number of available resources, XST does not modify the
instantiations and implement them as block DSP slices. The same behavior occurs if you
force specific macro implementation to be implemented as DSP slices by using the Use
DSP48 (USE_DSP48) constraint. If there are no resources, XST respects user constraints
even if the number of DSP slices is exceeded.
If the number of user-specified DSP slices exceeds the number of available DSP resources
on the target FPGA device, XST issues a warning, and uses only available DSP resources
on the chip for synthesis.
You can disable automatic DSP resource management (for example, to see how many
DSPs XST can potentially infer for a specific design) by specifying -1 (or any negative
value) as a constraint value.

Applies to the following devices only. Does not apply to any other devices.
• Virtex®-4
• Virtex-5
• Spartan®-3A DSP
Applicable Elements
Propagation Rules
Not applicable.
Syntax

XST Command Line

-dsp_utilization_ratio integer[%|#]
where
integer is [-1 to 100] when
– % is used, or
– both % and # are omitted
To specify a percent of total slices use %. To specify an absolute number of slices use #
The default is %.
For example:
• To specify 50% of DSP blocks of the target device enter :
-dsp_utilization_ratio 50
• To specify 50% of DSP blocks of the target device enter:
-dsp_utilization_ratio 50%
• To specify 50 DSP blocks enter:
-dsp_utilization_ratio 50#
Note There must be no space between the integer value and the percent (%) or pound
(#) characters.
ISE® Design Suite

Process > Process Properties > Synthesis Options > DSP Utilization Ratio
In ISE Design Suite, you can define the value of DSP Utilization Ratio only as a
percentage. You can not define the value as an absolute number of slices.

Extract BUFGCE (BUFGCE)

The Extract BUFGCE (BUFGCE) constraint:
• Implements BUFGMUX functionality by inferring a BUFGMUX primitive.
This operation reduces the wiring. Clock and clock enable signals are driven to n
sequential components by a single wire.
• Must be attached to the primary clock signal.
• Is accessible through Hardware Description Language (HDL) code.
If bufgce=yes, XST implements BUFGMUX functionality if possible. All flip-flops
must have the same clock enable signal.
Applicable Elements
Applies to clock signals.
Propagation Rules
Syntax
• yes
• no

VHDL Syntax Example

Declare as follows:
attribute bufgce : string;
Specify as follows:
attribute bufgce of signal_name: signal is "{yes|no}";
Verilog
(* bufgce = "{yes|no}" *)
XCF
NET "primary_clock_signal" bufgce={yes|no|true|false};
END;

FSM Style (FSM_STYLE)

The FSM Style (FSM_STYLE) constraint:
• Is both a global and a local constraint.
• Can make large Finite State Machine (FSM) components more compact and faster
by implementing them in the block RAM resources provided in Virtex® devices
and later.
• Can be used to direct XST to use block RAM resources rather than LUTs (default) to
implement FSMs.
Applicable Elements
Propagation Rules
Syntax
• lut (default)
• bram

VHDL
Declare as follows:
attribute fsm_style: string;
Declare as follows:
attribute fsm_style of {entity_name|signal_name} : {entity|signal} is "{lut|bram}";
Verilog
(* fsm_style = "{lut|bram}" *)

MODEL "entity_name" fsm_style = {lut|bram};

BEGIN MODEL "entity_name”
NET "signal_name" fsm_style = {lut|bram};
END;

XCF Syntax Example Three

INST "instance_name" fsm_style = {lut|bram};
END;
ISE® Design Suite

Process > Process Properties > Synthesis Options > FSM Style
Logical Shifter Extraction (SHIFT_EXTRACT)

The Logical Shifter Extraction (SHIFT_EXTRACT) constraint enables or disables logical
shifter macro inference.
Applicable Elements
Applies to the entire design, or to design elements and nets.
Propagation Rules
Syntax
-shift_extract {yes|no}
• yes (default)
• no
• true (XCF only)

VHDL
Declare as follows:
attribute shift_extract: string;
Specify as follows:
attribute shift_extract of {entity_name|signal_name}: {signal|entity} is "{yes|no}";
Verilog
(* shift_extract = "{yes|no}" *)


MODEL "entity_name" shift_extract={yes|no|true|false};

NET "signal_name" shift_extract={yes|no|true|false};
END;
XST Command Line

xst run -shift_extract {yes|no}
ISE® Design Suite

Process > Process Properties > HDL Options > Logical Shifter Extraction
LUT Combining (LC)

The LUT Combining (LC) constraint enables the merging of LUT pairs with common
inputs into single dual-output LUT6s in order to improve design area. This optimization
process may reduce design speed.
Applies to Virtex®-5 devices only. Does not apply to any other devices.
Applicable Elements
Propagation Rules
Not applicable.
Syntax
-lc {auto|area|off}
• auto
XST tries to make a trade-off between area and speed.
• area
XST performs maximum LUT combining to provide as small an implementation as
possible.
• off (default)
Disables LUT Combining.


XST Command Line

xst run -lc {auto|area|off}
ISE® Design Suite

Process > Process Properties > Xilinx® Specific Options > LUT Combining
Map Entity on a Single LUT (LUT_MAP)

The Map Entity on a Single LUT (LUT_MAP) constraint forces XST to map a single block
into a single LUT. If a described function on an RTL level description does not fit in a
single LUT, XST issues an error message.
Use the UNISIM library to directly instantiate LUT components in your Hardware
Description Language (HDL) code. To specify a function that a particular LUT must
execute, apply an INIT constraint to the instance of the LUT. To place an instantiated
LUT or register in a particular slice, attach an RLOC constraint to the same instance.
It is not always convenient to calculate INIT functions and different methods can be
used to achieve this. Instead, you can describe the function that you want to map onto a
single LUT in your VHDL or Verilog code in a separate block. Attaching a LUT_MAP
constraint to this block indicates to XST that this block must be mapped on a single
LUT. XST automatically calculates the INIT value for the LUT and preserves this LUT
during optimization.
XST automatically recognizes the XC_MAP constraint supported by Synopsys.
Applicable Elements
Applies to a VHDL entity or Verilog module.
Propagation Rules
Syntax
• yes (default)
• no
• true (XCF only)

VHDL
Declare as follows:

attribute lut_map: string;

Specify as follows:
attribute lut_map of entity_name : entity is "{yes|no}";
Verilog
(* lut_map = "{yes|no}" *)
XCF
MODEL "entity_name" lut_map={yes|no|true|false};
Map Logic on BRAM (BRAM_MAP)

The Map Logic on BRAM (BRAM_MAP) constraint:
• Is used to map an entire hierarchical block on the block RAM resources available in
Virtex® devices and later technologies.
Applicable Elements
BRAMs.
Propagation Rules
Isolate the logic (including output register) to be mapped on RAM in a separate
hierarchical level. Logic that does not fit on a single block RAM is not mapped. Ensure
that the whole entity fits, not just part of it.
The attribute BRAM_MAP is set on the instance or entity. If no block RAM can be
inferred, the logic is passed to Global Optimization, where it is optimized. The macros
are not inferred. Be sure that XST has mapped the logic.
Syntax
• yes
• no (default)


VHDL
Declare as follows:
attribute bram_map: string;
Specify as follows:
attribute bram_map of component_name: component is "{yes|no}";
Verilog
(* bram_map = "{yes|no}" *)

MODEL "entity_name" bram_map = {yes|no|true|false};

INST "instance_name" bram_map = {yes|no|true|false};
END;
Max Fanout (MAX_FANOUT)

The Max Fanout (MAX_FANOUT) constraint:
• Limits the fanout of nets or signals.
Large fanouts can cause routability problems. See Constraint Values below. XST tries to
limit fanout by duplicating gates or by inserting buffers. This limit is not a technology
limit, but only a guide to XST. This limit may not be precisely respected, especially when
the limit is small (less than 30).
In most cases, fanout control is performed by duplicating the gate driving the net with a
large fanout. If the duplication cannot be performed, buffers are inserted. These buffers
are protected against logic trimming at the implementation level by defining a Keep
(KEEP) attribute in the NGC file.
If the register replication option is set to no, only buffers are used to control fanout
of flip-flops and latches.
Max Fanout is global for the design, but you can control maximum fanout independently
for each entity or module or for given individual signals by using constraints.
If the actual net fanout is less than the Max Fanout value, XST behavior depends on how
Max Fanout is specified.
• If the value of Max Fanout is set in ISE® Design Suite or in the command line, or is
attached to a specific hierarchical block, XST interprets its value as a guidance.
• If Max Fanout is attached to a specific net, XST does not perform logic replication.
Placing Max Fanout on the net may prevent XST from improving timing
optimization.

For example, suppose the following:

• The critical path goes through the net.
• The actual fanout is 80.
• The Max Fanout value is set to 100.
In that instance:
• If Max Fanout is specified in ISE Design Suite, XST may replicate it, trying to
improve timing.
• If Max Fanout is attached to the net itself, XST does not perform logic replication.
Applicable Elements
Propagation Rules
Syntax
-max_fanout integer
The constraint value is an integer. The default value varies depending on the targeted
device family as shown in the following table.
Max Fanout Default Value

Devices Default Value
Spartan®-3 500
Spartan-3E
Spartan-3A
Spartan-3A DSP
Virtex®-4 500
Virtex-5 100000 (One Hundred Thousand)

VHDL
Declare as follows:
attribute max_fanout: string;
Specify as follows:
attribute max_fanout of {signal_name|entity_name}: {signal|entity} is "integer";

Verilog
(* max_fanout = "integer" *)

MODEL "entity_name" max_fanout=integer;

NET "signal_name" max_fanout=integer;
END;
XST Command Line

xst run -max_fanout integer
ISE Design Suite

Process > Process Properties > Xilinx® Specific Options > Max Fanout
Move First Stage (MOVE_FIRST_STAGE)

The Move First Stage (MOVE_FIRST_STAGE) constraint controls the retiming of
registers with paths coming from primary inputs.
Both Move First Stage and Move Last Stage (MOVE_LAST_STAGE) relate to Register
Balancing.
Several constraints influence register balancing.
Register Balancing (REGISTER_BALANCING)
Note
• A flip-flop (FF in the diagram) belongs to the First Stage if it is on the paths coming
from primary inputs.
• A flip-flop belongs to the Last Stage if it is on the paths going to primary outputs.

Move First Stage Diagram
During Register Balancing

During register balancing:
• First Stage flip-flops are moved forward
• Last Stage flip-flops are moved backward.
This process can dramatically increase input-to-clock and clock-to-output timing,
which is not desirable. To prevent this, you may use OFFSET_IN_BEFORE and
OFFSET_IN_AFTER constraints.
If:
• The design does not have a strong requirements, or
• You want to see the first results without touching the first and last flip-flop stages,
You can use two additional constraints:
• Move First Stage
• Move Last Stage
Applicable Elements
Applies to the following only:
• Entire design
• Single modules or entities
• Primary clock signal
Propagation Rules
For Move First Stage propagation rules, see the figure above.

Syntax
-move_first_stage {yes|no}
Both Move First Stage and Move Last Stage may have either of two values:
• yes
• no
– MOVE_FIRST_STAGE=no
Prevents the first flip-flop stage from moving
– MOVE_LAST_STAGE=no
Prevents the last flip-flop stage from moving

VHDL
Declare as follows:
attribute move_first_stage : string;
Specify as follows:
attribute move_first_stage of {entity_name|signal_name } : {signal|entity} is "{yes|no}";
Verilog
(* move_first_stage = "{yes|no}" *)

MODEL "entity_name" move_first_stage={yes|no|true|false};

NET "primary_clock_signal" move_first_stage={yes|no|true|false};
END;
XST Command Line

xst run -move_first_stage {yes|no}
ISE® Design Suite

Process > Process Properties > Xilinx® Specific Options > Move First Flip-Flop Stage
Move Last Stage (MOVE_LAST_STAGE)

The Move Last Stage (MOVE_LAST_STAGE) constraint controls the retiming of
registers with paths going to primary outputs.
Both Move Last Stage and Move First Stage (MOVE_FIRST_STAGE) relate to Register
Balancing.

Applicable Elements
Applies to the following:
• Entire design
• Single modules or entities
• Primary clock signal
Propagation Rules
See Move First Stage (MOVE_FIRST_STAGE).
Syntax
-move_last_stage {yes|no}
• yes (default)
• no
• true (XCF only)

VHDL
Declare as follows:
attribute move_last_stage : string;
Specify as follows:
attribute move_last_stage of {entity_name|signal_name} : {signal|entity} is "{yes|no}";
Verilog
(* move_last_stage = "{yes|no}" *)

MODEL "entity_name" move_last_stage={yes|no|true|false};

NET "primary_clock_signal" move_last_stage={yes|no|true|false};
END;

XST Command Line

xst run -move_last_stage {yes|no}
ISE® Design Suite

Process > Process Properties > Xilinx® Specific Options > Move Last Stage
Multiplier Style (MULT_STYLE)

The Multiplier Style (MULT_STYLE) constraint controls the way the macrogenerator
implements the multiplier macros.
Applicable Elements
Propagation Rules
Syntax
-mult_style {auto|block|kcm|csd|lut|pipe_lut}
• auto (default)
Instructs XST to look for the best implementation for each considered macro.
• block
• pipe_block
– Used to pipeline DSP48 based multipliers.
– Available for the following devices only:
♦ Virtex®-4
♦ Virtex-5
♦ Spartan®-3A DSP
• kcm
• csd
• lut
• pipe_lut
For pipeline slice-based multipliers only.

VHDL
Declare as follows:


Specify as follows:
attribute mult_style of {signal_name|entity_name} : {signal|entity} is
"{auto|block|pipe_block|kcm|csd|lut|pipe_lut}";
Verilog
(* mult_style = "{auto|block|pipe_block|kcm|csd|lut|pipe_lut}" *)

MODEL "entity_name" mult_style={auto|block|pipe_block|kcm|csd|lut|pipe_lut};

NET "signal_name" mult_style={auto|block|pipe_block|kcm|csd|lut|pipe_lut} ;
END;
XST Command Line

xst run -mult_style {auto|block|kcm|csd|lut|pipe_lut}
The -mult_style command line option is not supported for the following devices:
• Virtex-4
• Virtex-5
• Spartan-3A
For those devices, use:
-use_dsp48
ISE® Design Suite

Process > Process Properties > HDL Options > Multiplier Style
Mux Style (MUX_STYLE)

The Mux Style (MUX_STYLE) constraint controls the way the macrogenerator
implements the multiplexer macros.

Available Devices
Devices Resources
Spartan®-3 MUXF
Spartan-3E MUXF6
Spartan-3A MUXCY
Spartan-3A DSP MUXF7
Virtex®-4 MUXF8
Virtex-5
Applicable Elements
Propagation Rules
Syntax
mux_style {auto|muxf|muxcy}
• auto (default)
XST looks for the best implementation for each considered macro.
• muxf
• muxcy

VHDL
Declare as follows:
attribute mux_style: string;
Specify as follows:
attribute mux_style of {signal_name|entity_name} : {signal|entity} is
"{auto|muxf|muxcy}";
Verilog
(* mux_style = "{auto|muxf|muxcy}" *)

MODEL "entity_name" mux_style={auto|muxf|muxcy};


NET "signal_name" mux_style={auto|muxf|muxcy};
END;
XST Command Line

xst run -mux_style {auto|muxf|muxcy}
ISE® Design Suite

Process > Process Properties > HDL Options > Mux Style
Number of Global Clock Buffers (-bufg)

The Number of Global Clock Buffers (-bufg) command line option controls the
maximum number of BUFG components created by XST.
Applicable Elements
Propagation Rules
Not applicable.
Syntax
-bufg integer
The value is an integer. The default value depends on the target device, and is equal
to the maximum number of available BUFG components. Defaults for selected
architectures are shown below.
Devices Default Value
Virtex®-4 32
Virtex-5
Spartan®-3 8
Spartan-3E 24
Spartan-3A
Spartan-3A DSP


XST Command Line

xst run -bufg 8
Sets the number of global clock buffers to 8.
ISE® Design Suite

To set the number of global clock buffers in ISE Design Suite:
1. Select Process > Process Properties > Xilinx®-Specific Options.
3. Set the Number of Clock Buffers property.
Number of Regional Clock Buffers (-bufr)

The Number of Regional Clock Buffers (-bufr) command line option controls the
maximum number of BUFRs created by XST.
• May be used with Virtex®-4 devices only.
• May NOT be used with Virtex-5 devices.
• May NOT be used with Spartan®-3 devices.
• May NOT be used with CPLD devices.
Applicable Elements
Propagation Rules
Not applicable.
Syntax
-bufr integer
The value is an integer. The default value depends on the target device, and is equal to
the maximum number of available BUFRs.

XST Command Line

xst run -bufr 6 6
Sets the number of regional clock buffers to 6.

ISE® Design Suite

To set the number of regional clock buffers in ISE Design Suite:
1. Select Process > Process Properties > Xilinx®-Specific Options
3. Set the Number of Regional Clock Buffers property.
Optimize Instantiated Primitives (OPTIMIZE_PRIMITIVES)

The Optimize Instantiated Primitives (OPTIMIZE_PRIMITIVES) constraint:
• Switches off the default by which XST does not optimize instantiated primitives in
Hardware Description Language (HDL) designs.
• Allows XST to optimize Xilinx® library primitives that have been instantiated in an
HDL design.
Optimization of instantiated primitives is limited by the following factors:
• If an instantiated primitive has specific constraints such as RLOC attached, XST
preserves it as is.
• Not all primitives are considered by XST for optimization. Such hardware elements
as the following are not optimized (modified) even if optimization of instantiated
primitives is enabled:
– MULT18x18
– BRAM
– DSP48
Applicable Elements
Applies to hierarchical blocks, components, and instances.
Propagation Rules
Applies to the component or instance to which it is attached.
Syntax
• yes
• no (default)
• true (XCF only)


Schematic Syntax Examples

• Attach to a valid instance
• Attribute Name
OPTIMIZE_PRIMITIVES
VHDL
Declare as follows:
attribute optimize_primitives: string;
Specify as follows:
attribute optimize_primitives of {component_name|entity_name|label_name} :
{component|entity|label} is "{yes|no}";
Verilog
(* optimize_primitives = "{yes|no}" *)
XCF
MODEL "entity_name" optimize_primitives = {yes|no|true|false};
ISE® Design Suite

Process > Process Properties > Xilinx® Specific Options > Optimize Instantiated
Primitives
Pack I/O Registers Into IOBs (IOB)

The Pack I/O Registers Into IOBs (IOB) constraint packs flip-flops in the I/Os to improve
input/output path timing.
When IOB is set to auto, the action XST takes depends on the Optimization setting:
• If Optimization is set to area, XST packs registers as tightly as possible to the IOBs in
order to reduce the number of slices occupied by the design.
• If Optimization is set to speed, XST packs registers to the IOBs provided they are
not covered by timing constraints (in other words, they are not taken into account
by timing optimization). For example, if you specify a period constraint, XST packs
a register to the IOB if it is not covered by the period constraint. If a register is
covered by timing optimization, but you do want to pack it to an IOB, you must
apply the IOB constraint locally to the register.
Power Reduction (POWER)

The Power Reduction (POWER) constraint instructs XST to optimize the design to
consume as little power as possible.
Macro processing decisions are made to implement functions in a manner than uses
minimal power. Although POWER is allowed in both AREA and SPEED modes, it may
negatively impact the final overall area and speed of the design.

In the current release, power optimization done by XST is dedicated to DSP48 and
BRAM blocks.
XST supports two BRAM optimization methods:
• Method One does not significantly impact area and speed. Method One is used by
default when power optimization is enabled.
• Method Two saves more power, but may significantly impact area and speed.
Both methods can be controlled by using the RAM Style (RAM_STYLE) constraint with
block_power1 for Method One and block_power2 for Method Two.
In some situations, XST may issue an HDL Advisor message giving you tips on how
to improve your design. For example, if XST detects that Read First mode is used for
BRAM, XST recommends that you use Write First or No Change modes.
Applies to Virtex®-4 devices and Virtex-5 devices only. Does not apply to any other
FPGA devices. Does not apply to CPLD devices.
Applicable Elements
Applies to:
• A component or entity (VHDL)
• A model or label (instance) (Verilog)
• A model or INST (in model) (XCF)
• The entire design (XST command line)
Propagation Rules
Syntax
-power {yes|no}
• yes
• no (default)
• true (XCF only)

VHDL
Declare as follows:
attribute power: string;
Specify as follows:
attribute power of {component_name|entity_name} : {component_name|entity_name} is
"{yes|no}";

Verilog
(* power = "{yes|no}" *)
XCF
MODEL "entity_name" power = {yes|no|true|false};
The default is false.
XST Command Line

xst run -power {yes|no}
ISE® Design Suite

Process > Process Properties > Synthesis Options > Power Reduction
Priority Encoder Extraction (PRIORITY_EXTRACT)

The Priority Encoder Extraction (PRIORITY_EXTRACT) constraint enables or disables
priority encoder macro inference.
Applicable Elements
Propagation Rules
Syntax
• yes (default)
• no
• force
• true (XCF only)
For each identified priority encoder description, based on internal decision rules, XST
creates a macro or optimizes it with the rest of the logic. The force value allows you to
override those internal decision rules and force XST to extract the macro.
-priority_extract {yes|no|force}


VHDL
Declare as follows:
attribute priority_extract: string;
Specify as follows:
attribute priority_extract of {signal_name|entity_name} : {signal|entity} is
"{yes|no|force}";
Verilog
(* priority_extract = "{yes|no|force}" *)

MODEL "entity_name" priority_extract={yes|no|true|false|force};

NET "signal_name" priority_extract={yes|no|true|false|force};
END;
XST Command Line

xst run -priority_extract {yes|no|force}
ISE® Design Suite

Process > Process Properties > HDL Options > Priority Encoder Extraction
RAM Extraction (RAM_EXTRACT)

The RAM Extraction (RAM_EXTRACT) constraint enables or disables RAM macro
inference.
Applicable Elements
Propagation Rules

Syntax
-ram_extract {yes|no}
• yes (default)
• no
• true (XCF only)

VHDL
Declare as follows:
attribute ram_extract: string;
Specify as follows:
attribute ram_extract of {signal_name|entity_name} : {signal|entity} is "{yes|no}";
Verilog
(* ram_extract = "{yes|no}" *)

MODEL "entity_name" ram_extract={yes|no|true|false};

NET "signal_name" ram_extract={yes|no|true|false};
END;
XST Command Line

xst run -ram_extract {yes|no}
ISE® Design Suite

Process > Process Properties > HDL Options > RAM Extraction
RAM Style (RAM_STYLE)

The RAM Style (RAM_STYLE) constraint controls the way the macrogenerator
implements the inferred RAM macros.

The following are supported for Virtex®-4 devices and Virtex-5 devices only:
• block_power1
• block_power2
Applicable Elements
Propagation Rules
Syntax
ram_style {auto|block|distributed}
• auto (default)
• block
• distributed
• pipe_distributed
• block_power1
• block_power2
XST looks for the best implementation for each inferred RAM.
You must use block_power1 and block_power2 in order to achieve power-oriented
BRAM optimization.
Power Reduction (POWER)
The implementation style can be manually forced to use block RAM or distributed
RAM resources.
You can specify the following only through VHDL, Verilog, or XCF constraints:
• pipe_distributed
• block_power1
• block_power2

VHDL
Declare as follows:
attribute ram_style: string;
Specify as follows:
attribute ram_style of {signal_name|entity_name} : {signal|entity} is
"{auto|block|distributed|pipe_distributed|block_power1|block_power2}";
Verilog

(* ram_style =
"{auto|block|distributed|pipe_distributed|block_power1|block_power2}" *)

MODEL "entity_name"
ram_style={auto|block|distributed|pipe_distributed|block_power1|block_power2};

NET "signal_name"
ram_style={auto|block|distributed|pipe_distributed|block_power1|block_power2};
END;
XST Command Line

xst run -ram_style {auto|block|distributed}
The pipe_distributed value is not accessible through the command line.
ISE® Design Suite

Process > Process Properties > HDL Options > RAM Style
Read Cores (READ_CORES)

The Read Cores (READ_CORES) constraint enables or disables the ability of XST to
read Electronic Data Interchange Format (EDIF) or NGC core files for timing estimation
and device utilization control.
By reading a specific core, XST is better able to optimize logic around the core, since it
sees how the logic is connected. However, in some cases the Read Cores operation must
be disabled in XST in order to obtain the desired results. For example, the PCI™ core
must not be visible to XST, since the logic directly connected to the PCI core must be
optimized differently as compared to other cores. Read Cores allows you to enable or
disable read operations on a core by core basis.
Cores Processing
Applicable Elements
Since this constraint can be used with BoxType (BOX_TYPE) the set of objects on which
the both constraints can be applied must be the same.
Apply Read Cores to:
• A component or entity (VHDL)
• A model or label (instance) (Verilog)
• A model or INST (in model) (XCF)
• The entire design (XST command line)
If Read Cores is applied to at least a single instance of a block, then Read Cores is applied
to all other instances of this block for the entire design.

Propagation Rules
Not applicable.
Syntax
-read_cores {yes|no|optimize}
• no (false)
Disables cores processing
• yes (true) (default)
Enables cores processing, but maintains the core as a black box and does not further
incorporate the core into the design
• optimize
Enables cores processing, and merges the cores netlist into the overall design. This
value is available through the XST command line mode only.

VHDL
Declare as follows:
attribute read_cores: string;
Specify as follows:
attribute read_cores of {component_name|entity_name} : {component|entity} is
"{yes|no|optimize}";
Verilog
(* read_cores = "{yes|no|optimize}" *)

MODEL "entity_name" read_cores = {yes|no|true|false|optimize};

BEGIN MODEL "entity_name" END;
INST "instance_name" read_cores = {yes|no|true|false|optimize};
END;
XST Command Line

xst run -read_cores {yes|no|optimize}
ISE® Design Suite

Process > Process Properties > Synthesis Options > Read Cores
Note The optimize option is not available in ISE Design Suite.

Reduce Control Sets (REDUCE_CONTROL_SETS)

The Reduce Control Sets (REDUCE_CONTROL_SETS) constraint allows you to reduce
the number of control sets and, as a consequence, reduce the design area.
Reducing the number of control sets should:
• Improve the packing process in map.
• Reduce the number of used slices even if the number of LUTs is increased.
Applies to Virtex®-5 devices only. Does not apply to any other devices.
Applicable Elements
Propagation Rules
Not applicable.
Syntax
-reduce_control_sets {auto|no}
• auto
XST optimizes automatically, and reduces the existing control sets in the design.
• no (default)
XST performs no control set optimization.

XST Command Line

xst run -reduce_control_sets {auto|no}
ISE® Design Suite

Process > Process Properties > Xilinx Specific Options > Reduce Control Sets
Register Balancing (REGISTER_BALANCING)

The Register Balancing (REGISTER_BALANCING) constraint enables flip-flop
retiming.
The main goal of register balancing is to move flip-flops and latches across logic to
increase clock frequency.
The two categories of REGISTER_BALANCING are:
• Forward Register Balancing
• Backward Register Balancing

Forward Register Balancing
Forward Register Balancing moves a set of flip-flops at the inputs of a LUT to a single
flip-flop at its output.
When replacing several flip-flops with one, select the name based on the name of the
LUT across which the flip-flops are moving as shown in the following:
LutName _FRBId
Backward Register Balancing
Backward Register Balancing moves a flip-flop at the output of a LUT to a set of

flip-flops at its inputs.
As a consequence the number of flip-flops in the design can be increased or decreased.
The new flip-flop has the same name as the original flip-flop with an indexed suffix as
shown in the following:
OriginalFFName _BRBId
Additional Constraints That Impact Register Balancing

Two additional constraints control register balancing:

Several other constraints also influence register balancing:

– If the hierarchy is preserved, flip-flops are moved only inside the block
boundaries.
– If the hierarchy is flattened, flip-flops may leave the block boundaries.
If IOB=TRUE, register balancing is not applied to the flip-flops having this property.
Instantiated flip-flops are moved only if OPTIMIZE_PRIMITIVES=YES.
• Flip-flops are moved across instantiated primitives only if
OPTIMIZE_PRIMITIVES=YES.
• Keep (KEEP)
If applied to the output flip-flop signal, the flip-flop is not moved forward.
Applied to the Input Flip-Flop Signal
If applied to the input flip-flop signal, the flip-flop is not moved backward.
If applied to both the input and output of the flip-flop, it is equivalent to

REGISTER_BALANCING=no
Applicable Elements
Applies to:
• The entire design using the command line or ISE® Design Suite
• An entity or module
• A signal corresponding to the flip-flop description (RTL)
• A flip-flop instance
• The Primary Clock Signal
In this case the register balancing is performed only for flip-flops synchronized
by this clock.

Propagation Rules
Syntax
-register_balancing {yes|no|forward|backward}
• yes
Both forward and backward retiming are allowed.
• no (default)
Neither forward nor backward retiming is allowed.
• forward
Only forward retiming is allowed
• backward
Only backward retiming is allowed.
• true (XCF only)

VHDL
Declare as follows:
attribute register_balancing: string;
Specify as follows:
attribute register_balancing of {signal_name|entity_name}: {signal|entity} is
"{yes|no|forward|backward}";
Verilog
(* register_balancing = "{yes|no|forward|backward}" *)

MODEL "entity_name" register_balancing={yes|no|true|false|forward|backward};

NET "primary_clock_signal"
register_balancing={yes|no|true|false|forward|backward};"
END;
XCF Example Three


INST "instance_name" register_balancing={yes|no|true|false|forward|backward};

END;
XST Command Line

xst run -register_balancing {yes|no|forward|backward}
ISE Design Suite

Process > Process Properties > Xilinx Specific Options > Register Balancing
Register Duplication (REGISTER_DUPLICATION)

The Register Duplication (REGISTER_DUPLICATION) constraint:
• Enables or disables register replication.
• Is enabled, and is performed during timing optimization and fanout control.
Applicable Elements
Propagation Rules
Syntax
• yes (default)
• no
• true (XCF only)

VHDL
Declare as follows:
attribute register_duplication: string;
Specify as follows:
attribute register_duplication of entity_name: entity is "{yes|no}";
Verilog

(* register_duplication = "{yes|no}" *)

MODEL "entity_name" register_duplication={yes|no|true|false};

NET "signal_name" register_duplication={yes|no|true|false};
END;
ISE® Design Suite

Process > Process Properties > Xilinx Specific Options > Register Duplication
ROM Extraction (ROM_EXTRACT)

The ROM Extraction (ROM_EXTRACT) constraint enables or disables ROM macro
inference.
Typically, a ROM can be inferred from a case statement where all assigned contexts
are constant values.
Applicable Elements
Applies to the entire design, or to a design element or signal.
Propagation Rules
Syntax
-rom_extract {yes|no}
• yes (default)
• no
• true (XCF only)

VHDL
Declare as follows:

attribute rom_extract: string;

Specify as follows:
attribute rom_extract of {signal_name|entity_name } : {signal|entity} is "{yes|no}";
Verilog
(* rom_extract = "{yes|no}" *)

MODEL "entity_name" rom_extract={yes|no|true|false};

NET "signal_name" rom_extract={yes|no|true|false};
END;
XST Command Line

xst run -rom_extract {yes|no}
ISE® Design Suite

Process > Process Properties > HDL Options > ROM Extraction
ROM Style (ROM_STYLE)

The ROM Style (ROM_STYLE) constraint controls the way the macrogenerator
implements the inferred ROM macros.
Caution! ROM Extraction (ROM_EXTRACT) must be set to yes in order to use ROM
Style (ROM_STYLE).
Applicable Elements
Propagation Rules

Syntax
-rom_style {auto|block|distributed}
• auto (default)
XST looks for the best implementation for each inferred ROM. The implementation
style can be manually forced to use block ROM or distributed ROM resources.
• block
• distributed

VHDL
Declare as follows:
attribute rom_style: string;
Specify as follows:
attribute rom_style of {signal_name|entity_name} : {signal|entity} is
"{auto|block|distributed}";
Verilog
Declare as follows:
(* rom_style = "{auto|block|distributed}" *)

MODEL "entity_name" rom_style={auto|block|distributed};

NET "signal_name" rom_style={auto|block|distributed};
END;
XST Command Line

xst run -rom_style {auto|block|distributed}
ISE® Design Suite

Process > Process Properties > HDL Options > ROM Style

The Shift Register Extraction (SHREG_EXTRACT) constraint:
• Enables or disables shift register macro inference.
• Results in the usage of dedicated hardware resources such as SRL16 and SRLC16.

Shift Registers HDL Coding Techniques
Applicable Elements
Applies to the entire design, or to a design element or signal.
Propagation Rules
Syntax
-shreg_extract {yes|no}
• yes (default)
• no
• true (XCF only)

VHDL
Declare as follows:
attribute shreg_extract : string;
Specify as follows:
attribute shreg_extract of {signal_name|entity_name} : {signal|entity} is "{yes|no}";
Verilog
(* shreg_extract = "{yes|no}" *)

MODEL "entity_name"shreg_extract={yes|no|true|false};

NET "signal_name" shreg_extract={yes|no|true|false};
END;
XST Command Line

xst run -shreg_extract {yes|no}

ISE® Design Suite

Process > Process Properties > HDL Options > Shift Register Extraction
Slice (LUT-FF Pairs) Utilization Ratio (SLICE_UTILIZATION_RATIO)

The Slice (LUT-FF Pairs) Utilization Ratio (SLICE_UTILIZATION_RATIO) constraint
defines the area size in absolute numbers or percent of total numbers of the following
components that XST must not exceed during timing optimization:
• LUT-FF pairs (Virtex®-5 devices)
• slices (all other devices)
If the area constraint cannot be satisfied, XST makes timing optimization regardless
of the area constraint. To disable automatic resource management, specify -1 as a
constraint value.
Applicable Elements
Propagation Rules
Syntax

VHDL
Declare as follows:
attribute slice_utilization_ratio: string;
Specify as follows:
attribute slice_utilization_ratio of entity_name : entity is "integer";
attribute slice_utilization_ratio of entity_name : entity is "integer%";
attribute slice_utilization_ratio of entity_name : entity is "integer#";
XST interprets the integer values in the first two examples above as a percentage and in
the last example as an absolute number of slices or FF-LUT pairs.
The integer value range is 0 to 100 when percent (%) is used or both percent (%) and
pound (#) are omitted.

Verilog
(* slice_utilization_ratio = "integer" *)
(* slice_utilization_ratio = "integer%" *)
(* slice_utilization_ratio = "integer#" *)
XCF
MODEL "entity_name" slice_utilization_ratio=integer;
MODEL "entity_name" slice_utilization_ratio=integer%;
MODEL "entity_name" slice_utilization_ratio=integer#;
characters.
You must surround the integer value and the percent (%) and pound (#) characters
with double quotes ("...") because the percent (%) and pound (#) characters are special
characters in the XST Constraint File (XCF).
XST Command Line

xst run -slice_utilization_ratio integer
xst run -slice_utilization_ratio integer%
xst run -slice_utilization_ratio integer#
ISE® Design Suite

Process > Process Properties > Synthesis Options > Slice Utilization Ratio or Process >
Process Properties > Synthesis Options > LUT-FF Pairs Utilization Ratio
In ISE Design Suite, you can define the value of Slice (LUT-FF Pairs) Utilization Ratio
only as a percentage. You can not define the value as an absolute number of slices.

Slice (LUT-FF Pairs) Utilization Ratio Delta

(SLICE_UTILIZATION_RATIO_MAXMARGIN)
The Slice (LUT-FF Pairs) Utilization Ratio Delta
(SLICE_UTILIZATION_RATIO_MAXMARGIN) constraint:
• Is closely related to Slice (LUT-FF Pairs) Utilization Ratio
(SLICE_UTILIZATION_RATIO).
• Defines the tolerance margin for Slice (LUT-FF Pairs) Utilization Ratio
(SLICE_UTILIZATION_RATIO).
The value of the parameter can be defined in the form of percentage as well as an absolute
number of slices or LUT-FF pairs.
If the ratio is within the margin set, the constraint is met and timing optimization can
continue.
Applicable Elements
Propagation Rules
Syntax

VHDL
Declare as follows:
attribute slice_utilization_ratio_maxmargin: string;
Specify as follows:
attribute slice_utilization_ratio_maxmargin of entity_name : entity is "integer";
attribute slice_utilization_ratio_maxmargin of entity_name : entity is "integer%";
attribute slice_utilization_ratio_maxmargin of entity_name : entity is "integer#";

Verilog
(* slice_utilization_ratio_maxmargin = "integer" *)
(* slice_utilization_ratio_maxmargin = "integer%" *)
(* slice_utilization_ratio_maxmargin = "integer#" *)
XCF
MODEL "entity_name" slice_utilization_ratio_maxmargin=integer;
MODEL "entity_name" slice_utilization_ratio_maxmargin="integer%";
MODEL "entity_name" slice_utilization_ratio_maxmargin="integer#";
characters.
You must surround the integer value and the percent (%) and pound (#) characters
with double quotes ("...") because the percent (%) and pound (#) characters are special
characters in the XST Constraint File (XCF).
XST Command Line

xst run -slice_utilization_ratio_maxmargin integer
xst run -slice_utilization_ratio_maxmargin integer%
xst run -slice_utilization_ratio_maxmargin integer#
Slice Packing (-slice_packing)

The Slice Packing (-slice_packing) command line option enables the XST internal packer.
The packer attempts to pack critical LUT-to-LUT connections within a slice or a CLB.
This exploits the fast feedback connections among the LUTs in a CLB.
Applicable Elements

Propagation Rules
Not applicable.
Syntax
-slice_packing {yes|no}
• yes
• no

XST Command Line

xst run -slice_packing no
Disables the XST internal slice packer.
ISE® Design Suite

Process > Process Properties > Xilinx® Specific Options > Slice Packing
Use Low Skew Lines (USELOWSKEWLINES)

The Use Low Skew Lines (USELOWSKEWLINES) constraint:
• Is a basic routing constraint.
• Prevents XST from using dedicated clock resources and logic replication during
synthesis, based on the value of the Max Fanout (MAX_FANOUT) constraint.
• Specifies the use of low skew routing resources for any net.
Use Carry Chain (USE_CARRY_CHAIN)

The Use Carry Chain (USE_CARRY_CHAIN) constraint:
• Is both a global and a local constraint
• Can deactivate carry chain use for macro generation
XST uses carry chain resources to implement certain macros, but there are situations
where you can obtain better results by not using carry chain.
Applicable Elements
Applies to the entire design, or to signals.

Propagation Rules
Syntax
-use_carry_chain {yes|no}
• yes (default)
• no
• true (XCF only)

Schematic
• Attach to a valid instance
• Attribute Name
USE_CARRY_CHAIN
VHDL
Declare as follows:
attribute use_carry_chain: string;
Specify as follows:
attribute use_carry_chain of signal_name: signal is "{yes|no}";
Verilog
(* use_carry_chain = "{yes|no}" *)

MODEL "entity_name" use_carry_chain={yes|no|true|false};

NET "signal_name" use_carry_chain={yes|no|true|false};
END;
XST Command Line

xst run -use_carry_chain {yes|no}

Use Clock Enable (USE_CLOCK_ENABLE)

The Use Clock Enable (USE_CLOCK_ENABLE) constraint enables or disables the clock
enable function in flip-flops.
The disabling of the clock enable function is typically used for ASIC prototyping on
FPGA devices.
By detecting Use Clock Enable with a value of no or false, XST avoids using CE
resources in the final implementation. Moreover, for some designs, putting the Clock
Enable function on the data input of the flip-flop allows better logic optimization and
therefore better quality of results.
In auto mode, XST tries to estimate a trade off between using a dedicated clock enable
input of a flip-flop input and putting clock enable logic on the D input of a flip-flop. In a
case where a flip-flop is instantiated by you, XST removes the clock enable only if the
Optimize Instantiated Primitives option is set to yes.
Applicable Elements
Applies to:
• A signal representing a flip-flop
• An instance representing an instantiated flip-flop
Propagation Rules
Syntax
-use_clock_enable {auto|yes|no}
• auto (default)
• yes
• no
• true (XCF only)

VHDL
Declare as follows:
attribute use_clock_enable: string;
Specify as follows:

attribute use_clock_enable of {entity_name|component_name|signal_name|instance_name}

: {entity|component|signal|label} is "{auto|yes|no}";
Verilog
Place immediately before the instance, module, or signal declaration:
(* use_clock_enable = "{auto|yes|no}" *)

MODEL "entity_name" use_clock_enable={auto|yes|no|true|false};

NET "signal_name" use_clock_enable={auto|yes|no|true|false};
END

BEGIN MODEL "entity_name ;"
INST "instance_name" use_clock_enable={auto|yes|no|true|false};
END
XST Command Line

xst run -use_clock_enable {auto|yes|no}
ISE® Design Suite

Process > Process Properties > Xilinx Specific Options > Use Clock Enable
USE_DSP48 (Use DSP48)

This constraint is called:
• Use DSP48
Virtex®-4 devices
• Use DSP Block
Virtex-5 devices and Spartan®-3A DSP devices
XST enables you to use the resources of the DSP48 blocks introduced in Virtex-4 devices.
In auto mode, XST automatically implements such macros as MAC and accumulates on
DSP48, but some of them as adders are implemented on slices. You have to force their
implementation on DSP48 using a value of yes or true.
For more information on supported macros and their implementation control, see:
Several macros (for example, MAC) that can be placed on DSP48 are in fact a
composition of simpler macros such as multipliers, accumulators, and registers. To
achieve the best performance, XST by default tries to infer and implement the maximum
macro configuration. To shape a macro in a specific way, use the Keep (KEEP) constraint.
For example, DSP48 allows you to implement a multiple with two input registers. To
leave the first register stage outside of the DSP48, place the Keep (KEEP) constraint in
their outputs.

Applies to the following devices only. Does not apply to any other devices.
• Spartan-3A DSP
• Virtex-4
• Virtex-5
Applicable Elements
Applies to:
• A signal representing a macro described at the RTL level
Propagation Rules
Syntax
-use_dsp48 {auto|yes|no}
• auto (default)
• yes
• no
• true (XCF only)
In auto mode you can control the number of available DSP48 resources for synthesis
using DSP Utilization Ratio (DSP_UTILIZATION_RATIO). By default, XST tries to
utilize, as much as possible, all available DSP48 resources.

VHDL
Declare as follows:
attribute use_dsp48: string;
Specify as follows:
attribute use_dsp48 of {"entity_name|component_name|signal_name"} :
{entity|component|signal} is "{auto|yes|no}";
Verilog
(* use_dsp48 = "{auto|yes|no}" *)


MODEL "entity_name" use_dsp48={auto|yes|no|true|false};

NET "signal_name" use_dsp48={auto|yes|no|true|false};
END;"
XST Command Line

xst run -use_dsp48 {auto|yes|no}
ISE® Design Suite

Process > Process Properties > HDL Options > Use DSP48
Use Synchronous Set (USE_SYNC_SET)

The Use Synchronous Set (USE_SYNC_SET) constraint enables or disables the
synchronous set function in flip-flops.
Disabling the synchronous set function is typically used for ASIC prototyping on FPGA
devices. When XST detects Use Synchronous Set with a value of no or false, XST avoids
using synchronous reset resources in the final implementation. For some designs,
putting synchronous reset function on data input of the flip-flop allows better logic
optimization and therefore gives better quality of results.
In auto mode, XST tries to estimate a trade off between using dedicated Synchronous Set
input of a flip-flop input and putting Synchronous Set logic on the D input of a flip-flop.
When a flip-flop is instantiated by the designer, XST removes the synchronous reset only
if Optimize Instantiated Primitives is set to yes.
Applicable Elements
Applies to:
Propagation Rules

Syntax
-use_sync_set {auto|yes|no}
• auto (default)
• yes
• no
• true (XCF only)

VHDL
Declare as follows:
attribute use_sync_set: string;
Specify as follows:
attribute use_sync_set of {entity_name|component_name|signal_name|instance_name}:
{entity|component|signal|label} is "{auto|yes|no}";
Verilog
(* use_sync_set = "{auto|yes|no}" *)

MODEL "entity_name" use_sync_set={auto|yes|no|true|false};

NET "signal_name" use_sync_set={auto|yes|no|true|false};
END;

INST "instance_name" use_sync_set={auto|yes|no|true|false};
END;
XST Command Line

xst run -use_sync_set {auto|yes|no}
ISE® Design Suite

Process > Process Properties > Xilinx® Specific Options > Use Synchronous Set

Use Synchronous Reset (USE_SYNC_RESET)

The Use Synchronous Reset (USE_SYNC_RESET) constraint enables or disables the
usage of synchronous reset function of flip-flops.
Disabling synchronous reset can be used for ASIC prototyping flow on FPGA devices.
Applicable Elements
Applies to:
Propagation Rules
Syntax
-use_sync_reset {auto|yes|no}
• auto (default)
• yes
• no
• true (XCF only)
When XST detects Use Synchronous Reset with a value of no or false, XST avoids using
synchronous reset resources in the final implementation. For some designs, putting
synchronous reset function on data input of the flip-flop allows better logic optimization
and therefore better quality of results.
In auto mode, XST tries to estimate a trade off between using a dedicated Synchronous
Reset input on a flip-flop input and putting Synchronous Reset logic on the D input of a
flip-flop. When a flip-flop is instantiated by a designer, XST removes the synchronous
reset only if the Optimize Instantiated Primitives option is set to yes.

VHDL
Declare as follows:
attribute use_sync_reset: string;
Specify as follows:
attribute use_sync_reset of {entity_name|component_name|signal_name|instance_name}
: {entity|component|signal|label} is "{auto|yes|no}";

Verilog
(* use_sync_reset = "{auto|yes|no}" *)

MODEL "entity_name" use_sync_reset={auto|yes|no|true|false};

NET "signal_name" use_sync_reset={auto|yes|no|true|false};
END;

INST "instance_name" use_sync_reset={auto|yes|no|true|false};
END;
XST Command Line

xst run -use_sync_reset {auto|yes|no}
ISE® Design Suite

Process > Process Properties > Xilinx Specific Options > Use Synchronous Reset
XOR Collapsing (XOR_COLLAPSE)

The XOR Collapsing (XOR_COLLAPSE) constraint controls whether cascaded XORs
should be collapsed into a single XOR.
Applicable Elements
Applies to cascaded XORs.
Propagation Rules
Not applicable.

Syntax
-xor_collapse {yes|no}
• yes (default)
• no
• true (XCF only)

VHDL
Declare as follows:
attribute xor_collapse: string;
Specify as follows:
attribute xor_collapse {signal_name|entity_name} : {signal|entity} is "{yes|no}";
Verilog
(* xor_collapse = "{yes|no}" *)

MODEL "entity_name" xor_collapse={yes|no|true|false};

NET "signal_name" xor_collapse={yes|no|true|false};
END;
XST Command Line

xst run -xor_collapse {yes|no}
ISE® Design Suite

Process > Process Properties > HDL Options > XOR Collapsing

Chapter 10
XST CPLD Constraints (Non-Timing)

Important! The constraints described in this chapter apply to CPLD devices only. They
do not apply to FPGA devices.
• Data Gate (DATA_GATE)
Clock Enable (-pld_ce)

The Clock Enable (-pld_ce) command line option specifies how sequential logic should
be implemented when it contains a clock enable, either using the specific device
resources available for the clock enable or generating equivalent logic.
Keeping or not keeping the clock enable signal depends on the design logic. When
the clock enable is the result of a Boolean expression, setting Clock Enable to no may
improve the fitting result. The input data of the flip-flop is simplified when it is merged
with the clock enable expression.
Applies to all CPLD devices. Does not apply to FPGA devices.
Applicable Elements
Applies to an entire design through the XST command line.
Propagation Rules
Not applicable.
Syntax
-pld_ce {yes|no}
• yes (default)
The synthesizer implements the clock enable signal of the device.
• no
The clock enable function is implemented through equivalent logic.

Chapter 10: XST CPLD Constraints (Non-Timing)

xst run -pld_ce yes
Defines Clock Enable globally to yes. The clock enable function is implemented through
equivalent logic.
ISE® Design Suite

Process > Process Properties > Xilinx-Specific Options > Clock Enable
Data Gate (DATA_GATE)

The Data Gate (DATA_GATE) constraint:
• Applies to CoolRunner™-II devices only.
• Provides a direct means of reducing power consumption in your design.
Each I/O pin input signal passes through a latch that can block the propagation of
incident transitions during periods when such transitions are not of interest to your
CPLD design.
Input transitions that do not affect the CPLD design function still consume power, if not
latched, since they are routed among the CPLD’s Function Blocks. By asserting the Data
Gate control I/O pin on the device, selected I/O pin inputs become latched, eliminating
the power dissipation associated with external transitions on those pins.
Macro Preserve (-pld_mp)

The Macro Preserve (-pld_mp) command line option:
• Makes macro handling independent of design hierarchy processing.
• Allows you to merge all hierarchical blocks in the top module, while still keeping
the macros as hierarchical modules
You can keep the design hierarchy except for the macros, which are merged with the
surrounding logic. Merging the macros sometimes gives better results for design fitting.
Applicable Elements
Propagation Rules
Not applicable.

Syntax
-pld_mp {yes|no}
• yes (default)
Macros are preserved and generated by Macro+.
• no
Macros are rejected and generated by HDL synthesizer
Depending on the Flatten Hierarchy value, a rejected macro is either merged in the
design logic, or becomes a hierarchical block as shown in the following table.
Flatten Hierarchy Value Disposition
yes Merged in the design logic
no Becomes a hierarchical block
Very small macros such as 2-bit adders and 4-bit multiplexers are always merged,
independent of the Macro Preserve or Flatten Hierarchy options.
Syntax and Settings Examples

XST Command Line

xst run -pld_mp no
Macros are rejected and generated by HDL synthesizer.
ISE® Design Suite

Process > Process Properties > Xilinx®-Specific Options > Macro Preserve
No Reduce (NOREDUCE)
The No Reduce (NOREDUCE) constraint:
• Prevents minimization of redundant logic terms that are typically included in a
design to avoid logic hazards or race conditions.
• Identifies the output node of a combinatorial feedback loop to ensure correct
mapping.
WYSIWYG (-wysiwyg)
The WYSIWYG (-wysiwyg) command line option makes a netlist reflect the user
specification as closely as possible. That is, all the nodes declared in the Hardware
Description Language (HDL) design are preserved.
If WYSIWYG mode is enabled (yes), XST:
• Preserves all user internal signals (nodes)
• Creates SOURCE_NODE constraints in the NGC file for all these nodes
• Skips design optimization (collapse, factorization)

Only Boolean equation minimization is performed.
Applicable Elements
Propagation Rules
Not applicable.
Syntax
• yes
• no (default)

XST Command Line

xst run -wysiwyg {yes|no}
ISE® Design Suite

Process > Process Properties > Xilinx® Specific Options > WYSIWYG
XOR Preserve (-pld_xp)

The XOR Preserve (-pld_xp) command line option enables or disables hierarchical
flattening of XOR macros.
The XORs inferred by Hardware Description Language (HDL) synthesis are also
considered as macro blocks in the CPLD flow. They are processed separately to give
more flexibility for using device macrocells XOR gates. You can flatten its design (Flatten
Hierarchy yes, Macro Preserve no) but Xilinx® recommends preserving the XORs to:
• Reduce design complexity
• Reduce the number of PTerms
Set the value no to obtain completely flat netlists. Applying global optimization on a
completely flat design sometimes improves design fitting.
Applicable Elements

Propagation Rules
Not applicable.
Syntax
-pld_xp {yes|no}
• yes (default)
• no
yes preserves XOR macros.
no merges XOR macros with surrounded logic.
Select the following options to obtain a completely flattened design:
• Flatten Hierarchy
yes
• Macro Preserve
no
• XOR Preserve
no
The no value does not guarantee the elimination of the XOR operator from the Electronic
Data Interchange Format (EDIF) netlist. During the netlist generation, the netlist
mapper tries to recognize and infer XOR gates in order to decrease the logic complexity.
This process is independent of the XOR preservation done by Hardware Description
Language (HDL) synthesis, and is guided only by the goal of complexity reduction.

XST Command Line

xst run -pld_xp yes
Preserves XOR macros.
ISE® Design Suite

Process > Process Properties > Xilinx-Specific Options > XOR Preserve

Chapter 11
XST Timing Constraints

• Clock Signal (CLOCK_SIGNAL)
• Offset (OFFSET)
• Period (PERIOD)
• Applying Timing Constraints
• XCF Timing Constraint Support

Chapter 11: XST Timing Constraints
Applying Timing Constraints

• About Applying Timing Constraints
• Applying Timing Constraints Using Global Optimization Goal
• Applying Timing Constraints Using the UCF
• Writing Constraints to the NGC File
• Additional Options Affecting Timing Constraint Processing
About Applying Timing Constraints

Apply XST-supported timing constraints with:
• ISE® Design Suite in:
Process > Properties > Synthesis Options > Global Optimization Goal
• User Constraints File (UCF)
Applying Timing Constraints Using Global Optimization Goal

Global Optimization Goal (-glob_opt) allows you to apply the five global timing
constraints:
• ALLCLOCKNETS
• OFFSET_IN_BEFORE
• OFFSET_OUT_AFTER
• INPAD_TO_OUTPAD
• MAX_DELAY
These constraints are applied globally to the entire design. You cannot specify a value for
these constraints, since XST optimizes them for the best performance. These constraints
are overridden by constraints specified in the User Constraints File (UCF).
Applying Timing Constraints Using the UCF

The User Constraints File (UCF) allows you to specify timing constraints using native
UCF syntax. XST supports constraints such as:
• Period (PERIOD)
XST supports wildcards and hierarchical names with these constraints.
Writing Constraints to the NGC File

Timing constraints are not written to the NGC file by default. Timing constraints are
written to the NGC file only when:
• Write Timing Constraints is checked yes in ISE Design Suite in Process > Process
Properties, or
• The -write_timing_constraints option is specified when using the command line.

Additional Options Affecting Timing Constraint Processing

Three additional options affect timing constraint processing, regardless of how the
timing constraints are specified:
• Clock Signal (CLOCK_SIGNAL)
XCF Timing Constraint Support

This section discusses XST Constraint File (XCF) Timing Constraint Support and
includes:
• Hierarchy Separator
• Supported Timing Constraints
• Unsupported Timing Constraints
Hierarchy Separator
If you specify timing constraints in the XST Constraint File (XCF), Xilinx® recommends
that you use a forward slash (/) as a hierarchy separator instead of an underscore (_).
Supported Timing Constraints

The XST Constraint File (XCF) supports the following timing constraints:
• Period (PERIOD)
• Offset (OFFSET)
Unsupported Timing Constraints

If XST does not support all or part of a specified timing constraint, then XST:
• Issues a warning, and
• Ignores the unsupported timing constraint (or unsupported part of it) in the Timing
Optimization step
If Write Timing Constraints is set to yes, XST propagates the entire constraint to the final
netlist, even if it was ignored at the Timing Optimization step.
Clock Signal (CLOCK_SIGNAL)

The Clock Signal (CLOCK_SIGNAL) constraint allows you to define a clock signal
when the signal goes through combinatorial logic before being connected to the clock
input of a flip-flop.

In that instance, XST cannot identify which input pin or internal signal is the real clock
signal. You must define it manually
Applicable Elements
Applies to signals.
Propagation Rules
Applies to clock signals.
Syntax
• yes (default)
• no
• true (XCF only)

VHDL
Declare as follows:
attribute clock_signal : string;
Specify as follows:
attribute clock_signal of signal_name : signal is {yes|no};
Verilog
(* clock_signal = "{yes|no}" *)
XCF
NET "primary_clock_signal" clock_signal={yes|no|true|false};
END;
Cross Clock Analysis (-cross_clock_analysis)

The Cross Clock Analysis (-cross_clock_analysis) command line option tells XST to
perform inter-clock domain analysis during timing optimization.

Applicable Elements
Propagation Rules
Not applicable.
Syntax
-cross_clock_analysis {yes|no}
• yes
• no (default)

XST Command Line

xst run -cross_clock_analysis yes
Tells XST to perform inter-clock domain analysis during timing optimization.
ISE® Design Suite

Process > Process Properties > Synthesis Options > Cross Clock Analysis
From-To (FROM-TO)
The From-To (FROM-TO) constraint defines a timing constraint between two groups.
A group can be user-defined or predefined:
• FF
• PAD
• RAM
Syntax Example
TIMESPEC TSname = FROM group1 TO group2 value;
Global Optimization Goal (-glob_opt)

The Global Optimization Goal (-glob_opt) command line option selects the global
optimization goal.

Depending on the Global Optimization Goal, XST can optimize the following design
regions:
• Register to Register
• Inpad to Register
• Register to Outpad
• Inpad to Outpad
For a detailed description of supported timing constraints, see:
Partitions
Apply the following constraints with Global Optimization Goal:
• ALLCLOCKNETS (Register to Register)
Optimizes the period of the entire design.
XST identifies, by default, all paths from register to register on the same clock for all
clocks in a design. To take inter-clock domain delays into account, set Cross Clock
Analysis (-cross_clock_analysis) to yes.
• OFFSET_IN_BEFORE (Inpad to Register)
Optimizes the maximum delay from input pad to clock, either for a specific clock
or for an entire design.
XST identifies all paths from either all sequential elements or the sequential elements
driven by the given clock signal name to all primary output ports.
• OFFSET_OUT_AFTER (Register to Outpad)
Optimizes the maximum delay from clock to output pad, either for a specific clock
or for an entire design.
XST identifies all paths from all primary input ports to either all sequential elements
or the sequential elements driven by the given clock signal name.
• INPAD_TO_OUTPAD (Inpad to Outpad)
Optimizes the maximum delay from input pad to output pad throughout an entire
design.
• MAX_DELAY
Incorporates all previously mentioned constraints
These constraints affect the entire design. They apply only if no timing constraints are
specified in the constraint file.
Syntax
-glob_opt
{allclocknets|offset_in_before|offset_out_after|inpad_to_outpad|max_delay}
You cannot specify a value for Global Optimization Goal. XST optimizes the entire
design for the best performance.

XST Command Line

xst run -glob_opt OFFSET_OUT_AFTER

Optimizes the maximum delay from clock to output pad for the entire design
ISE® Design Suite

Process > Process Properties > Synthesis Options > Global Optimization Goal
Global Optimization Goal Domain Definitions

The possible domains are shown in the following schematic.
• ALLCLOCKNETS (register to register)
Identifies, by default, all paths from register to register on the same clock for all
clocks in a design. To take inter-clock domain delays into account, set Cross Clock
Analysis (–cross_clock_analysis) to yes.
• OFFSET_IN_BEFORE (inpad to register)
Identifies all paths from all primary input ports to either all sequential elements or
the sequential elements driven by the given clock signal name.
• OFFSET_OUT_AFTER (register to outpad)
Similar to the previous constraint, but sets the constraint from the sequential
elements to all primary output ports.
• INPAD_TO_OUTPAD (inpad to outpad)
Sets a maximum combinatorial path constraint.
• MAX_DELAY
Identifies all paths defined by the following timing constraints:
– ALLCLOCKNETS
– OFFSET_IN_BEFORE
– OFFSET_OUT_AFTER
– INPAD_TO_OUTPAD

Offset (OFFSET)
The Offset (OFFSET) constraint:
• Is a basic timing constraint.
• Specifies the timing relationship between an external clock and its associated data-in
or data-out pin.
• Is used only for pad-related signals.
• Cannot be used to extend the arrival time specification method to the internal
signals in a design.
• Allows you to:
– Calculate whether a setup time is being violated at a flip-flop whose data and
clock inputs are derived from external nets.
– Specify the delay of an external output net derived from the Q output of an
internal flip-flop being clocked from an external device pin.
Syntax
OFFSET = {IN|OUT} offset_time [units] {BEFORE|AFTER} clk_name [TIMEGRP
group_name];
Period (PERIOD)
The Period (PERIOD) constraint is a basic timing constraint and synthesis constraint.
A clock period specification checks timing between all synchronous elements within the
clock domain as defined in the destination element group. The group may contain paths
that pass between clock domains if the clocks are defined as a function of one or the other.
Syntax
NET netname PERIOD = value [{HIGH|LOW} value];

Timing Name (TNM)

The Timing Name (TNM) constraint:
• Is a basic grouping constraint.
• Identifies the elements that make up a group to be used in a timing specification.
• Tags the following specific elements as members of a group to simplify the
application of timing specifications to the group.
– FF
– RAM
– LATCH
– PAD
– CPU
– BRAM_PORTA
– BRAM_PORTB
– HSIO
– MULT
The RISING and FALLING keywords may be used with TNM constraints.
Syntax
{INST|NET|PIN} inst_net_or_pin_name TNM = [predefined_group:] identifier;
Timing Name on a Net (TNM_NET)

The Timing Name on a Net (TNM_NET) constraint:
• Is essentially equivalent to Timing Name (TNM) on a net except for input pad nets.
Note Special rules apply when using Timing Name on a Net with the Period
(PERIOD) constraint for DLL and DCM components.
PERIOD Specifications on CLKDLLs and DCMs in the Constraints Guide
• Is a property that you normally use in conjunction with a Hardware Description
Language (HDL) design to tag a specific net.
Note All downstream synchronous elements and pads tagged with the Timing
Name on a Net identifier are considered a group.
Syntax
NET netname TNM_NET = [predefined_group:] identifier;
Timegroup (TIMEGRP)
The Timegroup (TIMEGRP) constraint is a basic grouping constraint.
In addition to naming groups using the TNM identifier, you can also define groups in
terms of other groups. You can create a group that is a combination of existing groups
by defining a Timegroup constraint.

Place Timegroup constraints in an XST Constraint File (XCF) or a Netlist Constraints

File (NCF).
Use Timegroup attributes to create groups using the following methods:
• Combining multiple groups into one
• Defining flip-flop subgroups by clock sense
Syntax
TIMEGRP newgroup = existing_grp1 existing_grp2 [existing_grp3 ...];
Timing Ignore (TIG)

The Timing Ignore (TIG) constraint:
• Causes all paths going through a specific net to be ignored for timing analyses and
optimization purposes.
• Can be applied to the name of the signal affected.
Syntax
NET net_name TIG;
Write Timing Constraints (-write_timing_constraints)

The Write Timing Constraints (-write_timing_constraints) command line option
specifies when timing constraints are written to the NGC file.
Timing constraints are written to the NGC file only when:
• Write Timing Constraints is checked yes in ISE® Design Suite in Process > Process
Properties, or
• The -write_timing_constraints option is specified when using the command line.
Timing constraints are not written to the NGC file by default.
Applicable Elements
Propagation Rules
Not applicable.
Syntax
-write_timing_constraints {yes|no}
• yes (default)
• no


XST Command Line

xst run -write_timing_constraints yes
Timing constraints are written to the NGC file.
ISE Design Suite

Process > Process Properties > Synthesis Options > Write Timing Constraints

Chapter 12
XST Implementation Constraints

• Power Mode (PWR_MODE)
• RLOC
Implementation constraints control placement and routing. They are not directly used
by XST, but are propagated and made available to the implementation tools. The object
to which an implementation constraint is attached is preserved.
A binary equivalent of the implementation constraint is written to the NGC file. Since
the file is binary, you cannot edit an implementation constraint in the NGC file.
You can code an implementation constraint in the XST Constraint File (XCF) as
illustrated in Implementation Constraints Syntax Examples.
Implementation Constraints Syntax Examples

This section gives the following Implementation Constraints syntax examples:
• XCF Syntax Examples
• VHDL Syntax Examples
• Verilog Syntax Examples
XCF Syntax Examples

This section gives two XCF Syntax Examples, including, for each example, one for
Method One and one for Method Two.

To apply an implementation constraint to an entire entity, use either of the following
XST Constraint File (XCF) syntaxes:
Method One
MODEL EntityName PropertyName;
Method Two
MODEL EntityName PropertyName=PropertyValue;

To apply an implementation constraint to specific instances, nets, or pins within an
entity, use either of the following syntaxes:

Chapter 12: XST Implementation Constraints
Method One
BEGIN MODEL EntityName {NET|INST|PIN} {NetName|InstName|SigName}
PropertyName;
END;
Method Two
BEGIN MODEL EntityName {NET|INST|PIN} {NetName|InstName|SigName}
PropertyName=Propertyvalue;
END;
VHDL Syntax Examples

Specify implementation constraints in VHDL as follows:
attribute PropertyName of {NetName|InstName|PinName} : {signal|label} is
"PropertyValue";
Verilog Syntax Examples

Specify implementation constraints in Verilog as follows:
// synthesis attribute PropertyName of {NetName|InstName|PinName} is "PropertyValue";
In Verilog-2001, where descriptions precede the signal, module, or instance to which
they refer, specify implementation constraints as follows:
(* PropertyName="PropertyValue" *)
No Reduce (NOREDUCE)
No Reduce (NOREDUCE) prevents the optimization of the Boolean equation generating
a given signal. Assuming a local signal is assigned the arbitrary function below, and No
Reduce attached to the signal s:
signal s : std_logic;
attribute NOREDUCE : boolean;
attribute NOREDUCE of s : signal is "true";
...
s <= a or (a and b);
Specify No Reduce in the XST Constraint File (XCF) as follows:
BEGIN MODEL ENTNAME
NET s NOREDUCE;
NET s KEEP;
END;
XST writes the following statements to the NGC file:
NET s NOREDUCE;
NET s KEEP;

Chapter 12: XST Implementation Constraints
Power Mode (PWR_MODE)

The Power Mode (PWR_MODE) constraint controls the power consumption
characteristics of macrocells.
The following VHDL statement specifies that the function generating signal s should be
optimized for low power consumption:
attribute PWR_MODE : string;
attribute PWR_MODE of s : signal is "LOW";
XST writes the following statement to the NGC file:
NET s PWR_MODE=LOW;
NET s KEEP;
The HDL attribute can be applied to the signal on which XST infers the instance if:
• The attribute applies to an instance, and
• The instance is not available (not instantiated) in the HDL source
Examples of instances include:
• DRIVE
• IOSTANDARD

XCF
MODEL ENTNAME
NET s PWR_MODE=LOW;
NET s KEEP;
END;
RLOC (RLOC)
See:
RLOC (RLOC)

Chapter 13
XST Supported Third Party Constraints

This chapter describes XST Supported Third Party Constraints, and includes:
• XST Equivalents to Third Party Constraints
• Third Party Constraints Syntax Examples
XST Equivalents to Third Party Constraints

This section shows the XST equivalent for each of the third party constraints. For specific
information on these constraints, see the vendor documentation.
Several third party constraints are automatically supported by XST, as shown in the
table below. Constraints marked yes are fully supported. If a constraint is only partially
supported, the support conditions are shown in the Automatic Recognition column.
The following rules apply:
• VHDL uses standard attribute syntax. No changes are needed to the Hardware
Description Language (HDL) code.
• For Verilog with third party meta-comment syntax, the meta-comment syntax must
be changed to conform to XST conventions. The constraint name and its value can
be used as shown in the third party tool.
• For Verilog 2001 attributes, no changes are needed to the HDL code. The constraint
is automatically translated as in the case of VHDL attribute syntax.
XST Equivalents to Third Party Constraints

Automatic
Name Vendor XST Equivalent Recognition Available For
black_box Synopsys BoxType N/A VHDL, Verilog
black_box_pad_pin Synopsys N/A N/A N/A
black_box_tri_pins Synopsys N/A N/A N/A
cell_list Synopsys N/A N/A N/A
clock_list Synopsys N/A N/A N/A
Enum Synopsys N/A N/A N/A
full_case Synopsys Full Case N/A Verilog
ispad Synopsys N/A N/A N/A
map_to_module Synopsys N/A N/A N/A
net_name Synopsys N/A N/A N/A
parallel_case Synopsys Parallel Case N/A Verilog
return_port_name Synopsys N/A N/A N/A

Chapter 13: XST Supported Third Party Constraints
Automatic
resource_sharing Synopsys Resource Sharing N/A VHDL, Verilog
directives
set_dont_touch_networkSynopsys not required N/A N/A
set_dont_touch Synopsys not required N/A N/A
set_dont_use_cel_name Synopsys not required N/A N/A
set_prefer Synopsys N/A N/A N/A
state_vector Synopsys N/A N/A N/A
syn_allow_retiming Synopsys Register Balancing N/A VHDL, Verilog
syn_black_box Synopsys BoxType Yes VHDL, Verilog
syn_direct_enable Synopsys N/A N/A N/A
syn_edif_bit_format Synopsys N/A N/A N/A
syn_edif_scalar_format Synopsys N/A N/A N/A
syn_encoding Synopsys FSM Encoding Yes (The value safe VHDL, Verilog
Algorithm is not supported
for automatic
recognition. Use
Safe Implementation
in XST to activate this
mode.)
syn_enum_encoding Synopsys Enumerated Encoding N/A VHDL
syn_hier Synopsys Keep Hierarchy Yes VHDL, Verilog
syn_hier =
hardrecognized
askeep_hierarchy =
soft
syn_hier =
removerecognized
askeep_hierarchy = no
(XST supports only
the values hard
and remove for
syn_hier in automatic
recognition.)
syn_isclock Synopsys N/A N/A N/A
syn_keep Synopsys Keep Yes (XST preserves the VHDL, Verilog
designated net in the
final netlist, but does
not attach any KEEP
constraint to it.)
syn_maxfan Synopsys Max Fanout Yes VHDL, Verilog
syn_netlist_hierarchy Synopsys Netlist Hierarchy N/A VHDL, Verilog
syn_noarrayports Synopsys N/A N/A N/A
syn_noclockbuf Synopsys Buffer Type Yes VHDL, Verilog
syn_noprune Synopsys Optimize Instantiated Yes VHDL, Verilog
Primitives

Automatic
syn_pipeline Synopsys Register Balancing N/A VHDL, Verilog
syn_preserve Synopsys Equivalent Register Yes VHDL, Verilog
Removal
syn_ramstyle Synopsys ram_extract and Yes VHDL, Verilog
ram_style
XST implements
RAMs in
no_rw_check
mode regardless
if no_rw_check is
specified or not
the area value is
ignored
syn_reference_clock Synopsys N/A N/A N/A
syn_replicate Synopsys Register Duplication Yes VHDL, Verilog
syn_romstyle Synopsys rom_extract and Yes VHDL, Verilog
rom_style
syn_sharing Synopsys N/A N/A VHDL, Verilog
syn_state_machine Synopsys Automatic FSM Yes VHDL, Verilog
Extraction
syn_tco <n> Synopsys N/A N/A N/A
syn_tpd <n> Synopsys N/A N/A N/A
syn_tristate Synopsys N/A N/A N/A
syn_tristatetomux Synopsys N/A N/A N/A
syn_tsu <n> Synopsys N/A N/A N/A
syn_useenables Synopsys N/A N/A N/A
syn_useioff Synopsys Pack I/O Registers Into N/A VHDL, Verilog
IOBs
synthesis translate_off Synopsys Translate Off Yes VHDL, Verilog
synthesis translate_on Translate On
xc_alias Synopsys N/A N/A N/A
xc_clockbuftype Synopsys Buffer Type N/A VHDL, Verilog
xc_fast Synopsys FAST N/A VHDL, Verilog
xc_fast_auto Synopsys FAST N/A VHDL, Verilog
xc_global_buffers Synopsys BUFG (XST) N/A VHDL, Verilog
xc_ioff Synopsys Pack I/O Registers Into N/A VHDL, Verilog
IOBs
xc_isgsr Synopsys N/A N/A N/A
xc_loc Synopsys LOC Yes VHDL, Verilog
xc_map Synopsys LUT_MAP Yes (XST supports VHDL, Verilog
only the value
lut for automatic
recognition.)
xc_ncf_auto_relax Synopsys N/A N/A N/A

Automatic
xc_nodelay Synopsys NODELAY N/A VHDL, Verilog
xc_padtype Synopsys I/O Standard N/A VHDL, Verilog
xc_props Synopsys N/A N/A N/A
xc_pullup Synopsys PULLUP N/A VHDL, Verilog
xc_rloc Synopsys RLOC Yes VHDL, Verilog
xc_fast Synopsys FAST N/A VHDL, Verilog
xc_slow Synopsys N/A N/A N/A
xc_uset Synopsys U_SET Yes VHDL, Verilog
Third Party Constraints Syntax Examples

The following third party constraints syntax examples are the only ways to:
• Preserve a signal/net in a Hardware Description Language (HDL) design, and
• Prevent optimization on the signal or net during synthesis
Third Party Constraints Verilog Syntax Example

module testkeep (in1, in2, out1);
input in1;
input in2;
output out1;
(* keep = "yes" *) wire aux1;
(* keep = "yes" *) wire aux2;
assign aux1 = in1;
assign aux2 = in2;
assign out1 = aux1 & aux2;
endmodule
Third Party Constraints XCF Syntax Example
Keep (KEEP) can also be applied through the separate synthesis constraint file:
BEGIN MODEL testkeep
NET aux1 KEEP=true;
END;

Chapter 14
XST VHDL Language Support

This chapter:
• Explains how XST supports the VHSIC Hardware Description Language (VHDL)
• Provides details on VHDL supported constructs and synthesis options
• VHDL Logic Descriptions
• VHDL IEEE Support
• VHDL File Type Support
• VHDL Debugging Using Write Operation
• VHDL Data Types
• VHDL Record Types
• VHDL Initial Values
• VHDL Objects
• VHDL Operators
• VHDL Entity and Architecture Descriptions
• VHDL Combinatorial Circuits
• VHDL Sequential Circuits
• VHDL Functions and Procedures
• VHDL Assert Statements
• VHDL Models Defined Using Packages
• VHDL Constructs Supported in XST
• VHDL Reserved Words
VHDL Logic Descriptions

VHDL offers a broad set of constructs for compactly describing complicated logic:
• Allows the description of the structure of a system:
– How it is decomposed into subsystems
– How those subsystems are interconnected
• Allows the specification of the function of a system using familiar programming
language forms.
• Allows the design of a system to be simulated before being implemented and
manufactured. This feature allows you to test for correctness without the delay
and expense of hardware prototyping.
• Provides a mechanism for easily producing a detailed, device-dependent version of
a design to be synthesized from a more abstract specification. This feature allows

Chapter 14: XST VHDL Language Support
you to concentrate on more strategic design decisions, and reduce the overall time to
market for the design.
• IEEE VHDL Language Reference Manual
• XST Design Constraints
• VHDL Attribute Syntax
VHDL IEEE Support

This section discusses VHDL IEEE Support, and includes:
• Supported VHDL IEEE Standards
• VHDL IEEE Conflicts
• Non-LRM Compliant Constructs in VHDL
Supported VHDL IEEE Standards

XST supports the following VHDL IEEE standards:
• Std 1076-1987
• Std 1076-1993
• Std 1076-2006
Note Std 1076-2006 is only partially implemented. XST allows instantiation for Std
1076-2006 as shown in the following table.
Formal Port Associated Actual
buffer out
out buffer
VHDL IEEE Conflicts

VHDL IEEE Std 1076-1987 constructs are accepted if they do not conflict with VHDL
IEEE Std 1076-1993. In case of a conflict, Std 1076-1993 behavior overrides Std 1076-1987.
In cases where:
• Std 1076-1993 requires a construct to be an erroneous case, but
• Std 1076-1987 accepts it,
XST issues a warning instead of an error. An error would stop analysis.
VHDL IEEE Conflict Example

Following is an example of a VHDL IEEE conflict:
• Std 1076-1993 requires an impure function to use the impure keyword while
declaring a function.
• Std 1076-1987 has no such requirement.
In this case, XST:
• Accepts the VHDL code written for Std 1076-1987
• Issues a warning stating Std 1076-1993 behavior

Non-LRM Compliant Constructs in VHDL

XST supports some non-LRM compliant constructs. XST supports a specific non-LRM
compliant construct when:
• A majority of synthesis or simulation third-party tools support the construct, and
• It is a real language limitation for design coding, and has no impact on quality of
results or problem detection in the design.
For example, the LRM does not allow instantiation when the formal port is a buffer and
the effective one is an out (and vice-versa).
VHDL File Type Support

XST supports a limited File Read and File Write capability for VHDL as shown in the
following table.
Capability Usage Examples
File Read Initialize RAMs from an external file
File Write • Debug processes
• Write a specific constant or generic value to an external file

Use any of the read functions shown in the following table. These read functions are
supported by the following packages:
• standard
• std.textio
• ieee.std_logic_textio
Function Package
file (type text only) standard
access (type line only) standard
file_open (file, name, open_kind) standard
file_close (file) standard
endfile (file) standard
text std.textio
line std.textio
width std.textio
readline (text, line) std.textio
readline (line, bit, boolean) std.textio
read (line, bit) std.textio
readline (line, bit_vector, boolean) std.textio
read (line, bit_vector) std.textio
read (line, boolean, boolean) std.textio
read (line, boolean) std.textio
read (line, character, boolean) std.textio

Function Package
read (line, character) std.textio
read (line, string, boolean) std.textio
read (line, string) std.textio
write (file, line) std.textio
write (line, bit, boolean) std.textio
write (line, bit) std.textio
write (line, bit_vector, boolean) std.textio
write (line, bit_vector) std.textio
write (line, boolean, boolean) std.textio
write (line, boolean) std.textio
write (line, character, boolean) std.textio
write (line, character) std.textio
write (line, integer, boolean) std.textio
write (line, integer) std.textio
write (line, string, boolean) std.textio
write (line, string) std.textio
read (line, std_ulogic, boolean) ieee.std_logic_textio
read (line, std_ulogic) ieee.std_logic_textio
read (line, std_ulogic_vector), boolean ieee.std_logic_textio
read (line, std_ulogic_vector) ieee.std_logic_textio
read (line, std_logic_vector, boolean) ieee.std_logic_textio
read (line, std_logic_vector) ieee.std_logic_textio
write (line, std_ulogic, boolean) ieee.std_logic_textio
write (line, std_ulogic) ieee.std_logic_textio
write (line, std_ulogic_vector, boolean) ieee.std_logic_textio
write (line, std_ulogic_vector) ieee.std_logic_textio
write (line, std_logic_vector, boolean) ieee.std_logic_textio
write (line, std_logic_vector) ieee.std_logic_textio
hread ieee.std_logic_textio
VHDL Debugging Using Write Operation

This section discusses VHDL Debugging Using Write Operation, and includes:
• Rules for Debugging
• Using the Endfile Function

Rules for Debugging

Follow these rules for debugging using write operation in VHDL:
• During a std_logic read operation, the only allowed characters are 0 and 1. Other
values such as X and Z are not allowed. XST rejects the design if the file includes
characters other than 0 and 1, except that XST ignores a blank space character.
• Do not use identical names for files placed in different directories.
• Do not use conditional calls to read procedures, as shown in the following coding
example.
if SEL = ’1’ then
read (MY_LINE, A(3 downto 0));
else
read (MY_LINE, A(1 downto 0));
end if;
Using the Endfile Function

XST rejects the design if you use the following description style with the endfile function:
while (not endfile (MY_FILE)) loop
readline (MY_FILE, MY_LINE);
read (MY_LINE, MY_DATA);
end loop;
XST issues the following error message:
Line <MY_LINE> has not enough elements for target <MY_DATA>.
To fix the problem, add exit when endfile (MY_FILE); to the while loop.
while (not endfile (MY_FILE)) loop
readline (MY_FILE, MY_LINE);
exit when endfile (MY_FILE);
read (MY_LINE, MY_DATA);
end loop;

Coding Example
--
-- Print 2 constants to the output file
--
library IEEE;
use IEEE.STD_LOGIC_arith.ALL;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_TEXTIO.all;
entity file_support_1 is
generic (data_width: integer:= 4);
port( clk, sel: in std_logic;
din: in std_logic_vector (data_width - 1 downto 0);
dout: out std_logic_vector (data_width - 1 downto 0));
end file_support_1;
architecture Behavioral of file_support_1 is

file results : text is out "test.dat";
constant base_const: std_logic_vector(data_width - 1 downto 0):= conv_std_logic_vector(3,data_width);
constant new_const: std_logic_vector(data_width - 1 downto 0):= base_const + "1000";
begin
process(clk)
variable txtline : LINE;
begin
write(txtline,string’("--------------------"));
writeline(results, txtline);
write(txtline,string’("Base Const: "));
write(txtline,base_const);
write(txtline,string’("New Const: "));

write(txtline,new_const);
write(txtline,string’("--------------------"));

if (sel = ’1’) then
dout <= new_const;
else
dout <= din;
end if;
end if;
end process;
end Behavioral;

VHDL Data Types

This section discusses VHDL Data Types, and includes:
• Accepted VHDL Data Types
• VHDL Overloaded Data Types
• VHDL Multi-Dimensional Array Types
Accepted VHDL Data Types

XST accepts the following VHDL data types:
• VHDL Enumerated Types
• VHDL User-Defined Enumerated Types
• VHDL Bit Vector Types
• VHDL Integer Types
• VHDL Predefined Types
• VHDL STD_LOGIC_1164 IEEE Types
VHDL Enumerated Types

Type Values Meaning Comment
BIT 0, 1 -- --
BOOLEAN false, true -- --
REAL $-. to $+. -- --
STD_LOGIC U unitialized Not accepted by XST

X unknown Treated as don’t care
0 low Treated identically to L
1 high Treated identically to H
Z high impedance Treated as high impedance
W weak unknown Not accepted by XST
L weak low Treated identically to 0
H weak high Treated identically to 1
- don’t care Treated as don’t care
VHDL User-Defined Enumerated Types

type COLOR is (RED, GREEN, YELLOW) ;
VHDL Bit Vector Types

• BIT_VECTOR
• STD_LOGIC_VECTOR
VHDL Integer Types

INTEGER

VHDL Predefined Types

• BIT
• BOOLEAN
• BIT_VECTOR
• INTEGER
• REAL
VHDL STD_LOGIC_1164 IEEE Types

The following types are declared in the STD_LOGIC_1164 IEEE package:
• STD_LOGIC
This package is compiled in the IEEE library. To use one of these types, add the following
two lines to the VHDL specification:
library IEEE; use IEEE.STD_LOGIC_1164.all;
VHDL Overloaded Data Types

The following data types can be overloaded:
• VHDL Overloaded Enumerated Types
• VHDL Overloaded Bit Vector Types
• VHDL Overloaded Integer Types
• VHDL Overloaded STD_LOGIC_1164 IEEE Types
• VHDL Overloaded STD_LOGIC_ARITH IEEE Types
VHDL Overloaded Enumerated Types

• STD_ULOGIC
Contains the same nine values as the STD_LOGIC type, but does not contain
predefined resolution functions
• X01
Subtype of STD_ULOGIC containing the X, 0 and 1 values
• X01Z
Subtype of STD_ULOGIC containing the X, 0, 1 and Z values
• UX01
Subtype of STD_ULOGIC containing the U, X, 0 and 1 values
• UX01Z
Subtype of STD_ULOGIC containing the U, X, 0, 1, and Z values
VHDL Overloaded Bit Vector Types

• STD_ULOGIC_VECTOR
• UNSIGNED
• SIGNED
Unconstrained types (types whose length is not defined) are not accepted.

VHDL Overloaded Integer Types

• NATURAL
• POSITIVE
Any integer type within a user-defined range. For example:
type MSB is range 8 to 15;
means any integer:
• greater than 7, or
• less than 16
The types NATURAL and POSITIVE are VHDL predefined types.
VHDL Overloaded STD_LOGIC_1164 IEEE Types

The following types are declared in the STD_LOGIC_1164 IEEE package:
• STD_ULOGIC (and subtypes X01, X01Z, UX01, UX01Z)
• STD_LOGIC
• STD_ULOGIC_VECTOR
This package is compiled in the library IEEE. To use one of these types, add the following
two lines to the VHDL specification:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
VHDL Overloaded STD_LOGIC_ARITH IEEE Types

The types UNSIGNED and SIGNED (defined as an array of STD_LOGIC) are declared
in the STD_LOGIC_ARITH IEEE package.
This package is compiled in the library IEEE. To use these types, add the following two
lines to the VHDL specification:
library IEEE;
use IEEE.STD_LOGIC_ARITH.all;
VHDL Multi-Dimensional Array Types

XST supports multi-dimensional array types of up to three dimensions. BRAMs are not
inferred. Arrays can be:
• Signals
• Constants
• VHDL variables
You can do assignments and arithmetic operations with arrays. You can also pass
multi-dimensional arrays to functions, and use them in instantiations.
Coding Example One

The array must be fully constrained in all dimensions, as shown in the following coding
example.
subtype WORD8 is STD_LOGIC_VECTOR (7 downto 0);
type TAB12 is array (11 downto 0) of WORD8;
type TAB03 is array (2 downto 0) of TAB12;

Coding Example Two

You can also declare an array as a matrix, as shown in the following coding example.
subtype TAB13 is array (7 downto 0,4 downto 0) of
STD_LOGIC_VECTOR (8 downto 0);
Consider the following declarations:
subtype WORD8 is STD_LOGIC_VECTOR (7 downto 0);
type TAB05 is array (4 downto 0) of WORD8;
type TAB03 is array (2 downto 0) of TAB05;
signal WORD_A : WORD8;

signal TAB_A, TAB_B : TAB05;
signal TAB_C, TAB_D : TAB03;
constant CNST_A : TAB03 := (
("00000000","01000001","01000010","10000011","00001100"),
("00100000","00100001","00101010","10100011","00101100"),
("01000010","01000010","01000100","01000111","01000100"));
The following can now be specified:

• A multi-dimensional array signal or variable
TAB_A <= TAB_B; TAB_C <= TAB_D; TAB_C <= CNST_A;
• An index of one array

TAB_A (5) <= WORD_A; TAB_C (1) <= TAB_A;
• Indexes of the maximum number of dimensions

TAB_A (5) (0) <= ’1’; TAB_C (2) (5) (0) <= ’0’
• A slice of the first array

TAB_A (4 downto 1) <= TAB_B (3 downto 0);
• An index of a higher level array and a slice of a lower level array:

TAB_C (2) (5) (3 downto 0) <= TAB_B (3) (4 downto 1); TAB_D
(0) (4) (2 downto 0) <= CNST_A (5 downto 3)
Coding Example Three

Add the following declaration:
subtype MATRIX15 is array(4 downto 0, 2 downto 0) of
STD_LOGIC_VECTOR (7 downto 0); signal MATRIX_A : MATRIX15;

The following can now be specified:

• A multi-dimensional array signal or variable
MATRIXA <= CNST_A;
• An index of one row of the array
MATRIXA (5) <= TAB_A;
• Indexes of the maximum number of dimensions

MATRIXA (5,0) (0) <= ’1’;
Indexes may be variable.
VHDL Record Types

XST supports VHDL record types, as shown in the following Coding Example.
• Record types can contain other record types.
• Constants can be record types.
• Record types cannot contain attributes.
• XST supports aggregate assignments to record signals.
Coding Example
type REC1 is record
field1: std_logic;
field2: std_logic_vector (3 downto 0)
end record;
VHDL Initial Values

This section discusses VHDL Initial Values, and includes:
• Initializing Registers
• VHDL Local Reset/Global Reset
• Default Initial Values on Memory Elements in VHDL
Initializing Registers
In VHDL, you can initialize registers when you declare them.
The value:
• Is a constant
• Cannot depend on earlier initial values
• Cannot be a function or task call
• Can be a parameter value propagated to a register

Coding Example One

When you give a register an initial value in a declaration, XST sets this value:
• On the output of the register at global reset, or
• At power up
The assigned value:
• Is carried in the NGC file as an INIT attribute on the register
• Is independent of any local reset
signal arb_onebit : std_logic := ’0’;
signal arb_priority : std_logic_vector(3 downto 0) := "1011";
Coding Example Two
You can also assign a set/reset value to a register in behavioral VHDL code. Assign a
value to a register when the register reset line goes to the appropriate value.
process (clk, rst)
begin
if rst=’1’ then
arb_onebit <= ’0’;
end if;
end process;
When you set the initial value of a variable in the behavioral code, it is implemented in
the design as a flip-flop whose output can be controlled by a local reset. As such, it is
carried in the NGC file as an FDP or FDC flip-flop.
VHDL Local Reset/Global Reset

Local reset is independent of global reset. Registers controlled by a local reset may be set
to a different value from registers whose value is only reset at global reset (power up).
In the following coding example, the register arb_onebit is set to 1 at global reset, but
a pulse on the local reset (rst) can change its value to 0.
Local Reset/Global Reset VHDL Coding Example

The following coding example sets the initial value on the register output to 1 (one) at
initial power up, but since this is dependent upon a local reset, the value changes to 0
(zero) whenever the local set/reset is activated.
entity top is
Port (
clk, rst : in std_logic;
a_in : in std_logic;
dout : out std_logic);
end top;
architecture Behavioral of top is
signal arb_onebit : std_logic := ’1’;
begin
process (clk, rst)
begin
if rst=’1’ then
arb_onebit <= ’0’;
elsif (clk’event and clk=’1’) then
arb_onebit <= a_in;
end if;

end process;
dout <= arb_onebit;

end Behavioral;
Default Initial Values on Memory Elements in VHDL

Because every memory element in a Xilinx® FPGA device must come up in a known
state, in certain cases, XST does not use IEEE standards for initial values. In the Local
Reset/Global Reset VHDL Coding Example, if signal arb_onebit were not initialized
to 1 (one), XST would assign it a default of 0 (zero) as its initial state. In this case, XST
does not follow the IEEE standard, where U is the default for std_logic. This process of
initialization is the same for both registers and RAMs.
Where possible, XST adheres to the IEEE VHDL standard when initializing signal
values. If no initial values are supplied in the VHDL code, XST uses the default values
(where possible) as shown in the XST column in the following table.
Type IEEE XST
bit ’0’ ’0’
std_logic ’U’ ’0’
bit_vector (3 downto 0) 0000 0000
std_logic_vector (3 downto 0) 0000 0000
integer (unconstrained) integer’left integer’left
integer range 7 downto 0 integer’left = 7 integer’left = 7 (coded as 111)
integer range 0 to 7 integer’left = 0 integer’left = 0 (coded as 000)
Boolean FALSE FALSE (coded as 0)
enum(S0,S1,S2,S3) type’left = S0 type’left = S0 (coded as 000)
Unconnected output ports default to the values shown in the XST column of VHDL
Initial Values. If the output port has an initial condition, XST ties the unconnected
output port to the explicitly defined initial condition. According to the IEEE VHDL
specification, input ports cannot be left unconnected. As a result, XST issues an error
message if an input port is not connected. Even the open keyword is not sufficient
for an unconnected input port.

VHDL Objects
This section discusses VHDL Objects, and include:
• Signals in VHDL
• Variables in VHDL
• Constants in VHDL
Signals in VHDL
Signals in VHDL can be:
• Declared in an architecture declarative part.
• Used anywhere within the architecture.
• Declared in a block.
• Used within that block.
• Assigned by the assignment operator <=.
Coding Example
signal sig1 : std_logic; sig1 <= ’1’;
Variables in VHDL
Variables in VHDL:
• Are declared in a process or a subprogram.
• Are used within that process or that subprogram.
• Can be assigned by the assignment operator:
:=
Coding Example
variable var1 : std_logic_vector (7 downto 0); var1 := "01010011";
Constants in VHDL
Constants in VHDL:
• Can be declared in any declarative region.
• Can be used within that region.
• Cannot have their values be changed once declared.
Coding Example
signal sig1 : std_logic_vector (5 downto 0);
constant init0 : std_logic_vector (5 downto 0) := "010111";
sig1 <= init0;

VHDL Operators
Supported operators are listed in VHDL Expressions. This section provides coding
examples for each shift operator.
Shift Left Logical VHDL Coding Example

sll (Shift Left Logical) sig1 <= A(4 downto 0) sll 2
logically equivalent to:
sig1 <= A(2 downto 0) & "00";
Shift Right Logical VHDL Coding Example
srl (Shift Right Logical) sig1 <= A(4 downto 0) srl 2
sig1 <= "00" & A(4 downto 2);
Shift Left Arithmetic VHDL Coding Example
sla (Shift Left Arithmetic) sig1 <= A(4 downto 0) sla 2
sig1 <= A(2 downto 0) & A(0) & A(0);
Shift Right Arithmetic VHDL Coding Example
sra (Shift Right Arithmetic) sig1 <= A(4 downto 0) sra 2
sig1 <= <= A(4) & A(4) & A(4 downto 2);
Rotate Left VHDL Coding Example
rol (Rotate Left) sig1 <= A(4 downto 0) rol 2
sig1 <= A(2 downto 0) & A(4 downto 3);
Rotate Right VHDL Coding Example
ror (Rotate Right) A(4 downto 0) ror 2
sig1 <= A(1 downto 0) & A(4 downto 2);

VHDL Entity and Architecture Descriptions

VHDL entity and architecture descriptions include:
• Circuit Descriptions
• Entity Declarations
• Architecture Declarations
• Component Instantiation
• Recursive Component Instantiation
• Component Configuration
• Generic Parameter Declarations
• Generic and Attribute Conflict
VHDL Circuit Descriptions

A circuit description in VHDL consists of two parts:
• The interface (defining the I/O ports)
• The body
In VHDL:
• The entity corresponds to the interface
• The architecture describes the behavior
VHDL Entity Declarations

The I/O ports of the circuit are declared in the entity. Each port has:
• A name
• A mode
– in
– out
– inout
– buffer
• A type (one of the following ports in the Entity and Architecture Declaration VHDL
Coding Example)
– A
– B
– C
– D
– E
Not more than one-dimensional array types are accepted as ports.
VHDL Architecture Declarations

Internal signals may be declared in the architecture. Each internal signal has:
• A name
• A type
Signal T as shown below in the following coding example

Coding Example
Library IEEE;
entity EXAMPLE is
port (
A,B,C : in std_logic;
D,E : out std_logic );
end EXAMPLE;
architecture ARCHI of EXAMPLE is

signal T : std_logic;
begin
...
end ARCHI;
VHDL Component Instantiation

Structural descriptions assemble several blocks, and allow the introduction of hierarchy
in a design.
Concept Description
Component Building or basic block
Port Component I/O connector
Signal Corresponds to a wire between components
In VHDL, a component is represented by a design entity. The design entity is a

composite consisting of the concepts shown in the following table.
Concept View Describes
Entity declaration External What can be seen from
the outside, including the
component ports
Architecture body Internal The behavior or the structure
of the component
The connections between components are specified within component instantiation

statements. These statements specify an instance of a component occurring inside an
architecture of another component. Each component instantiation statement is labeled
with an identifier.
Besides naming a component declared in a local component declaration, a component
instantiation statement contains an association list -- the parenthesized list following the
reserved word port map. The association list specifies which actual signals or ports are
associated with which local ports of the component declaration.
XST supports unconstrained vectors in component declarations.

Coding Example
The following coding example shows the structural description of a half adder
composed of four nand2 components:
entity NAND2 is
port (
A,B : in BIT;
Y : out BIT );
end NAND2;
architecture ARCHI of NAND2 is

begin
Y <= A nand B;
end ARCHI;
entity HALFADDER is
port (
X,Y : in BIT;
C,S : out BIT );
end HALFADDER;
architecture ARCHI of HALFADDER is

component NAND2
port (
A,B : in BIT;
Y : out BIT );
end component;
for all : NAND2 use entity work.NAND2(ARCHI);

signal S1, S2, S3 : BIT;
begin
NANDA : NAND2 port map (X,Y,S3);
NANDB : NAND2 port map (X,S3,S1);
NANDC : NAND2 port map (S3,Y,S2);
NANDD : NAND2 port map (S1,S2,S);
C <= S3;
end ARCHI;
Synthesized Top Level Netlist Diagram

VHDL Recursive Component Instantiation

XST supports recursive component instantiation. Direct instantiation is not supported
for recursion. To prevent endless recursive calls, the number of recursions is limited
by default to 64. Use -recursion_iteration_limit to control the number of allowed
recursive calls.
4-Bit Shift Register With Recursive Component Instantiation VHDL Coding

Example
library ieee;
library unisim;
entity single_stage is
generic (sh_st: integer:=4);
port (
CLK : in std_logic;
DI : in std_logic;
DO : out std_logic );
end entity single_stage;
architecture recursive of single_stage is

component single_stage
generic (sh_st: integer);
port (
CLK : in std_logic;
DI : in std_logic;
DO : out std_logic );
end component;
signal tmp : std_logic;
begin
GEN_FD_LAST: if sh_st=1 generate
inst_fd: FD port map (D=>DI, C=>CLK, Q=>DO);
end generate;
GEN_FD_INTERM: if sh_st /= 1 generate
inst_fd: FD port map (D=>DI, C=>CLK, Q=>tmp);
inst_sstage: single_stage generic map (sh_st => sh_st-1)
port map (DI=>tmp, CLK=>CLK, DO=>DO);
end generate;
end recursive;
VHDL Component Configuration

Associating an entity and architecture pair to a component instance provides the means
of linking components with the appropriate model (entity and architecture pair).
XST supports component configuration in the declarative part of the architecture:
for instantiation_list: component_name use LibName.entity_Name(Architecture_Name);
Coding Example
The following coding example shows how to use a configuration clause for component
instantiation. The example contains a for all statement.
for all : NAND2 use entity work.NAND2(ARCHI);

This statement indicates that all NAND2 components use the entity NAND2 and
Architecture ARCHI.
When the configuration clause is missing for a component instantiation, XST links the
component to the entity with the same name (and same interface) and the selected
architecture to the most recently compiled architecture. If no entity or architecture is
found, a black box is generated during synthesis.
In command line mode, you may also use a dedicated configuration declaration to link
component instantiations in your design to design entities and architectures. In this case,
the value of the mandatory Top Module Name (-top) option in the run command is the
configuration name instead of the top level entity name.
VHDL Generic Parameter Declarations

The Generics (-generics) VHDL command line option allows you to redefine generics
values defined in the top-level design block. This allows you to easily modify the
design configuration without any Hardware Description Language (HDL) source
modifications, such as for IP core generation and testing flows.
Generic parameters may be declared in the entity declaration part. XST supports all
types for generics including, for example:
• Integer
• Boolean
• String
• Real
An example of using generic parameters is setting the width of the design.
Coding Example
By describing circuits with generic ports, the same component can be instantiated
repeatedly with different values of generic ports as shown in the following coding
example.
Library IEEE;
entity addern is
generic (width : integer := 8);
port (
A,B : in std_logic_vector (width-1 downto 0);
Y : out std_logic_vector (width-1 downto 0) );
end addern;
architecture bhv of addern is

begin
Y <= A + B;
end bhv;
Library IEEE;
entity top is
port (
X, Y, Z : in std_logic_vector (12 downto 0);

S :out std_logic_vector (16 downto 0) );

end top;
architecture bhv of top is

component addern
generic (width : integer := 8);
port (
A,B : in std_logic_vector (width-1 downto 0);
Y : out std_logic_vector (width-1 downto 0) );
end component;
for all : addern use entity work.addern(bhv);

signal C1 : std_logic_vector (12 downto 0);
signal C2, C3 : std_logic_vector (16 downto 0);
begin
U1 : addern generic map (n=>13) port map (X,Y,C1);
C2 <= C1 & A;
C3 <= Z & B;
U2 : addern generic map (n=>17) port map (C2,C3,S);
end bhv;
VHDL Generic and Attribute Conflicts

Since generics and attributes can be applied to both instances and components in the
VHDL code, and attributes can also be specified in a constraints file, from time to time,
conflicts may arise. To resolve these conflicts, XST uses the following rules of precedence:
1. Whatever is specified on an instance (lower level) takes precedence over what is
specified on a component (higher level).
2. If a generic and an attribute are specified on either the same instance or the same
component, the generic takes precedence, and XST issues a message warning of the
conflict.
3. An attribute specified in the XST Constraint File (XCF) always takes precedence over
attributes or generics specified in the VHDL code.
When an attribute specified on an instance overrides a generic specified on a component
in XST, it is possible that your simulation tool may nevertheless use the generic. This
may cause the simulation results to not match the synthesis results.
Precedence in VHDL
Generic on an Instance Generic on a Component
Attribute on an Instance Apply Generic (XST issues Apply Attribute (possible
warning) simulation mismatch)
Attribute on a Component Apply Generic Apply Generic (XST issues
warning)
Attribute in XCF Apply Attribute XST issues Apply Attribute
warning)
Security attributes on the block definition always have higher precedence than any
other attribute or generic.

VHDL Combinatorial Circuits

XST supports the following VHDL combinatorial circuits:
• Concurrent Signal Assignments
• Generate Statements
• Combinatorial Processes
• If...Else Statements
• Case Statements
• For...Loop Statements
VHDL Concurrent Signal Assignments

Combinatorial logic in VHDL may be described using concurrent signal assignments.
These can be defined within the body of the architecture. VHDL offers three types of
concurrent signal assignments:
• Simple
• Selected
• Conditional
You can describe as many concurrent statements as needed. The order of concurrent
signal definition in the architecture is irrelevant.
A concurrent assignment consists of two sides:
• Left-hand
• Right-hand
The assignment changes when any signal in the right side changes. In this case, the
result is assigned to the signal on the left side.
Simple Signal Assignment VHDL Coding Example

T <= A and B;
MUX Description Using Selected Signal Assignment VHDL Coding Example
library IEEE;
entity select_bhv is
generic (width: integer := 8);
port (
a, b, c, d : in std_logic_vector (width-1 downto 0);
selector : in std_logic_vector (1 downto 0);
T : out std_logic_vector (width-1 downto 0) );
end select_bhv;
architecture bhv of select_bhv is

begin
with selector select
T <= a when "00",
b when "01",
c when "10",
d when others;
end bhv;

MUX Description Using Conditional Signal Assignment VHDL Coding

Example
entity when_ent is
generic (width: integer := 8);
port (
a, b, c, d : in std_logic_vector (width-1 downto 0);
selector : in std_logic_vector (1 downto 0);
T : out std_logic_vector (width-1 downto 0) );
end when_ent;
architecture bhv of when_ent is

begin
T <= a when selector = "00" else
b when selector = "01" else
c when selector = "10" else
d;
end bhv;
VHDL Generate Statements

Repetitive structures are declared with the generate VHDL statement. For this purpose,
for I in 1 to N generate means that the bit slice description is repeated N times.
8-Bit Adder Described With For...Generate Statement VHDL Coding

Example
The following coding example describes an 8-bit adder by declaring the bit slice
structure.
entity EXAMPLE is
port (
A,B : in BIT_VECTOR (0 to 7);
CIN : in BIT;
SUM : out BIT_VECTOR (0 to 7);
COUT : out BIT );
end EXAMPLE;

signal C : BIT_VECTOR (0 to 8);
begin
C(0) <= CIN;
COUT <= C(8);
LOOP_ADD : for I in 0 to 7 generate
SUM(I) <= A(I) xor B(I) xor C(I);
C(I+1) <= (A(I) and B(I)) or (A(I) and C(I)) or (B(I) and C(I));
end generate;
end ARCHI;

N-Bit Adder Described With If...Generate and For… Generate Statement

VHDL Coding Example
XST supports the if condition generate statement for static (non-dynamic) conditions.
The following coding example shows a generic N-bit adder with a width ranging
between 4 and 32.
entity EXAMPLE is
generic (N : INTEGER := 8);
port (
A,B : in BIT_VECTOR (N downto 0);
CIN : in BIT;
SUM : out BIT_VECTOR (N downto 0);
COUT : out BIT );
end EXAMPLE;

signal C : BIT_VECTOR (N+1 downto 0);
begin
L1: if (N>=4 and N<=32) generate
C(0) <= CIN;
COUT <= C(N+1);
LOOP_ADD : for I in 0 to N generate
SUM(I) <= A(I) xor B(I) xor C(I);
C(I+1) <= (A(I) and B(I)) or (A(I) and C(I)) or (B(I) and C(I));
end generate;
end generate;
end ARCHI;
VHDL Combinatorial Processes

A process assigns values to signals differently than when using concurrent signal
assignments. The value assignments are made in a sequential mode. Later assignments
may cancel previous ones. See Assignments in a Process VHDL Coding Example. First the
signal S is assigned to 0, but later on (for (A and B) =1), the value for S is changed to 1.
A process is combinatorial when its inferred hardware does not involve any memory
elements. Said differently, when all assigned signals in a process are always explicitly
assigned in all paths of the Process statements, the process is combinatorial.
A combinatorial process has a sensitivity list appearing within parentheses after the
word process. A process is activated if an event (value change) appears on one of the
sensitivity list signals. For a combinatorial process, this sensitivity list must contain:
• All signals in conditions (for example, if and case)
• All signals on the right-hand side of an assignment
If one or more signals are missing from the sensitivity list, XST issues a warning message
for the missing signals and adds them to the sensitivity list. In this case, the result of the
synthesis may be different from the initial design specification.
A process may contain local variables. The variables are handled in a similar manner
as signals (but are not, of course, outputs to the design).
In Combinatorial Process VHDL Coding Example One, a variable named AUX is declared in
the declarative part of the process, and is assigned to a value (with :=) in the statement
part of the process.
In combinatorial processes, if a signal is not explicitly assigned in all branches of if or
case statements, XST generates a latch to hold the last value. To avoid latch creation,
ensure that all assigned signals in a combinatorial process are always explicitly assigned
in all paths of the Process statements.

Different statements can be used in a process:

• Variable and signal assignment
• If statement
• Case statement
• For...Loop statement
• Function and procedure call
Assignments in a Process VHDL Coding Example

entity EXAMPLE is
port (
A, B : in BIT;
S : out BIT );
end EXAMPLE;

begin
process (A, B)
begin
S <= ’0’ ;
if ((A and B) = ’1’) then
S <= ’1’ ;
end if;
end process;
end ARCHI;
Coding Example One
library ASYL;
use ASYL.ARITH.all;
entity ADDSUB is
port (
A,B : in BIT_VECTOR (3 downto 0);
ADD_SUB : in BIT;
S : out BIT_VECTOR (3 downto 0) );
end ADDSUB;
architecture ARCHI of ADDSUB is

begin
process (A, B, ADD_SUB)
variable AUX : BIT_VECTOR (3 downto 0);
begin
if ADD_SUB = ’1’ then
AUX := A + B ;
else
AUX := A - B ;
end if;
S <= AUX;
end process;
end ARCHI;

Coding Example Two

entity EXAMPLE is
port (
A, B : in BIT;
S : out BIT );
end EXAMPLE;

begin
process (A,B)
variable X, Y : BIT;
begin
X := A and B;
Y := B and A;
if X = Y then
S <= ’1’ ;
end if;
end process;
end ARCHI;
VHDL If...Else Statements

If...else statements:
• Use true and false conditions to execute statements.
• May be nested.
• May be executed in a block of multiple statements using begin and end keywords.
Expression Evaluates To Statement Executed

true First statement
false else statement
x else statement
z else statement
Coding Example
library IEEE;
entity mux4 is
port (
a, b, c, d : in std_logic_vector (7 downto 0);
sel1, sel2 : in std_logic;
outmux : out std_logic_vector (7 downto 0));
end mux4;
architecture behavior of mux4 is

begin
process (a, b, c, d, sel1, sel2)
begin
if (sel1 = ’1’) then
outmux <= a;
else
outmux <= b;

end if;
else
outmux <= c;
else
outmux <= d;
end if;
end if;
end process;
end behavior;
VHDL Case Statements

Case statements perform a comparison to an expression to evaluate one of a number
of parallel branches. The case statement evaluates the branches in the order they are
written. The first branch that evaluates to true is executed. If none of the branches
match, the default branch is executed.
VHDL Case Statement Coding Example

library IEEE;
entity mux4 is
port (
a, b, c, d : in std_logic_vector (7 downto 0);
sel : in std_logic_vector (1 downto 0);
outmux : out std_logic_vector (7 downto 0));
end mux4;
begin
process (a, b, c, d, sel)
begin
case sel is
when "00" => outmux <= a;
when "01" => outmux <= b;
when "10" => outmux <= c;
when others => outmux <= d; -- case statement
-- must be complete
end case;
end process;
end behavior;

VHDL For...Loop Statements

XST supports the for statement for:
• Constant bounds
• Stop test condition using any of the following operators:
– <
– <=
– >
– >=
• Next step computation falling within one of the following specifications:
– var = var + step
– var = var - step
where
♦ var is the loop variable
♦ step is a constant value
• Next and exit statements
VHDL For...Loop Statement Coding Example

library IEEE;
entity countzeros is
port (
a : in std_logic_vector (7 downto 0);
Count : out std_logic_vector (2 downto 0) );
end mux4;

signal Count_Aux: std_logic_vector (2 downto 0);
begin
process (a)
begin
Count_Aux <= "000";
for i in a’range loop
if (a[i] = ’0’) then
Count_Aux <= Count_Aux + 1; -- operator "+" defined
-- in std_logic_unsigned
end if;
end loop;
Count <= Count_Aux;
end process;
end behavior;
VHDL Sequential Circuits

Sequential circuits can be described using sequential processes. XST allows:
• VHDL Sequential Process With a Sensitivity List
• VHDL Sequential Process Without a Sensitivity List

VHDL Sequential Process With a Sensitivity List

A process is sequential when it is not a combinatorial process. In other words, a process
is sequential when some assigned signals are not explicitly assigned in all paths of
the statements. In this case, the hardware generated has an internal state or memory
(flip-flops or latches).
The following coding example provides a template for describing sequential circuits.
This topic describes macro inference (for example, registers and counters).
Coding Example
Declare asynchronous signals in the sensitivity list. Otherwise, XST issues a warning
and adds them to the sensitivity list. In this case, the behavior of the synthesis result
may be different from the initial specification.
process (CLK, RST) ...
begin
if RST = <’0’ | ’1’> then
-- an asynchronous part may appear here
-- optional part
.......
elsif <CLK’EVENT | not CLK’STABLE>
and CLK = <’0’ | ’1’> then
-- synchronous part
-- sequential statements may appear here
end if;
end process;
VHDL Sequential Process Without a Sensitivity List

Sequential processes without a sensitivity list must contain a Wait statement. The Wait
statement must be the first statement of the process. The condition in the Wait statement
must be a condition on the clock signal. Several Wait statements in the same process are
accepted, but a set of specific conditions must be respected.
VHDL Multiple Wait Statements Descriptions
An asynchronous part cannot be specified within processes without a sensitivity list.
VHDL Sequential Process Without a Sensitivity List Coding Example

The following VHDL coding example shows the skeleton of the process described in this
section. The clock condition may be a falling or a rising edge.
process ...
begin
wait until <CLK’EVENT | not CLK’ STABLE> and CLK = <’0’ | ’1’>;
... -- a synchronous part may be specified here.
end process;
XST does not support clock and clock enable descriptions within the same Wait
statement. Instead, code these descriptions as shown in Clock and Clock Enable (Supported)
VHDL Coding Example.
XST does not support Wait statements for latch descriptions.

Clock and Clock Enable (Not Supported) VHDL Coding Example

Caution! This coding style is NOT supported.
wait until CLOCK’event and CLOCK = ’0’ and ENABLE = ’1’ ;
Clock and Clock Enable (Supported) VHDL Coding Example

"8 Bit Counter Description Using a Process with a Sensitivity List" if ENABLE = ’1’ then ...
Register and Counter Descriptions VHDL Coding Examples

8-Bit Register Description Using a Process With a Sensitivity List VHDL

Coding Example
entity EXAMPLE is
port (
DI : in BIT_VECTOR (7 downto 0);
CLK : in BIT;
DO : out BIT_VECTOR (7 downto 0) );
end EXAMPLE;

begin
process (CLK)
begin
if CLK’EVENT and CLK = ’1’ then
DO <= DI ;
end if;
end process;
end ARCHI;
8 Bit Register Description Using a Process Without a Sensitivity List
Containing a Wait Statement VHDL Coding Example
entity EXAMPLE is
port (
CLK : in BIT;
DO : out BIT_VECTOR (7 downto 0) );
end EXAMPLE;

begin
process begin
wait until CLK’EVENT and CLK = ’1’;
DO <= DI;
end process;
end ARCHI;

8-Bit Register With Clock Signal and Asynchronous Reset Signal VHDL
Coding Example
entity EXAMPLE is
port (
CLK : in BIT;
RST : in BIT;
DO : out BIT_VECTOR (7 downto 0));
end EXAMPLE;

begin
process (CLK, RST)
begin
if RST = ’1’ then
DO <= "00000000";
elsif CLK’EVENT and CLK = ’1’ then
DO <= DI ;
end if;
end process;
end ARCHI;
8-Bit Counter Description Using a Process With a Sensitivity List VHDL
Coding Example
library ASYL;
use ASYL.PKG_ARITH.all;
entity EXAMPLE is
port (
CLK : in BIT;
RST : in BIT;
DO : out BIT_VECTOR (7 downto 0));
end EXAMPLE;

begin
process (CLK, RST)
variable COUNT : BIT_VECTOR (7 downto 0);
begin
if RST = ’1’ then
COUNT := "00000000";
elsif CLK’EVENT and CLK = ’1’ then
COUNT := COUNT + "00000001";
end if;
DO <= COUNT;
end process;
end ARCHI;

VHDL Multiple Wait Statements Descriptions

Sequential circuits can be described in VHDL with multiple wait statements in a process.
Follow these rules when using multiple wait statements:
• The process contains only one loop statement.
• The first statement in the loop is a wait statement.
• After each wait statement, a next or exit statement is defined.
• The condition in the wait statements is the same for each wait statement.
• This condition use only one signal — the clock signal.
• This condition has the following form:
"wait [on clock_signal] until [(clock_signal’EVENT | not clock_signal’STABLE) and ]
clock_signal = {’0’ | ’1’};"

Coding Example
The following VHDL coding example uses multiple wait statements. This example
describes a sequential circuit performing four different operations in sequence.
The design cycle is delimited by two successive rising edges of the clock signal. A
synchronous reset is defined providing a way to restart the sequence of operations at
the beginning. The sequence of operations consists of assigning each of the following
four inputs to the output RESULT:
• DATA1
• DATA2
• DATA3
• DATA4
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity EXAMPLE is
port (
DATA1, DATA2, DATA3, DATA4 : in STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (3 downto 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC );
end EXAMPLE;
architecture ARCH of EXAMPLE is

begin
process begin
SEQ_LOOP : loop
exit SEQ_LOOP when RST = ’1’;
RESULT <= DATA1;

RESULT <= DATA2;

RESULT <= DATA3;

RESULT <= DATA4;
end loop;
end process;
end ARCH;

VHDL Functions and Procedures

The declaration of a function or a procedure in VHDL provides a mechanism for
handling blocks used multiple times in a design. Functions and procedures can be
declared in the declarative part of an entity, in an architecture or in packages. The
heading part contains:
• Input parameters for functions and input
• Output and inout parameters for procedures.
These parameters can be unconstrained. They are not constrained to a given bound. The
content is similar to the combinatorial process content.
Resolution functions are not supported except the one defined in the IEEE std_logic_1164
package.
Function Declaration and Function Call VHDL Coding Example

The following VHDL coding example shows a function declared within a package. The
ADD function declared here is a single bit adder. This function is called four times with
the proper parameters in the architecture to create a 4-bit adder. The same example using
a procedure is shown in Procedure Declaration and Procedure Call VHDL Coding Example.
package PKG is
function ADD (A,B, CIN : BIT )
return BIT_VECTOR;
end PKG;
package body PKG is

function ADD (A,B, CIN : BIT )
return BIT_VECTOR is
variable S, COUT : BIT;
variable RESULT : BIT_VECTOR (1 downto 0);
begin
S := A xor B xor CIN;
COUT := (A and B) or (A and CIN) or (B and CIN);
RESULT := COUT & S;
return RESULT;
end ADD;
end PKG;
use work.PKG.all;
entity EXAMPLE is
port (
CIN : in BIT;
S : out BIT_VECTOR (3 downto 0);
COUT : out BIT );
end EXAMPLE;

signal S0, S1, S2, S3 : BIT_VECTOR (1 downto 0);
begin
S0 <= ADD (A(0), B(0), CIN);
S1 <= ADD (A(1), B(1), S0(1));
S2 <= ADD (A(2), B(2), S1(1));
S3 <= ADD (A(3), B(3), S2(1));
S <= S3(0) & S2(0) & S1(0) & S0(0);
COUT <= S3(1);
end ARCHI;

Procedure Declaration and Procedure Call VHDL Coding Example

package PKG is
procedure ADD (
A,B, CIN : in BIT;
C : out BIT_VECTOR (1 downto 0) );
end PKG;
package body PKG is

procedure ADD (
A,B, CIN : in BIT;
C : out BIT_VECTOR (1 downto 0)
) is
variable S, COUT : BIT;
begin
S := A xor B xor CIN;
COUT := (A and B) or (A and CIN) or (B and CIN);
C := COUT & S;
end ADD;
end PKG;
use work.PKG.all;
entity EXAMPLE is
port (
CIN : in BIT;
S : out BIT_VECTOR (3 downto 0);
COUT : out BIT );
end EXAMPLE;

begin
process (A,B,CIN)
variable S0, S1, S2, S3 : BIT_VECTOR (1 downto 0);
begin
ADD (A(0), B(0), CIN, S0);
ADD (A(1), B(1), S0(1), S1);
ADD (A(2), B(2), S1(1), S2);
ADD (A(3), B(3), S2(1), S3);
S <= S3(0) & S2(0) & S1(0) & S0(0);
COUT <= S3(1);
end process;
end ARCHI;
Recursive Function VHDL Coding Example
XST supports recursive functions. The following coding example represents n! function:
function my_func(x : integer) return integer is
begin
if x = 1 then
return x;
else
return (x*my_func(x-1));
end if;
end function my_func;

VHDL Assert Statements

XST supports VHDL Assert statements. Assert statements enable you to detect
undesirable conditions in VHDL designs, such as bad values for:
• conditions:
– generics
– constants
– generate
• parameters in called functions
For any failed condition in an Assert statement, XST (depending on the severity level)
either:
• Issues a warning message, or
• Rejects the design and issues an error message.
XST supports the Assert statement only with static condition.
Coding Example
The following coding example contains a block SINGLE_SRL which describes a shift
register. The size of the shift register depends on the SRL_WIDTH generic value. The
Assert statement ensures that the implementation of a single shift register does not
exceed the size of a single Shift Register LUT (SRL).

Since the size of the SRL is 16 bit, and XST implements the last stage of the shift register
using a flip-flop in a slice, then the maximum size of the shift register cannot exceed 17
bits. The SINGLE_SRL block is instantiated twice in the entity named TOP:
• first with SRL_WIDTH equal to 13
• second with SRL_WIDTH equal to 18
library ieee;
entity SINGLE_SRL is
generic (SRL_WIDTH : integer := 16);
port (
clk : in std_logic;
inp : in std_logic;
outp : out std_logic);
end SINGLE_SRL;
architecture beh of SINGLE_SRL is

signal shift_reg : std_logic_vector (SRL_WIDTH-1 downto 0);
begin
assert SRL_WIDTH <= 17

report "The size of Shift Register exceeds the size of a single SRL"
severity FAILURE;
process (clk)
begin
shift_reg <= shift_reg (SRL_WIDTH-1 downto 1) & inp;
end if;
end process;
outp <= shift_reg(SRL_WIDTH-1);
end beh;
library ieee;
entity TOP is
port (
clk : in std_logic;
inp1, inp2 : in std_logic;
outp1, outp2 : out std_logic);
end TOP;
architecture beh of TOP is

component SINGLE_SRL is
generic (SRL_WIDTH : integer := 16);
port(
clk : in std_logic;
inp : in std_logic;
outp : out std_logic);
end component;
begin
inst1: SINGLE_SRL generic map (SRL_WIDTH => 13)
port map(
clk => clk,
inp => inp1,
outp => outp1 );
inst2: SINGLE_SRL generic map (SRL_WIDTH => 18)
port map(
clk => clk,
inp => inp2,
outp => outp2 );
end beh;

Error Message
If you run the coding example above, XST issues the following error message:
...
================================================================
* HDL Analysis *
================================================================
Analyzing Entity <top> (Architecture <beh>).
Entity <top> analyzed. Unit <top> generated.
Analyzing generic Entity <single_srl> (Architecture <beh>).

SRL_WIDTH = 13
Entity <single_srl> analyzed. Unit <single_srl> generated.
Analyzing generic Entity <single_srl> (Architecture <beh>).

SRL_WIDTH = 18
ERROR:Xst - assert_1.vhd line 15: FAILURE:
The size of Shift Register exceeds the size of a single SRL
...

VHDL Models Defined Using Packages

This section discusses VHDL Models Defined Using Packages, and includes:
• About VHDL Models Defined Using Packages
• Using Standard Packages to Define VHDL Models
• Using IEEE Packages to Define VHDL Models
• Using Synopsys Packages to Define VHDL Models
About VHDL Models Defined Using Packages

VHDL models may be defined using packages. Packages contain:
• Type and subtype declarations
• Constant definitions
• Function and procedure definitions
• Component declarations
Using packages to define VHDL models provides the ability to change parameters and
constants of the design, such as constant values and function definitions.
Packages may contain two declarative parts:
• Body declaration
• Package declaration
The body declaration includes the description of function bodies declared in the package
declaration.
library lib_pack ;
-- lib_pack is the name of the library specified
-- where the package has been compiled (work by default)
use lib_pack .pack_name .all;
-- pack_name is the name of the defined package.
XST also supports predefined packages. These packages are pre-compiled and can be
included in VHDL designs. These packages are intended for use during synthesis, but
may also be used for simulation.
Using Standard Packages to Define VHDL Models

The Standard package:
• Is included by default
• Contains basic types:
– bit
– bit_vector
– integer

VHDL Models Defined Using IEEE Packages

XST supports the following IEEE packages:
• std_logic_1164
Supports the following types:
– std_logic
– std_ulogic
– std_logic_vector
– std_ulogic_vector
XST also supports conversion functions based on these types.
• numeric_bit
Supports the following types based on type bit:
– Unsigned vectors
– Signed vectors
XST also supports:
♦ All overloaded arithmetic operators on these types
♦ Conversion and extended functions for these types
• numeric_std
Supports the following types based on type std_logic:
– Unsigned vectors
– Signed vectors
This package is equivalent to std_logic_arith.
• math_real
Supports the following:
– Real number constants as shown in VHDL Real Number Constants
– Real number functions as shown in VHDL Real Number Constants
– The procedure uniform, which generates successive values between 0.0 and 1.0
VHDL Real Number Constants

Constant Value Constant Value
math_e e math_log_of_2 ln2
math_1_over_e 1/e math_log_of_10 ln10
math_pi math_log2_of_e log2e
math_2_pi math_log10_of_e log10e
math_1_over_pi math_sqrt_2
math_pi_over_2 math_1_oversqrt_2
math_pi_over_3 math_sqrt_pi
math_pi_over_4 math_deg_to_rad
math_3_pi_over_2 math_rad_to_deg

VHDL Real Number Functions

ceil(x) realmax(x,y) exp(x) cos(x) cosh(x)
floor(x) realmin(x,y) log(x) tan(x) tanh(x)
round(x) sqrt(x) log2(x) arcsin(x) arcsinh(x)
trunc(x) cbrt(x) log10(x) arctan(x) arccosh(x)
sign(x) "**"(n,y) log(x,y) arctan(y,x) arctanh(x)
"mod"(x,y) "**"(x,y) sin(x) sinh(x)
Functions and procedures in the math_real packages, as well as the real type, are for
calculations only. They are not supported for synthesis in XST.
Coding Example
library ieee;
use IEEE.std_logic_signed.all;
signal a, b, c : std_logic_vector (5 downto 0);
c <= a + b;
-- this operator "+" is defined in package std_logic_signed.
-- Operands are converted to signed vectors, and function "+"
-- defined in package std_logic_arith is called with signed
-- operands.
Using Synopsys Packages to Define VHDL Models

The following Synopsys packages are supported in the IEEE library:
• std_logic_arith
Supports types unsigned, signed vectors, and all overloaded arithmetic operators on
these types. It also defines conversion and extended functions for these types.
• std_logic_unsigned
Defines arithmetic operators on std_ulogic_vector and considers them as unsigned
operators.
• std_logic_signed
Defines arithmetic operators on std_logic_vector and considers them as signed
operators.
• std_logic_misc
Defines supplemental types, subtypes, constants, and functions for the
std_logic_1164 package, such as:
– and_reduce
– or_reduce

VHDL Constructs Supported in XST

XST supports the following VHDL Constructs:
• Design Entities and Configurations
• Expressions
• Statements
VHDL Design Entities and Configurations

Note XST does not allow underscores as the first character of signal names (for
example, _DATA_1).
XST supports VHDL design entities and configurations except as shown in the following
sections:
• VHDL Entity Headers
• VHDL Packages
• VHDL Physical Types
• VHDL Modes
• VHDL Declarations
• VHDL Objects
• VHDL Specifications
VHDL Entity Headers

• Generics
Supported
• Ports
Supported
• Entity Statement Part
Partial support. Allowed statements include:
– Attribute declarations
– Attribute specifications
– Constant declarations
VHDL Packages
STANDARD
Type TIME is not supported
VHDL Physical Types

• TIME
Ignored
• REAL
Supported, but only in functions for constant calculations
VHDL Modes
Linkage
Unsupported

VHDL Declarations
Type
Supported for:
– enumerated types
– types with positive range having constant bounds
– bit vector types
– multi-dimensional arrays
VHDL Objects
• Constant Declaration
Supported except for deferred constant
• Signal Declaration
Supported except for register and bus type signals
• Attribute Declaration
Supported for some attributes, otherwise skipped
VHDL Specifications
• Attribute
Supported for some predefined attributes only:
– HIGH
– LOW
– LEFT
– RIGHT
– RANGE
– REVERSE_RANGE
– LENGTH
– POS
– ASCENDING
– EVENT
– LAST_VALUE
• Configuration
Supported only with the all clause for instances list. If no clause is added, XST looks
for the entity or architecture compiled in the default library
• Disconnection
Unsupported
VHDL Expressions
XST supports the following expressions:
• VHDL Operators
• VHDL Operands

VHDL Operators
Operator Supported/Unsupported
Logical Operators: Supported
and, or, nand, nor, xor, xnor, not
Relational Operators: Supported
=, /=, <, <=, >, >=
& (concatenation) Supported
Adding Operators: +, - Supported
* Supported
/,rem Supported if the right operand is a constant power of 2
mod Supported if the right operand is a constant power of 2
Shift Operators: Supported
sll, srl, sla, sra, rol, ror
abs Supported
** Only supported if the left operand is 2
Sign: +, - Supported
VHDL Operands
Operand Supported/Unsupported
Abstract Literals Only integer literals are supported
Physical Literals Ignored
Enumeration Literals Supported
String Literals Supported
Bit String Literals Supported
Record Aggregates Supported
Array Aggregates Supported
Function Call Supported
Qualified Expressions Supported for accepted predefined attributes
Types Conversions Supported
Allocators Unsupported
Static Expressions Supported
VHDL Statements
XST supports all VHDL statements except as shown in the following sections:
• VHDL Wait Statements
• VHDL Loop Statements
• VHDL Concurrent Statements

VHDL Wait Statements

Wait Statement Supported/Unsupported
Wait on sensitivity_list until Boolean_expression. Supported with one signal in the sensitivity list and in the
Boolean expression. In case of multiple Wait statements,
For more information, see: the sensitivity list and the Boolean expression must be the
VHDL Sequential Circuits same for each Wait statement.
Note XST does not support Wait statements for latch
descriptions.
Wait for time_expression ... Unsupported
VHDL Sequential Circuits
Assertion Statement Supported (only for static conditions)
Signal Assignment Supported (delay is ignored)
Statement
VHDL Loop Statements

Loop Statement Supported/Unsupported
for... loop... end loop Supported for constant bounds only. Disable statements
are not supported.
loop ... end loop Only supported in the particular case of multiple Wait
statements
VHDL Concurrent Statements

Concurrent Statement Supported/Unsupported
Concurrent Signal Supported (no after clause, no transport or guarded options,
no waveforms) UNAFFECTED is supported.
Assignment Statement
For ... Generate Statement supported for constant bounds only
If ... Generate Statement supported for static condition only

VHDL Reserved Words

abs access after alias
all and architecture array
assert attribute begin block
body buffer bus case
component configuration constant disconnect
downto else elsif end
entity exit file for
function generate generic group
guarded if impure in
inertial inout is label
library linkage literal loop
map mod nand new
next nor not null
of on open or
others out package port

postponed procedure process pure
range record register reject
rem report return rol
ror select severity signal
shared sla sll sra
srl subtype then to

transport type unaffected units
until use variable wait
when while with xnor
xor

Chapter 15
XST Verilog Language Support

This chapter discusses XST Verilog Language Support, and includes:
• About XST Verilog Language Support
• Behavioral Verilog
• Variable Part Selects
• Structural Verilog Features
• Verilog Parameters
• Verilog Parameter and Attribute Conflicts
• Verilog Limitations in XST
• Verilog Attributes and Meta Comments
• Verilog Constructs Supported in XST
• Verilog System Tasks and Functions Supported in XST
• Verilog Primitives
• Verilog Reserved Keywords
• Verilog-2001 Support in XST
About XST Verilog Language Support

Complex circuits are commonly designed using a top down methodology. Various
specification levels are required at each stage of the design process. For example, at the
architectural level, a specification may correspond to a block diagram or an Algorithmic
State Machine (ASM) chart. A block or ASM stage corresponds to a register transfer
block where the connections are N-bit wires, such as:
• Register
• Adder
• Counter
• Multiplexer
• Glue logic
• Finite State Machine (FSM)
A Hardware Description Language (HDL) such as Verilog allows the expression of
notations such as ASM charts and circuit diagrams in a computer language.
Verilog provides both behavioral and structural language structures. These structures
allow expressing design objects at high and low levels of abstraction. Designing
hardware with a language such as Verilog allows using software concepts such as
parallel processing and object-oriented programming. Verilog has a syntax similar to C
and Pascal. XST supports it as IEEE 1364.

Chapter 15: XST Verilog Language Support
The Verilog support in XST provides an efficient way to describe both the global circuit
and each block according to the most efficient style. Synthesis is then performed with
the best synthesis flow for each block. Synthesis in this context is the compilation of
high-level behavioral and structural Verilog Hardware Description Language (HDL)
statements into a flattened gate-level netlist, which can then be used to custom program
a programmable logic device such as a Virtex® device. Different synthesis methods are
used for arithmetic blocks, glue logic, and Finite State Machine (FSM) components.
The XST User Guide for Virtex-4, Virtex-5, Spartan-3, and Newer CPLD Devices assumes that
you are familiar with basic Verilog concepts.
• Verilog design constraints and options
• Verilog attribute syntax
• Setting Verilog options in the Process window of ISE® Design Suite
XST General Constraints
• General Verilog information
IEEE Verilog HDL Reference Manual
Behavioral Verilog
For information about Behavioral Verilog, see:
Variable Part Selects

Verilog 2001 adds the capability of using variables to select a group of bits from a vector.
A variable part select is defined by the starting point of its range and the width of the
vector, instead of being bounded by two explicit values. The starting point of the part
select can vary, but the width of the part select remains constant.
Variable Part Select Symbols

Symbol Meaning
+ (plus) The part select increases from the starting point
- (minus) The part select decreases from the starting point
Coding Example
reg [3:0] data;
reg [3:0] select; // a value from 0 to 7
wire [7:0] byte = data[select +: 8];
Structural Verilog Features

This section discusses Structural Verilog Features, and includes:
• About Structural Verilog Features
• Instantiating Pre-Defined Primitives

About Structural Verilog Features

Structural Verilog descriptions assemble several blocks of code and allow the
introduction of hierarchy in a design. The basic concepts of hardware structure are:
• Component
The building or basic block
• Port
A component I/O connector
• Signal
Corresponds to a wire between components
In Verilog, a component is represented by a design module. The module declaration
provides the external view of the component. It describes what can be seen from the
outside, including the component ports. The module body provides an internal view. It
describes the behavior or the structure of the component.
The connections between components are specified within component instantiation
statements. These statements specify an instance of a component occurring within
another component or the circuit. Each component instantiation statement is labeled
with an identifier.
Besides naming a component declared in a local component declaration, a component
instantiation statement contains an association list (the parenthesized list) that specifies
which actual signals or ports are associated with which local ports of the component
declaration.
Verilog provides a large set of built-in logic gates which can be instantiated to build
larger logic circuits. The set of logical functions described by the built-in gates includes:
• AND
• OR
• XOR
• NAND
• NOR
• NOT
Building a Basic XOR Function Structural Verilog Coding Example

Following is an example of building a basic XOR function of two single bit inputs
a and b:
module build_xor (a, b, c);
input a, b;
output c;
wire c, a_not, b_not;
not a_inv (a_not, a);
not b_inv (b_not, b);
and a1 (x, a_not, b);
and a2 (y, b_not, a);
or out (c, x, y);
endmodule
Each instance of the built-in modules has a unique instantiation name such as:
• a_inv
• b_inv
• out

Structural Description of a Half Adder Structural Verilog Coding Example

The following coding example shows the structural description of a half adder
composed of four, 2 input nand modules:
module halfadd (X, Y, C, S);
input X, Y;
output C, S;
wire S1, S2, S3;
nand NANDA (S3, X, Y);
nand NANDB (S1, X, S3);
nand NANDC (S2, S3, Y);
nand NANDD (S, S1, S2);
assign C = S3;
endmodule
Synthesized Top Level Netlist Diagram
Instantiating Pre-Defined Primitives

The structural features of Verilog also allow you to design circuits by instantiating
pre-defined primitives such as:
• gates
• registers
• Xilinx® specific primitives such as:
– CLKDLL
– BUFG
These primitives are other than those included in Verilog. These pre-defined primitives
are supplied with the XST Verilog libraries (unisim_comp.v).

Structural Instantiation of REGISTER and BUFG Structural Verilog Coding

Example
module foo (sysclk, in, reset, out);
input sysclk, in, reset;
output out;
reg out;
wire sysclk_out;
FDC register (out, sysclk_out, reset, in);
//position based referencing
BUFG clk (.O(sysclk_out),.I(sysclk));
//name based referencing
...
endmodule
The unisim_comp.v library file supplied with XST, includes the definitions for:
• FDC
• BUFG
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDC (Q, C, CLR, D);
parameter INIT = 1’b0;
output Q;
input C;
input CLR;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFG ( O, I);
output O;
input I;
endmodule

Verilog Parameters
Verilog modules allow you to define constants known as parameters. Parameters can be
passed to module instances to define circuits of arbitrary widths. Parameters form the
basis of creating and using parameterized blocks in a design to achieve hierarchy.
Coding Example
The following Verilog coding example shows the use of parameters. Null string
parameters are not supported.
module lpm_reg (out, in, en, reset, clk);
parameter SIZE = 1;
input in, en, reset, clk;
output out;
wire [SIZE-1 : 0] in;
reg [SIZE-1 : 0] out;
always @(posedge clk or negedge reset)
begin
if (!reset)
out <= 1’b0;
else
if (en)
out <= in;
else
out <= out; //redundant assignment
end
endmodule
module top (); //portlist left blank intentionally
...
wire [7:0] sys_in, sys_out;
wire sys_en, sys_reset, sysclk;
lpm_reg #8 buf_373 (sys_out, sys_in, sys_en, sys_reset, sysclk);
...
endmodule
Instantiation of the module lpm_reg with a instantiation width of 8 causes the instance
buf_373 to be 8 bits wide.
The Generics (-generics) command line option allows you to redefine parameters
(Verilog) values defined in the top-level design block. This allows you to easily modify
the design configuration without any Hardware Description Language (HDL) source
modifications, such as for IP core generation and testing flows.

Verilog Parameter and Attribute Conflicts

This section discusses Verilog Parameter and Attribute Conflicts, and includes:
• Resolving Verilog Parameter and Attribute Conflicts
• Verilog Parameter and Attribute Conflicts Precedence
Resolving Verilog Parameter and Attribute Conflicts

Since parameters and attributes can be applied to both instances and modules in Verilog
code, and attributes can also be specified in a constraints file, conflicts will occasionally
arise.
XST uses the following rules of precedence to resolve these conflicts:
1. Specifications on an instance (lower level) takes precedence over specifications on a
module (higher level).
2. If a parameter and an attribute are specified on either the same instance or the same
module, the parameter takes precedence. XST issues a warning message.
3. An attribute specified in the XST Constraint File (XCF) takes precedence over
attributes or parameters specified in the Verilog code.
When an attribute specified on an instance overrides a parameter specified on a module
in XST, the simulation tool may use the parameter anyway. If that happens, the
simulation results may not match the synthesis results.
Verilog Parameter and Attribute Conflicts Precedence

Parameter on an Instance Parameter on a Module
Attribute on an Instance Apply Parameter (XST issues Apply Attribute (possible
warning) simulation mismatch)
Attribute on a Module Apply Parameter Apply Parameter (XST issues
warning)
Attribute in XCF Apply Attribute (XST issues Apply Attribute
warning)
Security attributes on the module definition always have higher precedence than any
other attribute or parameter.

Verilog Limitations in XST

This section describes Verilog Limitations in XST, and includes:
• Verilog Case Sensitivity
• Verilog Blocking and Nonblocking Assignments
• Verilog Integer Handling
Verilog Case Sensitivity

Since Verilog is case sensitive, module and instance names can be made unique by
changing capitalization. However, for compatibility with file names, mixed language
support, and other tools, Xilinx® recommends that you do not rely on capitalization
only to make instance names unique.
XST does not allow module names to differ by capitalization only. It renames instances
and signal names to ensure that lack of case sensitivity support in other tools in your
flow does not adversely impact your design.
XST Support for Verilog Case Sensitivity

XST supports Verilog case sensitivity as follows:
• Designs can use case equivalent names for I/O ports, nets, regs and memories.
• Equivalent names are renamed using a postfix (rnm<Index>).
• A rename construct is generated in the NGC file.
• Designs can use Verilog identifiers that differ in case only. XST renames them using
a postfix as with equivalent names.
For instance:
module upperlower4 (input1, INPUT1, output1, output2);
input input1;
input INPUT1;
For this example, INPUT1 is renamed to INPUT1_rnm0.
Verilog Restrictions Within XST

XST rejects code using equivalent names (named blocks, tasks, and functions) such as
the following:
...
always @(clk)
begin: fir_main5
reg [4:0] fir_main5_w1;
reg [4:0] fir_main5_W1;
ERROR:Xst:863 - "design.v", line 6: Name conflict
(<fir_main5/fir_main5_w1> and <fir_main5/fir_main5_W1>)
Code using case equivalent module names such as the following is rejected:
module UPPERLOWER10 (...);
...
module upperlower10 (...);
...

ERROR:Xst:909 - Module name conflict (UPPERLOWER10 and

upperlower10)
Verilog Blocking and Nonblocking Assignments

This section gives two rejected coding examples for blocking and nonblocking
assignments.
Rejected Coding Example One

XST rejects Verilog designs if a given signal is assigned through both blocking and
nonblocking assignments as shown in the following coding example.
always @(in1)
begin
if (in2)
out1 = in1;
else
out1 <= in2;
end
Rejected Coding Example Two
The following coding example is rejected even if there is no real mixing of blocking
and nonblocking assignments.
if (in2)
begin
out1[0] = 1’b0;
out1[1] <= in1;
end
else
begin
out1[0] = in2;
out1[1] <= 1’b1;
end
If a variable is assigned in both a blocking and nonblocking assignment, XST issues the
following error message:
ERROR:Xst:880 - "design.v", line n:
Cannot mix blocking and non-blocking assignments on signal <out1>.
There are also restrictions when mixing blocking and nonblocking assignments on
bits and slices.
Errors are checked at the signal level, not at the bit level.
If there is more than one blocking or nonblocking error, only the first is reported.
In some cases, the line number for the error might be incorrect (as there might be
multiple lines where the signal has been assigned).
Verilog Integer Handling

XST handles Verilog integers differently from other synthesis tools in several instances.
They must be coded in a particular way. Unsized integers in Verilog case item
expressions and concatenations may cause unpredictable results
Unsized Integers in Verilog Case Item Expressions

Unsized integers in Verilog case item expressions may cause unpredictable results.

In the following coding example, the case item expression 4 is an unsized integer that
causes unpredictable results. To avoid problems, size the 4 to 3 bits as follows:
reg [2:0] condition1;
always @(condition1)
begin
case(condition1)
4 : data_out = 2; // < will generate bad logic
3’d4 : data_out = 2; // < will work
endcase
end
Unsized Integers in Verilog Concatenations

Unsized integers in Verilog concatenations may cause unpredictable results.
If you use an expression that results in an unsized integer:
1. Assign the expression to a temporary signal.
2. Use the temporary signal in the concatenation as follows:
reg [31:0] temp;
assign temp = 4’b1111 % 2;
assign dout = {12/3,temp,din};

Verilog Attributes and Meta Comments

XST supports both of the following in Verilog:
• Verilog-2001 style attributes
Xilinx® recommends Verilog-2001 attributes since they are more generally accepted.
• Verilog meta comments
Meta comments are comments that are understood by the Verilog parser.
XST supports Verilog-2001 attribute statements. Attributes are comments that pass
specific information to software tools such as synthesis tools. Verilog-2001 attributes
can be specified anywhere for operators or signals within module declarations and
instantiations. Other attribute declarations may be supported by the compiler, but
are ignored by XST.
Verilog Meta Comments

Use Verilog meta comments to:
• Set constraints on individual objects such as:
– module
– instance
– net
• Set directives on synthesis:
– parallel_case and full_case directives
– translate_on and translate_off directives
– all tool specific directives
Example:
syn_sharing
XST supports both C-style and Verilog style meta comments.
Writing Verilog Meta Comments

Style Syntax Line Rules
C-style /* ... */ Comments can be multiple
line
Verilog style // ... Comments end at the end of
the line

Supported Constraints
XST supports the following constraints:
// synthesis translate_on
// synthesis translate_off
// synthesis parallel_case full_case
// synthesis parallel_case
// synthesis full_case
• Constraints on individual objects
Syntax
// synthesis attribute [of] ObjectName [is] AttributeValue
Coding Example
// synthesis attribute RLOC of u123 is R11C1.S0
// synthesis attribute HUSET u1 MY_SET
// synthesis attribute fsm_extract of State2 is "yes"
// synthesis attribute fsm_encoding of State2 is "gray"

Verilog Constructs Supported in XST

This section discusses Verilog Constructs Supported in XST, including:
• Constants
• Data Types
• Continuous Assignments
• Procedural Assignments
• Design Hierarchies
• Compiler Directives
Note XST does not allow underscores as the first character of signal names (for
example, _DATA_1)
Verilog Constants Supported in XST

Constant Supported/Unsupported
Integer Constants Supported
Real Constants Supported
Strings Constants Unsupported
Verilog Data Types Supported in XST

XST supports all Verilog data types except as shown in the following table.
Net Types Drive Strengths Registers Named Events
tri0, tri1, and trireg All drive strengths Real and realtime All named events are
are unsupported. are ignored. registers are unsupported.
unsupported.
Verilog Continuous Assignments Supported in XST

Continuous Assignment Supported/Unsupported
Drive Strength Ignored
Delay Ignored
Verilog Procedural Assignments Supported in XST

XST supports Verilog Procedural Assignments except as noted below:
• assign
Supported with limitations
Behavioral Verilog Assign and Deassign Statements
• deassign
Supported with limitations.
• force
Unsupported

• release
Unsupported
• forever statements
Unsupported
• repeat statements
Supported, but repeat value must be constant
• for statements
Supported, but bounds must be static
• delay (#)
Ignored
• event (@)
Unsupported
• wait
Unsupported
• Named Events
Unsupported
• Parallel Blocks
Unsupported
• Specify Blocks
Ignored
• Disable
Supported except in For and Repeat Loop statements.
Verilog Design Hierarchies Supported in XST

Design Hierarchy Supported/Unsupported
module definition Supported
macromodule definition Unsupported
hierarchical names Unsupported
defparam Supported
array of instances Supported

Verilog Compiler Directives Support in XST

Compiler Directive Supported/Unsupported
‘celldefine ‘endcelldefine Ignored
‘default_nettype Supported
‘define Supported
‘ifdef ‘else ‘endif Supported
‘undef, ‘ifndef, ‘elsif, Supported
‘include Supported
‘resetall Ignored
‘timescale Ignored
‘unconnected_drive Ignored
‘nounconnected_drive
‘uselib Unsupported
‘file, ‘line Supported

Verilog System Tasks and Functions Supported in XST

This section discusses Verilog System Tasks and Functions Supported in XST, and
includes:
• Supported System Tasks and Functions
• Unsupported System Tasks
• Signed and Unsigned System Tasks
• Readmemb and Readmemh System Tasks
• Other System Tasks
• Verilog Display Syntax Example
Supported System Tasks and Functions

System Task or Function Supported/Unsupported Comment
$display Supported Escape sequences are limited to %d,
%b, %h, %o, %c and %s
$fclose Supported
$fdisplay Supported
$fgets Supported
$finish Supported $finish is supported for statically never
active conditional branches only
$fopen Supported
$fscanf Supported Escape sequences are limited to %b and
%d
$fwrite Supported
$monitor Ignored
$random Ignored
$readmemb Supported
$readmemh Supported
$signed Supported
$stop Ignored
$strobe Ignored
$time Ignored
$unsigned Supported
$write Supported Escape sequences are limited to %d,
%b, %h, %o, %c and %s
all others Ignored
Unsupported System Tasks

The XST Verilog compiler ignores unsupported system tasks.

Signed and Unsigned System Tasks

The $signed and $unsigned system tasks can be called on any expression using the
following syntax:
• $signed(expr) or
• $unsigned(expr)
The return value from these calls is the same size as the input value. Its sign is forced
regardless of any previous sign.
Readmemb and Readmemh System Tasks

The $readmemb and $readmemh system tasks can be used to initialize block memories.
Use $readmemb for binary and $readmemh for hexadecimal representation. To avoid
the possible difference between XST and simulator behavior, Xilinx® recommends that
you use index parameters in these system tasks. See the following coding example.
Other System Tasks

The remainder of the system tasks can be used to display information to your computer
screen and log file during processing, or to open and use a file during synthesis.
You must call these tasks from within initial blocks. XST supports a subset of escape
sequences, specifically:
• %h
• %d
• %o
• %b
• %c
• %s
Verilog Display Syntax Example

The following example shows the syntax for $display that reports the value of a binary
constant in decimal format:
parameter c = 8’b00101010;
initial
begin
$display ("The value of c is %d", c);
end
The following information is written to the log file during the HDL Analysis phase:
Analyzing top module <example>.
c = 8’b00101010
"foo.v" line 9: $display : The value of c is 42

Verilog Primitives
This section discusses Verilog Primitives, and includes:
• Supported Primitives
• Unsupported Primitives
• Syntax
Supported Primitives
XST supports the following Verilog gate-level primitives except as indicated:
• Pulldown and Pullup
Unsupported
• Drive strength and delay
Ignored
• Arrays of primitives
Unsupported
Unsupported Primitives
XST does not support:
• Verilog switch-level primitives, such as:
– cmos, nmos, pmos, rcmos, rnmos, rpmos
– rtran, rtranif0, rtranif1, tran, tranif0, tranif1
• Verilog user-defined primitives
Syntax
gate_type instance_name (output, inputs,...);
Coding Example
and U1 (out, in1, in2); bufif1 U2 (triout, data, trienable);

Verilog Reserved Keywords

Keywords marked with an asterisk (*) are reserved by Verilog, but are not supported by
XST.
always and assign automatic
begin buf bufif0 bufif1
case casex casez cell*
cmos config* deassign default
defparam design* disable edge
else end endcase endconfig*
endfunction endgenerate endmodule endprimitive
endspecify endtable endtask event
for force forever fork
function generate genvar highz0
highz1 if ifnone incdir*
include* initial inout input
instance* integer join large
liblist* library* localparam* macromodule
medium module nand negedge
nmos nor noshow-cancelled* not
notif0 notif1 or output
parameter pmos posedge primitive
pull0 pull1 pullup pulldown
pulsestyle- _ondetect* pulsestyle- _onevent* rcmos real
realtime reg release repeat
rnmos rpmos rtran rtranif0
rtranif1 scalared show-cancelled* signed
small specify specparam strong0
strong1 supply0 supply1 table
task time tran tranif0
tranif1 tri tri0 tri1
triand trior trireg use*
vectored wait wand weak0
weak1 while wire wor
xnor xor

Verilog-2001 Support in XST

XST supports the following Verilog-2001 features:
• Generate statements
• Combined port/data type declarations
• ANSI-style port lists
• Module parameter port lists
• ANSI C style task/function declarations
• Comma separated sensitivity list
• Combinatorial logic sensitivity
• Default nets with continuous assigns
• Disable default net declarations
• Indexed vector part selects
• Multi-dimensional arrays
• Arrays of net and real data types
• Array bit and part selects
• Signed reg, net, and port declarations
• Signed based integer numbers
• Signed arithmetic expressions
• Arithmetic shift operators
• Automatic width extension past 32 bits
• Power operator
• N sized parameters
• Explicit in-line parameter passing
• Fixed local parameters
• Enhanced conditional compilation
• File and line compiler directives
• Variable part selects
• Recursive Tasks and Functions
• Constant Functions
• Sutherland, Stuart. Verilog 2001: A Guide to the New Features of the VERILOG Hardware
Description Language (2002)
• IEEE Standards Association. 1364-2001: IEEE Standard Verilog Hardware Description
Language (2001)

Chapter 16
XST Behavioral Verilog Language

Support
This chapter discusses XST Behavioral Verilog Language Support, and includes:
• Behavioral Verilog Variable Declarations
• Behavioral Verilog Initial Values
• Behavioral Verilog Local Reset
• Behavioral Verilog Arrays
• Behavioral Verilog Multi-Dimensional Arrays
• Behavioral Verilog Data Types
• Behavioral Verilog Legal Statements
• Behavioral Verilog Expressions
• Behavioral Verilog Blocks
• Behavioral Verilog Modules
• Behavioral Verilog Module Declarations
• Behavioral Verilog Continuous Assignments
• Behavioral Verilog Procedural Assignments
• Behavioral Verilog Constants
• Behavioral Verilog Macros
• Behavioral Verilog Include Files
• Behavioral Verilog Comments
• Behavioral Verilog Generate Statements

Chapter 16: XST Behavioral Verilog Language Support
Behavioral Verilog Variable Declarations

Variables in Verilog may be declared as integers or real. These declarations are intended
for use in test code only. Verilog provides data types such as reg and wire for actual
hardware description.
Variables in Verilog
Data Type Variable Given Default Width Verilog-2001
Value In
reg procedural block one bit (scalar) signed or unsigned
wire continuous one bit (scalar) signed or unsigned
assignment
Coding Example
To specify an N-bit width (vectors) for a declared reg or wire, the left and right bit
positions are defined in square brackets separated by a colon.
reg [3:0] arb_priority;
wire [31:0] arb_request;
wire signed [8:0] arb_signed;
where
• arb_request[31] is the MSB
• arb_request[0] is the LSB

Behavioral Verilog Initial Values

In Verilog-2001, you can initialize registers when you declare them.
The value:
• Is a constant
• Cannot depend on earlier initial values
• Cannot be a function or task call
• Can be a parameter value propagated to the register
• Specifies all bits of a vector
When you assign a register an initial value in a declaration, XST sets this initial value on
the output of the register:
• At global reset, or
• At power up
An initial value assigned in this manner:
• Is carried in the NGC file as an INIT attribute on the register
• Is independent of any local reset
reg arb_onebit = 1’b0;
reg [3:0] arb_priority = 4’b1011;
You can also assign a set/reset (initial) value to a register in the behavioral Verilog code.
Assign a value to a register when the register reset line goes to the appropriate value as
shown in the following coding example.
begin
if (rst)
arb_onebit <= 1’b0;
end
end
When you set the initial value of a variable in the behavioral code, it is implemented in
the design as a flip-flop whose output can be controlled by a local reset. As such, it is
carried in the NGC file as an FDP or FDC flip-flop.

Behavioral Verilog Local Reset

Local reset is independent of global reset. Registers controlled by a local reset may be set
to a different value than ones whose value is only reset at global reset (power up). In
the following coding example, the register, arb_onebit, is set to 0 at global reset, but
a pulse on the local reset (rst) can change its value to 1.
Coding Example
module mult(clk, rst, A_IN, B_OUT);
input clk,rst,A_IN;
output B_OUT;
reg arb_onebit = 1’b0;
always @(posedge clk or posedge rst)

begin
if (rst)
arb_onebit <= 1’b1;
else
arb_onebit <= A_IN;
end
end
B_OUT <= arb_onebit;
endmodule
This sets the set/reset value on the register output at initial power up, but since this is
dependent upon a local reset, the value changes whenever the local set/reset is activated.

Behavioral Verilog Arrays

Verilog allows arrays of reg and wires to be defined as shown in the following coding
examples.
Behavioral Verilog Arrays Coding Example

The following coding example describes an array of 32 elements each, 4 bits wide which
can be assigned in behavioral Verilog code:
reg [3:0] mem_array [31:0];
Structural Verilog Arrays Coding Example
The following coding example describes an array of 64 elements each 8 bits wide which
can be assigned only in structural Verilog code:
wire [7:0] mem_array [63:0];
Behavioral Verilog Multi-Dimensional Arrays

XST supports multi-dimensional array types of up to two dimensions. Multi-dimensional
arrays can be any net or any variable data type. You can code assignments and
arithmetic operations with arrays, but you cannot select more than one element of
an array at one time. You cannot pass multi-dimensional arrays to system tasks or
functions, or to regular tasks or functions.
Coding Example One

The following Verilog coding example describes an array of 256 x 16 wire elements each
8 bits wide, which can be assigned only in structural Verilog code:
wire [7:0] array2 [0:255][0:15];
Coding Example Two
The following Verilog coding example describes an array of 256 x 8 register elements,
each 64 bits wide, which can be assigned in behavioral Verilog code:
reg [63:0] regarray2 [255:0][7:0];

Behavioral Verilog Data Types

This section discusses Behavioral Verilog Data Types, and includes:
• Bit Data Type Values
• Supported Verilog Data Types
• Nets and Registers
Bit Data Type Values

The Verilog representation of the bit data type contains the following values:
• 0
logic zero
• 1
logic one
• x
unknown logic value
• z
high impedance
Supported Verilog Data Types

XST supports the following Verilog data types:
• Net
– wire
– tri
– triand/wand
– trior/wor
• Registers
– reg
– integer
• Supply nets
– supply0
– supply1
• Constants
parameter
• Multi-Dimensional Arrays (Memories)
Nets and Registers

Nets and registers can be either:
• Single bit (scalar)
• Multiple bit (vectors)

Coding Example
The following Behavioral Verilog coding example shows sample Verilog data types
found in the declaration section of a Verilog module.
wire net1; // single bit net
reg r1; // single bit register
tri [7:0] bus1; // 8 bit tristate bus
reg [15:0] bus1; // 15 bit register
reg [7:0] mem[0:127]; // 8x128 memory register
parameter state1 = 3’b001; // 3 bit constant
parameter component = "TMS380C16"; // string

Behavioral Verilog Legal Statements

The following statements are legal in Behavioral Verilog.
• Variable and signal assignments
– Variable = expression
– if (condition) statement
– else statement
– case (expression)
expression: statement
...
default: statement
endcase
– for (variable = expression; condition; variable = variable + expression) statement
– while (condition) statement
– forever statement
– functions and tasks
• All variables are declared as integer or reg.
Note A variable cannot be declared as a wire.

Behavioral Verilog Expressions

An expression involves constants and variables with arithmetic, logical, relational, and
conditional operators as shown in Operators Supported in Behavioral Verilog.
The logical operators are further divided as bit-wise versus logical, depending on
whether it is applied to an expression involving several bits or a single bit.
Operators Supported in Behavioral Verilog

Arithmetic Logical Relational Conditional
+ & < ?
- && ==
* | ===
** || <=
/ ^ >=
% ~ >=
~^ !=
^~ !==
<< >
>>
<<<
>>>
Expressions Supported in Behavioral Verilog

Expression Symbol Supported/Unsupported
Concatenation {} Supported
Replication {{}} Supported
+, -, *,** Supported
Arithmetic
/ Supported only if second operand is a
power of 2
Modulus % Supported only if second operand is a
power of 2
Addition + Supported
Subtraction - Supported
Multiplication * Supported

Expression Symbol Supported/Unsupported

Power ** Supported
• Both operands are constants,
with the second operand being
non-negative.
• If the first operand is a 2, then the
second operand may be a variable.
• XST does not support the real
data type. Any combination of
operands that results in a real type
causes an error.
• The values X (unknown) and Z
(high impedance) are not allowed.
Division / Supported
XST generates incorrect logic for the
division operator between signed
and unsigned constants. Example:
-1235/3’b111
Relational >, <, >=, <= Supported
Logical Negation ! Supported
Logical AND && Supported
Logical OR || Supported
Logical Equality == Supported
Logical Inequality != Supported
Case Equality === Supported
Case Inequality !== Supported
Bitwise Negation ~ Supported
Bitwise AND & Supported
Bitwise Inclusive OR | Supported
Bitwise Exclusive OR ^ Supported
Bitwise Equivalence ~^, ^~ Supported
Reduction AND & Supported
Reduction NAND ~& Supported
Reduction OR | Supported
Reduction NOR ~| Supported
Reduction XOR ^ Supported
Reduction XNOR ~^, ^~ Supported
Left Shift << Supported
Right Shift Signed >>> Supported
Left Shift Signed <<< Supported
Right Shift >> Supported
Conditional ?: Supported
Event OR or, ’,’ Supported

Results of Evaluating Expressions in Behavioral Verilog

The following table lists the results of evaluating expressions using the more frequently
used operators supported by XST.
The (===) and (!==) operators are special comparison operators useful in simulations to
check if a variable is assigned a value of (x) or (z). They are treated as (==) or (!=) in
synthesis.
ab a==b a===b a!=b a!==b a&b a&&b a|b a||b a^b
00 1 1 0 0 0 0 0 0 0
01 0 0 1 1 0 0 1 1 1
0x x 0 x 1 0 0 x x x
0z x 0 x 1 0 0 x x x
10 0 0 1 1 0 0 1 1 1
11 1 1 0 0 1 1 1 1 0
1x x 0 x 1 x x 1 1 x
1z x 0 x 1 x x 1 1 x
x0 x 0 x 1 0 0 x x x
x1 x 0 x 1 x x 1 1 x
xx x 1 x 0 x x x x x
xz x 0 x 1 x x x x x
z0 x 0 x 1 0 0 x x x
z1 x 0 x 1 x x 1 1 x
zx x 0 x 1 x x x x x
zz x 1 x 0 x x x x x

Behavioral Verilog Blocks

Block statements are used to group statements together.
XST supports sequential blocks only. Within these blocks, the statements are executed
in the order listed.
Block statements are designated by begin and end keywords.
XST does not support parallel blocks.
Behavioral Verilog Modules

In Verilog a design component is represented by a module. The connections between
components are specified within module instantiation statements. Such a statement
specifies an instance of a module. Each module instantiation statement has a name
(instance name). In addition to the name, a module instantiation statement contains an
association list that specifies which actual nets or ports are associated with which local
ports (formals) of the module declaration.
All procedural statements occur in blocks that are defined inside modules. The two
kinds of procedural blocks are:
• initial block
• always block
Within each block, Verilog uses a begin and end to enclose the statements. Since initial
blocks are ignored during synthesis, only always blocks are discussed. The always
blocks usually take the following format:
always
begin
statement
....
end
Each statement is a procedural assignment line terminated by a semicolon.

Behavioral Verilog Module Declarations

The I/O ports of the circuit are declared in the module declaration. Each port has:
• A name
• A mode
– in
– out
– inout
The input and output ports defined in the module declaration called EXAMPLE in the
following coding example are the basic input and output I/O signals for the design. The
in-out port in Verilog is analogous to a bi-directional I/O pin on the device with the data
flow for output versus input being controlled by the enable signal to the tristate buffer.
The following coding example describes E as a tristate buffer with a high-true output
enable signal.
• If oe = 1, the value of signal A is output on the pin represented by E.
• If oe = 0, the buffer is in high impedance (Z), and any input value driven on the
pin E (from the external logic) is brought into the device and fed to the signal
represented by D.
Coding Example
module EXAMPLE (A, B, C, D, E);
input A, B, C;
output D;
inout E;
wire D, E;
...
assign E = oe ? A : 1’bz;
assign D = B & E;
...
endmodule

Behavioral Verilog Continuous Assignments

Continuous assignments model combinatorial logic in a concise way.
XST supports both explicit and implicit continuous assignments.
• Explicit continuous assignments are introduced by the assign keyword after the net
has been separately declared.
• Implicit continuous assignments combine declaration and assignment.
• XST ignores delays and strengths given to a continuous assignment.
• Continuous assignments are allowed on wire and tri data types only.
Explicit Continuous Assignment Coding Example

wire par_eq_1;
....
assign par_eq_1 = select ? b : a;
Implicit Continuous Assignment Coding Example
wire temp_hold = a | b;

Behavioral Verilog Procedural Assignments

This section discusses Behavioral Verilog Procedural Assignments, and includes:
• About Behavioral Verilog Procedural Assignments
• Behavioral Verilog Combinatorial Always Blocks
• Behavioral Verilog If... Else Statement
• Behavioral Verilog Case Statements
• Behavioral Verilog For and Repeat Loops
• Behavioral Verilog While Loops
• Behavioral Verilog Sequential Always Blocks
• Behavioral Verilog Assign and Deassign Statements
• Behavioral Verilog Assignment Extension Past 32 Bits
• Behavioral Verilog Tasks and Functions
• Behavioral Verilog Recursive Tasks and Functions
• Behavioral Verilog Constant Functions
• Behavioral Verilog Blocking Versus Non-Blocking Procedural Assignments
About Behavioral Verilog Procedural Assignments

Behavioral Verilog procedural assignments are:
• Used to assign values to variables declared as regs.
• Introduced by always blocks, tasks, and functions
• Usually used to model registers and Finite State Machine (FSM) components.
XST supports:
• Combinatorial functions
• Combinatorial and sequential tasks
• Combinatorial and sequential always blocks
Behavioral Verilog Combinatorial Always Blocks

Combinatorial logic can be modeled efficiently using two forms of Verilog time control
statements:
• # (pound)
• * (asterisk)
Since the # (pound) time control statement is ignored for synthesis, this discussion
describes modeling combinatorial logic with the * (asterisk) time control statement.
A combinatorial always block has a sensitivity list appearing within parentheses after
the word always. An always block is activated if an event (value change or edge)
appears on one of the sensitivity list signals. This sensitivity list can contain any signal
that appears in conditions (if or case, for example), and any signal appearing on the
right-hand side of an assignment. By substituting an * (asterisk) without parentheses for
a list of signals, the always block is activated for an event in any of the always block’s
signals as described above.
In combinatorial processes, if a signal is not explicitly assigned in all branches of if or
case statements, XST generates a latch to hold the last value. To avoid latch creation, be
sure that all assigned signals in a combinatorial process are always explicitly assigned in
all paths of the process statements.

The following statements can be used in a process:

• Variable and signal assignment
• if...else statement
• case statement
• for and while loop statement
• Function and task call
Behavioral Verilog If... Else Statement

If... else statements use true/false conditions to execute statements.
• If the expression evaluates to true, the first statement is executed.
• If the expression evaluates to false (or x or z) the else statement is executed.
A block of multiple statements may be executed using begin and end keywords.
If... else statements may be nested.
Coding Example
The following coding example shows how a MUX can be described using an if... else
statement:
module mux4 (sel, a, b, c, d, outmux);
input [1:0] sel;
input [1:0] a, b, c, d;
output [1:0] outmux;
reg [1:0] outmux;
always @(sel or a or b or c or d)
begin
if (sel[1])
if (sel[0])
outmux = d;
else
outmux = c;
else
if (sel[0])
outmux = b;
else
outmux = a;
end
endmodule
Behavioral Verilog Case Statements

A case statement:
• Performs a comparison to an expression to evaluate one of a number of parallel
branches.
• Evaluates the branches in the order they are written.
– The first branch that evaluates to true is executed.
– If none of the branches match, the default branch is executed.
Do not use unsized integers in case statements. Always size integers to a specific number
of bits, or results can be unpredictable.
casez treats all z values in any bit position of the branch alternative as a dont care.
casex treats all x and z values in any bit position of the branch alternative as a dont care.

The question mark (?) can be used as a dont care in either the casez or casex case
statements.
Coding Example
The following coding example shows how a MUX can be described using a case
statement:
module mux4 (sel, a, b, c, d, outmux);
input [1:0] sel;
input [1:0] a, b, c, d;
output [1:0] outmux;
reg [1:0] outmux;
always @(sel or a or b or c or d)
begin
case (sel)
2’b00: outmux = a;
2’b01: outmux = b;
2’b10: outmux = c;
default: outmux = d;
endcase
end
endmodule
The preceding case statement evaluates the values of the input sel in priority order. To
avoid priority processing, Xilinx® recommends that you use a parallel-case Verilog
attribute to ensure parallel evaluation of the sel inputs as shown in the following:
(* parallel_case *) case(sel)
Behavioral Verilog For and Repeat Loops

When using always blocks, repetitive or bit slice structures can also be described using
the for statement or the repeat statement.
For Statement
The for statement is supported for:
• Constant bounds
• Stop test condition using one of the following operators:
– <
– <=
– >
– >=
• Next step computation falling in one of the following specifications:
– var = var + step
– var = var - step
where
♦ var is the loop variable
♦ step is a constant value
Repeat Statement
The repeat statement is supported for constant values only.

Disable Statements
Disable statements are not supported.
Coding Example
module countzeros (a, Count);
input [7:0] a;
output [2:0] Count;
reg [2:0] Count;
reg [2:0] Count_Aux;
integer i;
always @(a)
begin
Count_Aux = 3’b0;
for (i = 0; i < 8; i = i+1)
begin
if (!a[i])
Count_Aux = Count_Aux+1;
end
Count = Count_Aux;
end
endmodule
Behavioral Verilog While Loops

When using always blocks, use the while statement to execute repetitive procedures. A
while loop executes other statements until its test expression becomes false. It is not
executed if the test expression is initially false.
• The test expression is any valid Verilog expression.
• To prevent endless loops, use -loop_iteration_limit.
• while loops can have disable statements. The disable statement is used inside a
labeled block, since the syntax is disable <blockname>.
Coding Example
parameter P = 4;
always @(ID_complete)
begin : UNIDENTIFIED
integer i;
reg found;
unidentified = 0;
i = 0;
found = 0;
while (!found && (i < P))
begin
found = !ID_complete[i];
unidentified[i] = !ID_complete[i];
i = i + 1;
end
end

Behavioral Verilog Sequential Always Blocks

Sequential circuit description is based on always blocks with a sensitivity list. The
sensitivity list contains a maximum of three edge-triggered events:
• A clock signal event (mandatory)
• A reset signal event (possibly)
• A set signal event
One, and only one, if...else statement is accepted in such an always block.
An asynchronous part may appear before the synchronous part in the first and the
second branch of the if...else statement. Signals assigned in the asynchronous part are
assigned to the following constant values:
• 0
• 1
• X
• Z
• Any vector composed of these values
These same signals are also assigned in the synchronous part (that is, the last branch
of the if...else statement). The clock signal condition is the condition of the last branch
of the if...else statement.
8 Bit Register Using an Always Block Behavioral Verilog Coding Example

module seq1 (DI, CLK, DO);
input [7:0] DI;
input CLK;
output [7:0] DO;
reg [7:0] DO;

DO <= DI ;
8 Bit Register with Asynchronous Reset (High-True) Using an Always Block
Behavioral Verilog Coding Example
module EXAMPLE (DI, CLK, RST, DO);
input [7:0] DI;
input CLK, RST;
output [7:0] DO;
reg [7:0] DO;
always @(posedge CLK or posedge RST)

if (RST == 1’b1)
DO <= 8’b00000000;
else
DO <= DI;
endmodule

8 Bit Counter with Asynchronous Reset (Low-True) Using an Always Block

Behavioral Verilog Coding Example
module seq2 (CLK, RST, DO);
input CLK, RST;
output [7:0] DO;
reg [7:0] DO;
always @(posedge CLK or posedge RST)

if (RST == 1’b1)
DO <= 8’b00000000;
else
DO <= DO + 8’b00000001;
endmodule

Assign and deassign statements are supported within simple templates.
Behavioral Verilog Assign and Deassign Statements General Template

module assig (RST, SELECT, STATE, CLOCK, DATA_IN);
input RST;
input SELECT;
input CLOCK;
input [0:3] DATA_IN;
output [0:3] STATE;
reg [0:3] STATE;
always @ (RST)
if(RST)
begin
assign STATE = 4’b0;
end
else
begin
deassign STATE;
end
always @ (posedge CLOCK)

begin
STATE <= DATA_IN;
end
endmodule
The main limitations on support of the assign/deassign statement in XST are:
• For a given signal, there is only one assign/deassign statement.
• The assign/deassign statement is performed in the same always block through an
if/else statement.
• You cannot assign a bit/part select of a signal through an assign/deassign statement.

Behavioral Verilog Assign/Deassign Statement

For a given signal, there is only one assign/deassign statement. For example, XST rejects
the following design:
module dflop (RST, SET, STATE, CLOCK, DATA_IN);
input RST;
input SET;
input CLOCK;
input DATA_IN;
output STATE;
reg STATE;
always @ (RST) // block b1

if(RST)
else
deassign STATE;
always @ (SET) // block b1

if(SET)
else
deassign STATE;
always @ (posedge CLOCK) // block b2

begin
STATE <= DATA_IN;
end
endmodule
Behavioral Verilog Assign/Deassign Statement Performed in Same

Always Block
The assign/deassign statement is performed in the same always block through an
if...else statement. For example, XST rejects the following design:
module dflop (RST, SET, STATE, CLOCK, DATA_IN);
input RST;
input SET;
input CLOCK;
input DATA_IN;
output STATE;
reg STATE;
always @ (RST or SET) // block b1

case ({RST,SET})
2’b00: assign STATE = 1’b0;
2’b11: deassign STATE;
endcase

begin
STATE <= DATA_IN;
end
endmodule

Cannot Assign Bit/Part Select of Signal Through Assign/Deassign

Statement
You cannot assign a bit/part select of a signal through an assign/deassign statement. For
example, XST rejects the following design:
module assig (RST, SELECT, STATE, CLOCK, DATA_IN);
input RST;
input SELECT;
input CLOCK;
input [0:7] DATA_IN;
output [0:7] STATE;
reg [0:7] STATE;
always @ (RST) // block b1

if(RST)
begin
assign STATE[0:7] = 8’b0;
end
else
begin
deassign STATE[0:7];
end

begin
if (SELECT)
STATE [0:3] <= DATA_IN[0:3];
else
STATE [4:7] <= DATA_IN[4:7];
end
Behavioral Verilog Assignment Extension Past 32 Bits

If the expression on the left-hand side of an assignment is wider than the expression on
the right-hand side, the left-hand side is padded to the left according to the following
rules:
• If the right-hand expression is signed, the left-hand expression is padded with the
sign bit:
– 0 for positive
– 1 for negative
– z for high impedance
– x for unknown
• If the right-hand expression is unsigned, the left-hand expression is padded with
0(zeros).
• For unsized x or z constants only, the following rule applies. If the value of
the right-hand expression’s leftmost bit is z (high impedance) or x (unknown),
regardless of whether the right-hand expression is signed or unsigned, the left-hand
expression is padded with that value (z or x, respectively).
These rules follow the Verilog-2001 standard. They are not backwardly compatible
with Verilog-1995.

Behavioral Verilog Tasks and Functions

The declaration of a function or task is intended for handling blocks used multiple times
in a design. They must be declared and used in a module. The heading part contains the
parameters: input parameters (only) for functions and input/output/inout parameters
for tasks. The return value of a function can be declared either signed or unsigned. The
content is similar to the combinatorial always block content.
Coding Example One

The following coding example shows a function declared within a module.
• The ADD function declared is a single-bit adder.
• This function is called four times with the proper parameters in the architecture
to create a 4-bit adder.
module comb15 (A, B, CIN, S, COUT);
input [3:0] A, B;
input CIN;
output [3:0] S;
output COUT;
wire [1:0] S0, S1, S2, S3;
function signed [1:0] ADD;
input A, B, CIN;
reg S, COUT;
begin
S = A ^ B ^ CIN;
COUT = (A&B) | (A&CIN) | (B&CIN);
ADD = {COUT, S};
end
endfunction
assign S0 = ADD (A[0], B[0], CIN),

S1 = ADD (A[1], B[1], S0[1]),
S2 = ADD (A[2], B[2], S1[1]),
S3 = ADD (A[3], B[3], S2[1]),
S = {S3[0], S2[0], S1[0], S0[0]},
COUT = S3[1];
endmodule

Coding Example Two

The following coding example shows Coding Example One described with a task.
module EXAMPLE (A, B, CIN, S, COUT);
input [3:0] A, B;
input CIN;
output [3:0] S;
output COUT;
reg [3:0] S;
reg COUT;
reg [1:0] S0, S1, S2, S3;
task ADD;
input A, B, CIN;
output [1:0] C;
reg [1:0] C;
reg S, COUT;
begin
S = A ^ B ^ CIN;
COUT = (A&B) | (A&CIN) | (B&CIN);
C = {COUT, S};
end
endtask
always @(A or B or CIN)

begin
ADD (A[0], B[0], CIN, S0);
ADD (A[1], B[1], S0[1], S1);
ADD (A[2], B[2], S1[1], S2);
ADD (A[3], B[3], S2[1], S3);
S = {S3[0], S2[0], S1[0], S0[0]};
COUT = S3[1];
end
endmodule

Behavioral Verilog Recursive Tasks and Functions

Verilog-2001 supports recursive tasks and functions.
You can use recursion only with the automatic keyword.
To prevent endless recursive calls, the number of recursions is limited by default to 64.
Use -recursion_iteration_limit to control the number of allowed recursive calls.
Coding Example
function automatic [31:0] fac;
input [15:0] n;
if (n == 1)
fac = 1;
else
fac = n * fac(n-1); //recursive function call
endfunction

Behavioral Verilog Constant Functions

Verilog-2001 adds support for constant functions. XST supports function calls to
calculate constant values.
Coding Example
module rams_cf (clk, we, a, di, do);

parameter DEPTH=1024;
input clk;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [size(DEPTH):0];

if (we)
ram[a] <= di;
end
assign do = ram[a];
function integer size;

input depth;
integer i;
begin
size=1;
for (i=0; 2**i<depth; i=i+1)
size=i+1;
end
endfunction
endmodule

Behavioral Verilog Blocking Versus Non-Blocking Procedural

Assignments
The pound (#) and at symbol (@) time control statements delay execution of the
statement following them until the specified event is evaluated as true. Blocking and
non-blocking procedural assignments have time control built into their respective
assignment statement. The pound (#) delay is ignored for synthesis.
Behavioral Verilog Blocking Procedural Assignment Syntax Example

The syntax for a blocking procedural assignment is shown in the following example.
reg a; a = #10 (b | c);
or
if (in1) out = 1’b0; else out = in2;
As the name implies, these types of assignments block the current process from
continuing to execute additional statements at the same time. These should mainly be
used in simulation.
Non-blocking assignments, on the other hand, evaluate the expression when the
statement executes, but allow other statements in the same process to execute as well at
the same time. The variable change occurs only after the specified delay.
Behavioral Verilog Non-Blocking Procedural Assignment Syntax Example

The following syntax example shows the syntax for a non-blocking procedural
assignment.
variable <= @(posedge_or_negedge_bit) expression;
Coding Example
The following coding example shows how to use a non-blocking procedural assignment.
if (in1) out <= 1’b1; else out <= in2;

Behavioral Verilog Constants

By default, constants in Verilog are assumed to be decimal integers. They can be
specified explicitly in binary, octal, decimal, or hexadecimal by prefacing them with the
appropriate syntax. For example, the following all represent the same value:
• 4’b1010
• 4’o12
• 4’d10
• 4’ha
Behavioral Verilog Macros

Verilog provides a way to define macros as shown in the following coding example.
‘define TESTEQ1 4’b1101
Later in the design code, a reference to the defined macro is made as follows:
if (request == ‘TESTEQ1)
This is shown in the following coding example.
‘define myzero 0
assign mysig = ‘myzero;
The Verilog ‘ifdef and ‘endif constructs determine whether or not a macro is defined.
These constructs are used to define conditional compilation. If the macro called out by
the ‘ifdef command has been defined, that code is compiled. If not, the code following
the ‘else command is compiled. The ‘else is not required, but ‘endif must complete
the conditional statement.
The ‘ifdef and ‘endif constructs are shown in the following coding example.
‘ifdef MYVAR
module if_MYVAR_is_declared;
...
endmodule
‘else
module if_MYVAR_is_not_declared;
...
endmodule
‘endif
Verilog Macros (-define) allows you to define (or redefine) Verilog macros. This allows
you to easily modify the design configuration without any Hardware Description
Language (HDL) source modifications, such as for IP core generation and testing flows.

Behavioral Verilog Include Files

Verilog allows you to separate source code into more than one file. To reference the code
contained in another file, use the following syntax in the current file:
‘include "path/file-to-be-included"
The path can be relative or absolute.
Multiple ‘include statements are allowed in a single Verilog file. This feature makes
your code more manageable in a team design environment where different files describe
different modules of the design.
Identifying the Directory

To enable the file in your ‘include statement to be recognized, identify the directory
where it resides, either to ISE® Design Suite or to XST.
• Since ISE Design Suite searches the ISE Design Suite project directory by default,
adding the file to your project directory identifies the file to ISE Design Suite
• To direct ISE Design Suite to a different directory, include a path (relative or
absolute) in the ‘include statement in your source code.
• To point XST directly to your include file directory, use Verilog Include Directories
(-vlgincdir)
• If the ‘include file is required for ISE Design Suite to construct the design hierarchy,
the file need not be added to the project, but the file must either:
– Reside in the project directory
or
– Be referenced by a relative or absolute path
Include File Conflicts

Conflicts may occur when the specified file:
• Has been added to an ISE Design Suite project directory
and
• Is specified with ‘include
Coding Example
‘timescale 1 ns/1 ps
‘include "modules.v"
...
XST issues an error message:
ERROR:Xst:1068 - fifo.v, line 2. Duplicate declarations of
module’RAMB4_S8_S8’

Behavioral Verilog Comments

Behavioral Verilog supports two forms of comments as shown in the following table.
Behavioral Verilog comments are similar to the comments used in a language such as
C++.
Symbol Description Used for Example
// Double forward One-line comments // Define a one-line comment as illustrated by this sentence
slash
/* Slash asterisk Multi-line comments /* Define a multi-line comment by enclosing it as illustrated
by this sentence */

Behavioral Verilog Generate Statements

A generate statement allows you to dynamically create Verilog code from conditional
statements. This allows you to create repetitive structures or structures that are
appropriate only under certain conditions.
Structures likely to be created using a generate statement are:
• Primitive or module instances
• Initial or always procedural blocks
• Continuous assignments
• Net and variable declarations
• Parameter redefinitions
• Task or function definitions
Generate For Statements

Use a Behavioral Verilog generate for loop to create one or more instances that can be
placed inside a module. Use the generate for loop the same way you would a normal
Verilog for loop, with the following limitations:
• The index for a generate for loop has a genvar variable.
• The assignments in the for loop control refers to the genvar variable.
• The contents of the for loop are enclosed by begin and end statements. The begin
statement is named with a unique qualifier.
Coding Example
Following is an 8-bit adder using a generate for loop behavioral Verilog coding example.
generate
genvar i;
for (i=0; i<=7; i=i+1)

begin : for_name
adder add (a[8*i+7 : 8*i], b[8*i+7 : 8*i], ci[i], sum_for[8*i+7 : 8*i], c0_or[i+1]); end
endgenerate
Generate If... else Statements

Use a Behavioral Verilog generate if... else statement inside a generate block to
conditionally control which objects are generated.

Coding Example
In the following coding example of a generate if... else statement:
• generate controls the type of multiplier that is instantiated
• The contents of each branch of the if... else statement are enclosed by begin and
end statements.
• The begin statement is named with a unique qualifier.
generate
if (IF_WIDTH < 10)
begin : if_name
adder # (IF_WIDTH) u1 (a, b, sum_if);
end
else
begin : else_name
subtractor # (IF_WIDTH) u2 (a, b, sum_if);
end
endgenerate
Generate Case Statements

Use a Behavioral Verilog generate case statement inside a generate block to conditionally
control which objects are generated. Use a generate case statement when there are
several conditions to be tested to determine what the generated code would be.
• Each test statement in a generate case is enclosed by begin and end statements.
• The begin statement is named with a unique qualifier.
Coding Example
In the following coding example of a generate case statement, generate controls the
type of adder that is instantiated:
generate
case (WIDTH)
1:
begin : case1_name
adder #(WIDTH*8) x1 (a, b, ci, sum_case, c0_case);
end
2:
begin : case2_name
adder #(WIDTH*4) x2 (a, b, ci, sum_case, c0_case);
end
default:
begin : d_case_name
adder x3 (a, b, ci, sum_case, c0_case);
end
endcase
endgenerate

Chapter 17
XST Mixed Language Support

This chapter discusses XST Mixed Language Support, and includes:
• About XST Mixed Language Support
• Mixed Language Project Files
• VHDL and Verilog Boundary Rules in Mixed Language Projects
• Port Mapping in Mixed Language Projects
• Generics Support in Mixed Language Projects
• LSO Files in Mixed Language Projects
About XST Mixed Language Support

XST supports mixed VHDL and Verilog projects.
• Mixing VHDL and Verilog is restricted to design unit (cell) instantiation only.
– A VHDL design can instantiate a Verilog module.
– A Verilog design can instantiate a VHDL entity.
– No other mixing between VHDL and Verilog is not supported.
• In a VHDL design, a restricted subset of VHDL types, generics, and ports is allowed
on the boundary to a Verilog module.
• In a Verilog design, a restricted subset of Verilog types, parameters, and ports is
allowed on the boundary to a VHDL entity or configuration.
• XST binds VHDL design units to a Verilog module during Elaboration.
• Component instantiation based on default binding is used for binding Verilog
modules to a VHDL design unit.
• Configuration specification, direct instantiation and component configurations are
not supported for a Verilog module instantiation in VHDL.
• VHDL and Verilog project files are unified.
• VHDL and Verilog libraries are logically unified.
• Specification of the work directory for compilation (xsthdpdir), previously
available only for VHDL, is now available for Verilog.
• The xhdp.ini mechanism for mapping a logical library name to a physical directory
name on the host file system, previously available only for VHDL, is now available
for Verilog.
• Mixed language projects accept a search order used for searching unified logical
libraries in design units (cells). During Elaboration, XST follows this search order
for picking and binding a VHDL entity or a Verilog module to the mixed language
project.

Chapter 17: XST Mixed Language Support
Mixed Language Project Files

XST uses dedicated mixed language project files to support mixed VHDL and Verilog
designs. You can use this mixed language format not only for mixed projects, but also
for purely VHDL or Verilog projects.
• If you run XST from ISE® Design Suite, XST creates the project file. It is always
a mixed language project file.
• If you run XST from the command line, you must create the mixed language project
file yourself.
Project Type Set -ifmt to
command line mixed or value omitted
VHDL vhdl
Verilog verilog
The VHDL and Verilog formats can be used for existing designs.
The syntax for invoking a library or any external file in a mixed language project is:
language library file_name.ext
Coding Example
The following example shows how to invoke libraries in a mixed language project.
vhdl work my_vhdl1.vhd
verilog work my_vlg1.v
vhdl my_vhdl_lib my_vhdl2.vhd
verilog my_vlg_lib my_vlg2.v
• Each row specifies a single Hardware Description Language (HDL) design file.
• Each column has the meaning shown in the following table.
Column Syntax Example Specifies
First language vhdl Whether the HDL file
is VHDL or Verilog
Second library work The logic library
where the HDL is
compiled. The default
logic library is work.
Third file_name.ext my_vhdl1.vhd The name of the HDL
file.

VHDL and Verilog Boundary Rules in Mixed Language Projects

The boundary between VHDL and Verilog is enforced at the design unit level.
A VHDL design can instantiate a Verilog module.
A Verilog design can instantiate a VHDL entity.
Instantiating a Verilog Module in a VHDL Design

To instantiate a Verilog module in a VHDL design:
1. Declare a VHDL component with the same name (respecting case sensitivity) as
the Verilog module you want to instantiate. If the Verilog module name is not all
lowercase, use the case property to preserve the case of your Verilog module.
a. In ISE® Design Suite, select:
Process > Process Properties > Synthesis Options > Case > Maintain
or
b. Set the -case command line option to maintain
2. Instantiate the Verilog component as if you were instantiating a VHDL component.
Using a VHDL configuration declaration, you could attempt to bind this component to a
particular design unit from a particular library. Such binding is not supported. Only
default Verilog module binding is supported.
The only Verilog construct that can be instantiated in a VHDL design is a Verilog
module. No other Verilog constructs are visible to VHDL code.
During elaboration, all components subject to default binding are regarded as design
units with the same name as the corresponding component name. During binding, XST
treats a component name as a VHDL design unit name and searches for it in the logical
library work. If XST finds a VHDL design unit, XST binds it. If XST cannot find a VHDL
design unit, it treats the component name as a Verilog module name, and searches for it
using a case sensitive search. XST searches for the Verilog module in the user-specified
list of unified logical libraries in the user-specified search order.
XST selects the first Verilog module matching the name, and binds it.
Since libraries are unified, a Verilog cell by the same name as that of a VHDL design
unit cannot co-exist in the same logical library. A newly compiled cell/unit overrides a
previously compiled one.
Instantiating a VHDL Design Unit in a Verilog Design

• How to Instantiate a VHDL Entity
• Binding
• Limitations
How to Instantiate a VHDL Entity

To instantiate a VHDL entity:
1. Declare a module name with the same as name as the VHDL entity (optionally
followed by an architecture name) that you want to instantiate.
2. Perform a normal Verilog instantiation.

The only VHDL construct that can be instantiated in a Verilog design is a VHDL entity.
No other VHDL constructs are visible to Verilog code. When you do this, XST uses the
entity/architecture pair as the Verilog/VHDL boundary.
Binding
XST performs the binding during elaboration.
XST first:
1. Searches for a Verilog module as follows:
• Uses the name of the instantiated module.
• Searches in the user-specified list of unified logical libraries.
• Searches in the user-specified order.
• Ignores any architecture name specified in the module instantiation.
2. Binds the name if found.
If XST cannot find a Verilog module, then XST:
1. Treats the name of the instantiated module as a VHDL entity.
2. Searches for the VHDL entity as follows:
• Performs a case sensitive search
• Searches in the user-specified list of unified logical libraries
• Searches in the user-specified order
Note This assumes that a VHDL design unit was stored with an extended identifier.
3. Selects the first VHDL entity matching the name.
4. Binds the entity.
Limitations
XST has the following limitations when instantiating a VHDL design unit from a Verilog
module:
• Use explicit port association. Specify formal and effective port names in the port
map.
• All parameters are passed at instantiation, even if they are unchanged.
• The parameter override is named and not ordered. The parameter override occurs
through instantiation, and not through defparams.
Correct Use of Parameter Override Coding Example

ff #(.init(2’b01)) u1 (.sel(sel), .din(din), .dout(dout));
Incorrect Use of Parameter Override Coding Example
XST does not accept the following:
ff u1 (.sel(sel), .din(din), .dout(dout));
defparam u1.init = 2’b01;

Port Mapping in Mixed Language Projects

Port Mapping in mixed language projects includes:
• VHDL in Verilog Port Mapping
• Verilog in VHDL Port Mapping
• VHDL in Mixed Language Port Mapping
• Verilog in Mixed Language Port Mapping
VHDL in Verilog Port Mapping

For VHDL entities instantiated in Verilog designs, XST supports the following port types:
• in
• out
• inout
XST does not support VHDL buffer and linkage ports.
Verilog in VHDL Port Mapping

For Verilog modules instantiated in VHDL designs, XST supports the following port
types:
• input
• output
• inout
XST does not support connection to bi-directional pass options in Verilog.
XST does not support unnamed Verilog ports for mixed language boundaries.
Use an equivalent component declaration for connecting to a case sensitive port in a
Verilog module. By default, XST assumes Verilog ports are in all lowercase.
VHDL in Mixed Language Port Mapping

XST supports the following VHDL data types for mixed language designs:
• bit
• bit_vector
• std_logic
• std_ulogic
• std_ulogic_vector
Verilog in Mixed Language Port Mapping

XST supports the following Verilog data types for mixed language designs:
• wire
• reg

Generics Support in Mixed Language Projects

XST supports the following VHDL generic types and their Verilog equivalents for mixed
language designs:
• integer
• real
• string
• boolean
LSO Files in Mixed Language Projects

The Library Search Order (LSO) file specifies the search order that XST uses to link the
libraries used in VHDL and Verilog mixed language designs. By default, XST searches
the files specified in the project file in the order in which they appear in that file.
XST uses the default search order when:
• The DEFAULT_SEARCH_ORDER keyword is used in the LSO file, or
• The LSO file is not specified
Specifying the LSO File in ISE Design Suite

In ISE® Design Suite, the default name for the Library Search Order (LSO) file is
project_name.lso. If a project_name.lso file does not already exist, ISE Design
Suite automatically creates one.
If ISE Design Suite detects an existing project_name.lso file, this file is preserved and
used as is. In ISE Design Suite, the name of the project is the name of the top-level block.
In creating a default LSO file, ISE Design Suite places the DEFAULT_SEARCH_ORDER
keyword in the first line of the file.
Specifying the LSO File in the Command Line

Library Search Order (LSO) (-lso) specifies the Library Search Order (LSO) file when
running XST from the command line. If -lso is omitted, XST uses the default library
search order without using an LSO file.
LSO Rules
When processing a mixed language project, XST obeys the following search order rules,
depending on the contents of the Library Search Order (LSO) file:
• Library Search Order (LSO) Empty
• DEFAULT_SEARCH_ORDER Keyword Only
• DEFAULT_SEARCH_ORDER Keyword and List of Libraries
• List of Libraries Only
• DEFAULT_SEARCH_ORDER Keyword and Non-Existent Library Name”
Library Search Order (LSO) Empty

When the Library Search Order (LSO) file is empty, XST:
• Issues a warning stating that the LSO file is empty
• Searches the files specified in the project file using the default library search order
• Updates the LSO file by adding the list of libraries in the order that they appear
in the project file.

DEFAULT_SEARCH_ORDER Keyword Only

When the Library Search Order (LSO) file contains only the DEFAULT_SEARCH_ORDER
keyword, XST:
• Searches the specified library files in the order in which they appear in the project file
• Updates the LSO file by:
– Removing the DEFAULT_SEARCH_ORDER keyword
– Adding the list of libraries to the LSO file in the order in which they appear
in the project file
For a project file, my_proj.prj, with the following contents:
vhdl vhlib1 f1.vhd verilog rtfllib f1.v vhdl vhlib2 f3.vhd LSO
file Created by ProjNav
and an LSO file, my_proj.lso, created by ISE® Design Suite, with the following
contents:
DEFAULT_SEARCH_ORDER
XST uses the following search order.
vhlib1 rtfllib vhlib2
After processing, the contents of my_proj.lso is:
DEFAULT_SEARCH_ORDER Keyword and List of Libraries

When the Library Search Order (LSO) file contains the DEFAULT_SEARCH_ORDER
keyword, and a list of the libraries, XST:
• Searches the specified library files in the order in which they appear in the project file
• Ignores the list of library files in the LSO file
• Leaves the LSO file unchanged
vhdl vhlib1 f1.vhd verilog rtfllib f1.v vhdl vhlib2 f3.vhd
and an LSO file, my_proj.lso, created with the following contents:
rtfllib vhlib2 vhlib1 DEFAULT_SEARCH_ORDER
XST uses the following search order:
rtfllib vhlib2 vhlib1 DEFAULT_SEARCH_ORDER
List of Libraries Only

When the Library Search Order (LSO) file contains a list of the libraries without the
DEFAULT_SEARCH_ORDER keyword, XST:
• Searches the library files in the order in which they appear in the LSO file
• Leaves the LSO file unchanged

rtfllib vhlib2 vhlib1

DEFAULT_SEARCH_ORDER Keyword and Non-Existent Library Name

When the Library Search Order (LSO) file contains a library name that does not exist in
the project or INI file, and the LSO file does not contain the DEFAULT_SEARCH_ORDER
keyword, XST ignores the library.
personal_lib rtfllib vhlib2 vhlib1

Chapter 18
XST Log File

This chapter discusses the XST Log File, and includes:
• XST Log File Contents
• Reducing the Size of the XST Log File
• Macros in XST Log Files
• XST Log File Examples
XST FPGA Log File Contents

The XST FPGA log file contains:
• Copyright Statement
• Table of Contents
• Synthesis Options Summary
• HDL Compilation
• Design Hierarchy Analyzer
• HDL Analysis
• HDL Synthesis Report
• Advanced HDL Synthesis Report
• Low Level Synthesis
• Partition Report
• Final Report
Copyright Statement
The XST FPGA log file copyright statement contains:
• ISE® Design Suite release number
• Xilinx® notice of copyright
Table of Contents
The XST FPGA log file table of contents lists the major sections in the log file. These
headings are not linked. Use the Find function in your text editor.

Chapter 18: XST Log File
Synthesis Options Summary

The XST FPGA log file Synthesis Options Summary contains information relating to:
• Source Parameters
• Target Parameters
• Source Options
• Target Options
• General Options
• Other Options
HDL Compilation
For information on Hardware Description Language (HDL) Compilation, see:
XST FPGA Log File HDL Analysis
Design Hierarchy Analyzer

For information on Design Hierarchy Analyzer, see:
XST FPGA Log File HDL Analysis
HDL Analysis
During Hardware Description Language (HDL) Compilation, Design Hierarchy
Analyzer, and HDL Analysis, XST:
• Parses and analyzes VHDL and Verilog files
• Recognizes the design hierarchy
• Gives the names of the libraries into which they are compiled
During this step, XST may report:
• Potential mismatches between synthesis and simulation results
• Potential multi-sources
• Other issues

During Hardware Description Language (HDL) Synthesis, XST tries to recognize as
many basic macros as possible to create a technology-specific implementation. This is
done on a block by block basis. At the end of this step, XST issues the HDL Synthesis
Report.
For more information about the processing of each macro and the corresponding
messages issued during synthesis, see:

XST performs advanced macro recognition and inference. In this step, XST:
• Recognizes, for example, dynamic shift registers
• Implements pipelined multipliers
• Codes state machines

The Advanced HDL Synthesis Report contains a summary of recognized macros in

the overall design, sorted by macro type.
Low Level Synthesis

In the XST FPGA Log File Low Level Synthesis phase, XST reports the potential removal
of, for example:
• equivalent flip-flops
• register replication
FPGA Optimization Report Section
Partition Report
If the design is partitioned, the XST FPGA log file Partition Report contains information
detailing the design partitions.

Final Report
The XST FPGA log file Final Report includes:
• Final Results, including
– RTL Top Level Output File Name (for example, stopwatch.ngr)
– Top Level Output File Name (for example, stopwatch)
– Output Format (for example, NGC)
– Optimization Goal (for example, Speed)
– Whether the Keep Hierarchy constraint is used (for example, No)
• Cell usage
Cell usage reports on, for example, the number and type of BELS, Clock Buffers,
and IO Buffers.
• Device Utilization Summary
The Device Utilization Summary estimates the number of slices, and gives, for
example, the number of flip-flops, IOBs, and BRAMS. The Device Utilization
Summary closely approximates the report produced by MAP.
• Partition Resource Summary
The Partition Resource Summary estimates the number of slices, and gives, for
example, the number of flip-flops, IOBs, and BRAMS for each partition. The
Partition Resource Summary closely resembles the report produced by MAP.
• Timing Report
At the end of synthesis, XST reports the timing information for the design. The
Timing Report shows the information for all four possible domains of a netlist:
– register to register
– input to register
– register to outpad
– inpad to outpad
For an example, see:
Timing Report section in XST FPGA Log File Example
FPGA Optimization Report Section
• Encrypted Modules
If a design contains encrypted modules, XST hides the information about these
modules.

Reducing the Size of the XST Log File

To reduce the size of the XST Log File:
• Use Message Filtering
• Use Quiet Mode
• Use Silent Mode
• Hide Specific Messages
Use Message Filtering

When running XST from ISE® Design Suite, use the Message Filtering wizard to filter
specific messages out of the log file.
Using the Message Filters in the ISE Design Suite Help
Use Quiet Mode

Quiet Mode limits the number of messages printed to the computer screen (stdout).
To invoke Quiet Mode, set -intstyle to either of the following:
• ise
Formats messages for ISE® Design Suite
• xflow
Formats messages for XFLOW
Normally, XST prints the entire log to stdout. In Quiet Mode, XST does not print the
following portions of the log to stdout:
• Copyright Message
• Table of Contents
• Synthesis Options Summary
• The following portions of the Final Report
– Final Results header for CPLD devices
– Final Results section for FPGA devices
– A note in the Timing Report stating that the timing numbers are only a synthesis
estimate.
– Timing Detail
– CPU (XST runtime)
– Memory usage
The following sections are still available for FPGA devices:
• Device Utilization Summary
• Clock Information
• Timing Summary
Use Silent Mode

Silent Mode prevents any messages from being sent to the computer screen (stdout),
although XST continues to generate the entire log file.
To invoke Silent Mode, set the -intstyle command line option to:

silent
Hide Specific Messages

• XIL_XST_HIDEMESSAGES Environment Variable Values
• Messages Hidden When Value is Set to hdl_level and hdl_and_low_levels
• Messages Hidden When Value is Set to low_level or hdl_and_low_levels
XIL_XST_HIDEMESSAGES Environment Variable Values

To hide specific messages at the HDL or Low Level Synthesis steps, set the
XIL_XST_HIDEMESSAGES environment variable to one of the values shown in the
following table.
Value Meaning
none (default) Maximum verbosity. All messages are printed
out.
hdl_level Reduce verbosity during VHDL or Verilog
Analysis and HDL Basic and Advanced
Synthesis.
low_level Reduce verbosity during Low-level Synthesis.
hdl_and_low_levels Reduce verbosity at all stages.
Messages Hidden When Value is Set to hdl_level and hdl_and_low_levels

The following messages are hidden when the value of the XIL_XST_HIDEMESSAGES
environment variable is set to hdl_level and hdl_and_low_levels:
• WARNING:HDLCompilers:38 - design.v line 5 Macro ’my_macro’
redefined
Note This message is issued by the Verilog compiler only.
• WARNING:Xst:916 - design.vhd line 5: Delay is ignored for
synthesis.
• WARNING:Xst:766 - design.vhd line 5: Generating a Black Box
for component comp.
• Instantiating component comp from Library lib.
• Set user-defined property "LOC = X1Y1" for instance inst in
unit block.
• Set user-defined property "RLOC = X1Y1" for instance inst in
unit block.
• Set user-defined property "INIT = 1" for instance inst in unit
block.
• Register reg1 equivalent to reg2 has been removed.

Messages Hidden When Value is Set to low_level or hdl_and_low_levels

The following messages are hidden when the value of the XIL_XST_HIDEMESSAGES
environment variable is set to low_level or hdl_and_low_levels:
• WARNING:Xst:382 - Register reg1 is equivalent to reg2.
Register reg1 equivalent to reg2 has been removed.
• WARNING:Xst:1710 - FF/Latch reg (without init value) is
constant in block block.
• WARNING:Xst 1293 - FF/Latch reg is constant in block block.
• WARNING:Xst:1291 - FF/Latch reg is unconnected in block block.
• WARNING:Xst:1426 - The value init of the FF/Latch reg hinders
the constant cleaning in the block block. You could achieve
better results by setting this init to value.
Macros in XST Log Files

XST Log Files contain detailed information about the set of macros and associated
signals inferred by XST from the VHDL or Verilog source on a block by block basis.
Macro inference is done in two steps:
1. HDL Synthesis
XST recognizes as many simple macro blocks as possible, such as adders,
subtractors, and registers.
2. Advanced HDL Synthesis
XST does additional macro processing by improving the macros (for example,
pipelining of multipliers) recognized at the HDL synthesis step, or by creating
the new, more complex ones, such as dynamic shift registers. The Macro
Recognition report at the Advanced HDL Synthesis step is formatted the same as
the corresponding report at the HDL Synthesis step.
XST gives overall statistics of recognized macros twice:
• After the HDL Synthesis step
• After the Advanced HDL Synthesis step
XST no longer lists statistics of preserved macros in the final report.
XST Log File Examples

• Recognized Macros XST Log File Example
• Additional Macro Processing XST Log File Example
• XST FPGA Log File Example
• XST CPLD Log File Example

Recognized Macros XST Log File Example

The following log file example shows the set of recognized macros on a block by block
basis, as well as the overall macro statistics after this step.
===================================================
* HDL Synthesis *
===================================================
...
Synthesizing Unit <decode>.
Related source file is "decode.vhd".
Found 16x10-bit ROM for signal <one_hot>.
Summary:
inferred 1 ROM(s).
Unit <decode> synthesized.
Synthesizing Unit <statmach>.

Related source file is "statmach.vhd".
Found finite state machine <FSM_0> for signal <current_state>.
------------------------------------------------------
| States | 6 |
| Transitions | 11 |
| Inputs | 1 |
| Outputs | 2 |
| Clock | CLK (rising_edge) |
| Reset | RESET (positive) |
| Reset State | clear |
| Power Up State | clear |
------------------------------------------------------
Summary:
Unit <statmach> synthesized.
...
==============================================================
Macro Statistics
# ROMs : 3
16x10-bit ROM : 1
16x7-bit ROM : 2
# Counters : 2
==============================================================
...

Additional Macro Processing XST Log File Example

The following XST FPGA log file example shows the additional macro processing done
during the Advanced HDL Synthesis step and the overall macro statistics after this step.
===================================================
===================================================

Optimizing FSM <MACHINE/current_state/FSM_0> on signal <current_state[1:3]> with gray encoding.
----------------------
State | Encoding
----------------------
clear | 000
zero | 001
start | 011
counting | 010
stop | 110
stopped | 111
----------------------
============================================================
Macro Statistics
# FSMs : 1
# ROMs : 3
16x10-bit ROM : 1
16x7-bit ROM : 2
# Counters : 2
# Registers : 3
Flip-Flops/Latches : 3
============================================================
...
XST FPGA Log File Example

The following is an example of an XST log file for FPGA synthesis. Release 10.1 - xst
K.31 (nt64)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT

=============================
* Synthesis Options Summary *
=============================
---- Source Parameters
Input File Name : "stopwatch.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "stopwatch"
Output Format : NGC
Target Device : xc4vlx15-12-sf363
---- Source Options
Top Module Name : stopwatch
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Use DSP Block : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 32
Number of Regional Clock Buffers : 16
Register Duplication : YES

Slice Packing : YES

Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Library Search Order : stopwatch.lso
Keep Hierarchy : NO
Netlist Hierarchy : as_optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
===================================================
===================================================
* HDL Compilation *
===================================================
Compiling verilog file "smallcntr.v" in library work
Compiling verilog file "statmach.v" in library work
Module <smallcntr> compiled
Compiling verilog file "hex2led.v" in library work
Module <statmach> compiled
Compiling verilog file "decode.v" in library work

Module <hex2led> compiled

Compiling verilog file "cnt60.v" in library work
Module <decode> compiled
Compiling verilog file "stopwatch.v" in library work
Module <cnt60> compiled
Module <stopwatch> compiled
No errors in compilation
Analysis of file <"stopwatch.prj"> succeeded.
Compiling vhdl file "C:/xst/watchver/tenths.vhd" in Library work.
Entity <tenths> compiled.
Entity <tenths> (Architecture <tenths_a>) compiled.
Compiling vhdl file "C:/xst/watchver/dcm1.vhd" in Library work.
Entity <dcm1> compiled.
Entity <dcm1> (Architecture <BEHAVIORAL>) compiled.
===================================================
* Design Hierarchy Analysis *
===================================================
Analyzing hierarchy for module <stopwatch> in library <work>.
Analyzing hierarchy for entity <dcm1> in library <work>
(architecture <BEHAVIORAL>).
Analyzing hierarchy for module <statmach> in library <work> with
parameters.
clear = "000001"
counting = "001000"
start = "000100"
stop = "010000"
stopped = "100000"
zero = "000010"
Analyzing hierarchy for module <decode> in library <work>.
Analyzing hierarchy for module <cnt60> in library <work>.
Analyzing hierarchy for module <hex2led> in library <work>.
Analyzing hierarchy for module <smallcntr> in library <work>.
===================================================
* HDL Analysis *
===================================================
Analyzing top module <stopwatch>.
Module <stopwatch> is correct for synthesis.
Analyzing Entity <dcm1> in library <work> (Architecture
<BEHAVIORAL>).

Set user-defined property "CAPACITANCE = DONT_CARE" for instance

<CLKIN_IBUFG_INST> in unit <dcm1>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance
Set user-defined property "IOSTANDARD = DEFAULT" for instance
Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for
instance <DCM_INST> in unit <dcm1>.
Set user-defined property "CLKFX_DIVIDE = 1" for instance
<DCM_INST> in unit <dcm1>.
Set user-defined property "CLKFX_MULTIPLY = 4" for instance
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for
Set user-defined property "CLKIN_PERIOD = 20.0000000000000000"
for instance <DCM_INST> in unit <dcm1>.
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for
Set user-defined property "CLK_FEEDBACK = 1X" for instance
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS"
for instance <DCM_INST> in unit <dcm1>.
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance
Set user-defined property "DSS_MODE = NONE" for instance
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for
Set user-defined property "FACTORY_JF = C080" for instance
Set user-defined property "PHASE_SHIFT = 0" for instance
Set user-defined property "SIM_MODE = SAFE" for instance
Set user-defined property "STARTUP_WAIT = TRUE" for instance
Entity <dcm1> analyzed. Unit <dcm1> generated.
Analyzing module <statmach> in library <work>.
clear = 6’b000001
counting = 6’b001000
start = 6’b000100
stop = 6’b010000
stopped = 6’b100000

zero = 6’b000010
Module <statmach> is correct for synthesis.
Analyzing module <decode> in library <work>.
Module <decode> is correct for synthesis.
Analyzing module <cnt60> in library <work>.
Module <cnt60> is correct for synthesis.
Analyzing module <smallcntr> in library <work>.
Module <smallcntr> is correct for synthesis.
Analyzing module <hex2led> in library <work>.
Module <hex2led> is correct for synthesis.
===================================================
* HDL Synthesis *
===================================================
Performing bidirectional port resolution...
Related source file is "statmach.v".
-------------------------------------------------
| States | 6 |
| Inputs | 2 |
| Outputs | 2 |
| Reset State | 000001 |
-------------------------------------------------
Found 1-bit register for signal <CLKEN>.
Found 1-bit register for signal <RST>.
Summary:
Related source file is "decode.v".
Found 16x10-bit ROM for signal <ONE_HOT>.

Summary:
inferred 1 ROM(s).
Unit <decode> synthesized.
Synthesizing Unit <hex2led>.
Related source file is "hex2led.v".
Found 16x7-bit ROM for signal <LED>.
Summary:
inferred 1 ROM(s).
Unit <hex2led> synthesized.
Synthesizing Unit <smallcntr>.
Related source file is "smallcntr.v".
Found 4-bit up counter for signal <QOUT>.
Summary:
Unit <smallcntr> synthesized.
Synthesizing Unit <dcm1>.
Related source file is "C:/xst/watchver/dcm1.vhd".
Unit <dcm1> synthesized.
Synthesizing Unit <cnt60>.
Related source file is "cnt60.v".
Unit <cnt60> synthesized.
Synthesizing Unit <stopwatch>.
Related source file is "stopwatch.v".
Unit <stopwatch> synthesized.
=======================================
Macro Statistics
# ROMs : 3
16x10-bit ROM : 1
16x7-bit ROM : 2
# Counters : 2
# Registers : 2
1-bit register : 2
===================================================
===================================================
===================================================


Optimizing FSM <MACHINE/current_state/FSM> on signal
<current_state[1:3]> with sequential encoding.
--------------------
State | Encoding
--------------------
000001 | 000
000010 | 001
000100 | 010
001000 | 011
010000 | 100
100000 | 101
--------------------
Loading device for application Rf_Device from file ’4vlx15.nph’
in environment C:\xilinx.
Executing edif2ngd -noa "tenths.edn" "tenths.ngo"
Release 10.1 - edif2ngd K.31 (nt64)
INFO:NgdBuild - Release 10.1 edif2ngd K.31 (nt64)
INFO:NgdBuild - Copyright (c) 1995-2008 Xilinx, Inc. All rights
reserved.
Writing module to "tenths.ngo"...
Reading core <tenths_c_counter_binary_v8_0_xst_1.ngc>.
Loading core <tenths_c_counter_binary_v8_0_xst_1> for timing and
area information for instance <BU2>.
Loading core <tenths> for timing and area information for
instance <xcounter>.
===================================================
Macro Statistics
# ROMs : 3
16x10-bit ROM : 1
16x7-bit ROM : 2
# Counters : 2
# Registers : 5
Flip-Flops : 5
===================================================
===================================================

===================================================
Optimizing unit <stopwatch> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block stopwatch,
actual ratio is 0.
Number of LUT replicated for flop-pair packing : 0
Final Macro Processing ...
===================================================
Final Register Report
Macro Statistics
# Registers : 13
Flip-Flops : 13
===================================================
===================================================
* Partition Report *
===================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
===================================================
* Final Report *
===================================================
Final Results
RTL Top Level Output File Name : stopwatch.ngr
Top Level Output File Name : stopwatch
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs : 27
Cell Usage :
# BELS : 70
# GND : 2
# INV : 1
# LUT1 : 3
# LUT2 : 1
# LUT2_L : 1

# LUT3 : 8
# LUT3_D : 1
# LUT3_L : 1
# LUT4 : 37
# LUT4_D : 1
# LUT4_L : 4
# MUXCY : 3
# MUXF5 : 2
# VCC : 1
# XORCY : 4
# FDC : 13
# FDCE : 4
# Clock Buffers : 1
# BUFG : 1
# IO Buffers : 27
# IBUF : 2
# IBUFG : 1
# OBUF : 24
# DCM_ADVs : 1
# DCM_ADV : 1
===================================================
Device utilization summary:
---------------------------
Selected Device : 4vlx15sf363-12
Number of Slices: 32 out of 6144 0%
Number of Slice Flip Flops: 17 out of 12288 0%
Number of 4 input LUTs: 58 out of 12288 0%
Number of IOs: 27
Number of bonded IOBs: 27 out of 240 11%
Number of GCLKs: 1 out of 32 3%
Number of DCM_ADVs: 1 out of 4 25%
---------------------------
Partition Resource Summary:
---------------------------
---------------------------
===================================================

TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+-----------
Clock Signal | Clock buffer (FF name) | Load |
-----------------------------------+-----------
CLK | Inst_dcm1/DCM_INST:CLK0| 17 |
-----------------------------------+-----------
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+---------------
Control Signal | Buffer (FF name) | Load |
-----------------------------------+---------------
MACHINE/RST(MACHINE/RST:Q) | NONE(sixty/lsbcount/QOUT_1)| 8 |
RESET | IBUF | 5 |
sixty/msbclr(sixty/msbclr_f5:O) | NONE(sixty/msbcount/QOUT_0)|
4 |
-----------------------------------+---------------
Timing Summary:
---------------
Speed Grade: -12
Maximum output required time after clock: 4.617ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
===================================================
Timing constraint: Default period analysis for Clock ’CLK’
Clock period: 2.282ns (frequency: 438.212MHz)
---------------------------------------------------
Delay: 2.282ns (Levels of Logic = 4)
Source: xcounter/BU2/U0/q_i_1 (FF)
Destination: sixty/msbcount/QOUT_1 (FF)


Data Path: xcounter/BU2/U0/q_i_1 to sixty/msbcount/QOUT_1
Gate Net
---------------------------------------- ------------
FDCE:C->Q 12 0.272 0.672 U0/q_i_1 (q(1))
LUT4:I0->O 11 0.147 0.492 U0/thresh0_i_cmp_eq00001 (thresh0)
end scope: ’BU2’
end scope: ’xcounter’
LUT4_D:I3->O 1 0.147 0.388 sixty/msbce (sixty/msbce)
LUT3:I2->O 1 0.147 0.000 sixty/msbcount/QOUT_1_rstpot
(sixty/msbcount/QOUT_1_rstpot)
FDC:D 0.017 sixty/msbcount/QOUT_1
----------------------------------------
(32.0% logic, 68.0% route)
===================================================
Timing constraint: Default OFFSET IN BEFORE for Clock ’CLK’
---------------------------------------------------
Offset: 1.655ns (Levels of Logic = 3)
Source: STRTSTOP (PAD)
Destination: MACHINE/current_state_FSM_FFd3 (FF)
Data Path: STRTSTOP to MACHINE/current_state_FSM_FFd3
Gate Net
---------------------------------------- ------------
IBUF:I->O 4 0.754 0.446 STRTSTOP_IBUF (STRTSTOP_IBUF)
LUT4:I2->O 1 0.147 0.000 MACHINE/current_state_FSM_FFd3-In_F
(N48)
MUXF5:I0->O 1 0.291 0.000 MACHINE/current_state_FSM_FFd3-In
(MACHINE/current_state_FSM_FFd3-In)
FDC:D 0.017 MACHINE/current_state_FSM_FFd3
----------------------------------------
(73.0% logic, 27.0% route)
===================================================

Timing constraint: Default OFFSET OUT AFTER for Clock ’CLK’

---------------------------------------------------
Offset: 4.617ns (Levels of Logic = 2)
Source: sixty/lsbcount/QOUT_1 (FF)
Destination: ONESOUT<6> (PAD)
Data Path: sixty/lsbcount/QOUT_1 to ONESOUT<6>
Gate Net
---------------------------------------- ------------
FDC:C->Q 13 0.272 0.677 sixty/lsbcount/QOUT_1
(sixty/lsbcount/QOUT_1)
LUT4:I0->O 1 0.147 0.266 lsbled/Mrom_LED21 (lsbled/Mrom_LED2)
OBUF:I->O 3.255 ONESOUT_2_OBUF (ONESOUT<2>)
----------------------------------------
(79.6% logic, 20.4% route)
===================================================
Total REAL time to Xst completion: 20.00 secs
Total CPU time to Xst completion: 19.53 secs
-->
Total memory usage is 333688 kilobytes
Number of errors : 0 ( 0 filtered)
)Number of warnings : 0 ( 0 filtered
Number of infos : 1 ( 0 filtered)
XST CPLD Log File Example

The following is an example of an XST log file for CPLD
synthesis.
Release 10.1 - xst K.31 (nt64)
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis

6.1) Advanced HDL Synthesis Report

7) Low Level Synthesis
8) Partition Report
9) Final Report
======================================================
* Synthesis Options Summary *
======================================================
---- Source Parameters
Input File Name : "stopwatch.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "stopwatch"
Output Format : NGC
Target Device : CoolRunner2 CPLDs
---- Source Options
Top Module Name : stopwatch
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : YES
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Effort : 1
Library Search Order : stopwatch.lso
Keep Hierarchy : YES
Netlist Hierarchy : as_optimized
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Verilog 2001 : YES

---- Other Options

Clock Enable : YES
wysiwyg : NO
======================================================
======================================================
* HDL Compilation *
======================================================
Compiling verilog file "smallcntr.v" in library work
Compiling verilog file "tenths.v" in library work
Module <smallcntr> compiled
Compiling verilog file "statmach.v" in library work
Module <tenths> compiled
Compiling verilog file "hex2led.v" in library work
Module <statmach> compiled
Compiling verilog file "decode.v" in library work
Module <hex2led> compiled
Compiling verilog file "cnt60.v" in library work
Module <decode> compiled
Compiling verilog file "stopwatch.v" in library work
Module <cnt60> compiled
Module <stopwatch> compiled
No errors in compilation
Analysis of file <"stopwatch.prj"> succeeded.
======================================================
* Design Hierarchy Analysis *
======================================================
Analyzing hierarchy for module <stopwatch> in library <work>.
Analyzing hierarchy for module <statmach> in library <work> with
parameters.
clear = "000001"
counting = "001000"
start = "000100"
stop = "010000"
stopped = "100000"
zero = "000010"
Analyzing hierarchy for module <tenths> in library <work>.
Analyzing hierarchy for module <decode> in library <work>.
Analyzing hierarchy for module <cnt60> in library <work>.
Analyzing hierarchy for module <hex2led> in library <work>.

Analyzing hierarchy for module <smallcntr> in library <work>.

======================================================
* HDL Analysis *
======================================================
Analyzing top module <stopwatch>.
Module <stopwatch> is correct for synthesis.
Analyzing module <statmach> in library <work>.
clear = 6’b000001
counting = 6’b001000
start = 6’b000100
stop = 6’b010000
stopped = 6’b100000
zero = 6’b000010
Module <statmach> is correct for synthesis.
Analyzing module <tenths> in library <work>.
Module <tenths> is correct for synthesis.
Analyzing module <decode> in library <work>.
Module <decode> is correct for synthesis.
Analyzing module <cnt60> in library <work>.
Module <cnt60> is correct for synthesis.
Analyzing module <smallcntr> in library <work>.
Module <smallcntr> is correct for synthesis.
Analyzing module <hex2led> in library <work>.
Module <hex2led> is correct for synthesis.
======================================================
* HDL Synthesis *
======================================================
Performing bidirectional port resolution...
Related source file is "statmach.v".
-------------------------------------------------
| States | 6 |
| Inputs | 2 |
| Outputs | 2 |


| Reset State | 000001 |
| Implementation | automatic |
-------------------------------------------------
Found 1-bit register for signal <CLKEN>.
Found 1-bit register for signal <RST>.
Summary:
Synthesizing Unit <tenths>.
Related source file is "tenths.v".
Found 4-bit up counter for signal <Q>.
Summary:
Unit <tenths> synthesized.
Related source file is "decode.v".
Found 16x10-bit ROM for signal <ONE_HOT>.
Summary:
inferred 1 ROM(s).
.Unit <decode> synthesized
Synthesizing Unit <hex2led>.
Related source file is "hex2led.v".
Found 16x7-bit ROM for signal <LED>.
Summary:
inferred 1 ROM(s).
Unit <hex2led> synthesized.
Synthesizing Unit <smallcntr>.
Related source file is "smallcntr.v".
Found 4-bit up counter for signal <QOUT>.
Summary:
Unit <smallcntr> synthesized.
Synthesizing Unit <cnt60>.
Related source file is "cnt60.v".
Unit <cnt60> synthesized.

Synthesizing Unit <stopwatch>.

Related source file is "stopwatch.v".
Found 1-bit register for signal <strtstopinv>.
Summary:
Unit <stopwatch> synthesized.
======================================================
Macro Statistics
# ROMs : 3
16x10-bit ROM : 1
16x7-bit ROM : 2
# Counters : 3
# Registers : 3
1-bit register : 3
======================================================
======================================================
======================================================
Optimizing FSM <MACHINE/current_state/FSM> on signal
<current_state[1:3]> with sequential encoding.
--------------------
State | Encoding
--------------------
000001 | 000
000010 | 001
000100 | 010
001000 | 011
010000 | 100
100000 | 101
--------------------
======================================================
Macro Statistics
# ROMs : 3
16x10-bit ROM : 1
16x7-bit ROM : 2

# Counters : 3
# Registers : 6
Flip-Flops : 6
======================================================
======================================================
======================================================
Optimizing unit <stopwatch> ...
Optimizing unit <statmach> ...
Optimizing unit <decode> ...
Optimizing unit <hex2led> ...
Optimizing unit <tenths> ...
Optimizing unit <smallcntr> ...
Optimizing unit <cnt60> ...
============================================
* Partition Report *
======================================================
Partition Implementation Status
-------------------------------
-------------------------------
======================================================
* Final Report *
======================================================
Final Results
RTL Top Level Output File Name : stopwatch.ngr
Top Level Output File Name : stopwatch
Output Format : NGC
Keep Hierarchy : YES
Target Technology : CoolRunner2 CPLDs
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 28

Cell Usage :
# BELS : 413
# AND2 : 120
# AND3 : 10
# AND4 : 6
# INV : 174
# OR2 : 93
# OR3 : 1
# XOR2 : 9
# FD : 1
# FDC : 5
# FDCE : 12
# IO Buffers : 28
# IBUF : 4
# OBUF : 24
======================================================
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.83 secs
-->
Total memory usage is 196636 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Chapter 19
XST Naming Conventions

This chapter discusses XST Naming Conventions, and includes:
• XST Net Naming Conventions
• XST Instance Naming Conventions
• XST Name Generation Control
XST Net Naming Conventions

The following XST net naming conventions are listed in order of naming priority:
1. Maintain external pin names.
2. Keep hierarchy in signal names, using forward slashes (/) or underscores (_) as
hierarchy designators.
3. Maintain output signal names of registers, including state bits. Use the hierarchical
name from the level where the register was inferred.
4. Ensure that output signals of clock buffers get _clockbuffertype (such as _BUFGP
or _IBUFG) follow the clock signal name.
5. Maintain input nets to registers and tristates names.
6. Maintain names of signals connected to primitives and black boxes.
7. Name output net names of IBUFs using the form net_name_IBUF. For example, for
an IBUF with an output net name of DIN, the output IBUF net name is DIN_IBUF.
8. Name input net names to OBUFs using the form net_name_OBUF. For example,
for an OBUF with an input net name of DOUT, the input OBUF net name is
DOUT_OBUF.
9. Base names for internal (combinatorial) nets on user HDL signal names where
possible.
XST Instance Naming Conventions

Xilinx® highly recommends that you use the following instance naming conventions.
To use instance naming conventions from previous releases of ISE® Design Suite, insert
the following command line option in the XST command line:
-old_instance_names 1

Chapter 19: XST Naming Conventions
The following rules are listed in order of naming priority:

1. Keep hierarchy in instance names, using forward slashes (/) or underscores (_) as
hierarchy designators.
When instance names are generated from VHDL or Verilog generate statements,
labels from generate statements are used in composition of instance names.
For example, for the following VHDL generate statement:
i1_loop: for i in 1 to 10 generate
inst_lut:LUT2 generic map (INIT => "00")
XST generates the following instance names for LUT2:
i1_loop[1].inst_lut
i1_loop[2].inst_lut
i1_loop[9].inst_lut
...
i1_loop[10].inst_lut
2. Name register instances, including state bits, for the output signal.
3. Name clock buffer instances _clockbuffertype (such as _BUFGP or _IBUFG) after
the output signal.
4. Maintain instantiation instance names of black boxes.
5. Maintain instantiation instance names of library primitives.
6. Name input and output buffers using the form _IBUF or _OBUF after the pad name.
7. Name Output instance names of IBUFs using the form instance_name_IBUF.
8. Name input instance names to OBUFs using the form instance_name_OBUF.
XST Name Generation Control

The following constraints control how names are written.
• Case (-case)
• Duplication Suffix (-duplication_suffix)
Define in ISE Design Suite in:
• Synthesis Properties, OR
• The command line

Chapter 20

This chapter discusses XST Command Line Mode, and includes:
• About XST Command Line Mode
• Launching XST in Command Line Mode Using the XST Shell
• Launching XST in Command Line Mode Using a Script File
• Running XST in Script Mode (VHDL)
• Running XST in Script Mode (Verilog)
• Running XST in Script Mode (Mixed Language)
• Setting Up an XST Script Using the Run Command
• Setting Up an XST Script Using the Set Command
• Setting Up an XST Script Using the Elaborate Command
• Synthesizing VHDL Designs Using Command Line Mode
• Synthesizing Verilog Designs Using Command Line Mode
• Synthesizing Mixed Designs Using Command Line Mode
About XST Command Line Mode

This section discusses About XST Command Line Mode, and includes:
• Running XST in Command Line Mode
• XST File Types in Command Line Mode
• Temporary Files in Command Line Mode
• Names With Spaces in Command Line Mode
Running XST in Command Line Mode

To run XST in command line mode:
• On a workstation, run xst
• On a PC, run xst.exe
XST File Types in Command Line Mode

XST generates the following files types in command line mode:
• Design output file, NGC (.ngc)
This file is generated in the current output directory (see the -ofn option).
• Register Transfer Level (RTL) netlist for RTL and Technology Viewers (.ngr)
• Synthesis log file (.srp)
• Temporary files

Chapter 20: XST Command Line Mode
Temporary Files in Command Line Mode

Temporary files are generated in the XST temp directory in command line mode. By
default, the XST temp directory is:
• Workstations
/tmp
• Windows
The directory specified by either the TEMP or TMP environment variable
Use set -tmpdir <directory> to change the XST temp directory.
VHDL or Verilog compilation files are generated in the temp directory. The default temp
directory is the xst subdirectory of the current directory.
Tip Xilinx® recommends that you clean the XST temp directory regularly. The temp
directory contains the files resulting from the compilation of all VHDL and Verilog files
during all XST sessions. Eventually, the number of files stored in the temp directory may
severely impact CPU performance. XST does not automatically clean the temp directory.
Names With Spaces in Command Line Mode

XST supports file and directory names with spaces in command line mode.
Enclose file or directory names containing spaces in double quotes:
"C:\my project"
Enclose multiple directories in braces:
-vlgincdir {"C:\my project" C:\temp}
Launching XST in Command Line Mode Using the XST Shell

Type xst to enter directly into an XST shell. Enter your commands and execute them.
To run synthesis, specify a complete command with all required options. XST does not
accept a mode where you can first enter set option_1, then set option_2, and then enter
run.
Since all options are set at the same time, Xilinx® recommends that you use a script file.
Launching XST in Command Line Mode Using a Script File

Store your commands in a separate script file and run them all at once. To execute your
script file, run the following workstation or PC command:
xst -ifn in_file_name -ofn out_file_name -intstyle {silent|ise|xflow}
The -ofn option is not mandatory. If you omit it, XST automatically generates a log file
with the file extension .srp, and all messages display on the screen. Use the following to
limit the number of messages printed to the screen:
• The -intstyle silent option
• The XIL_XST_HIDEMESSAGES environment variable
• The message filter feature in ISE® Design Suite
Reducing the Size of the XST Log File
For example, assume that the following text is contained in a file foo.scr:

run -ifn tt1.prj -top tt1 -ifmt MIXED -opt_mode SPEED -opt_level 1 -ofn tt1.ngc -p
<parttype>
This script file can be executed under XST using the following command:
xst -ifn foo.scr
You can also generate a log file with the following command:
xst -ifn foo.scr -ofn foo.log
A script file can be run either using xst -ifn script name, or executed under the XST
prompt, by using the script script_name command.
script foo.scr
If you make a mistake in an XST command option, or its value, XST issues an error
message and stops execution. For example, if in the previous script example VHDL is
incorrectly spelled (“VHDLL”), XST gives the following error message:
--> ERROR:Xst:1361 - Syntax error in command run for option
"-ifmt" : parameter "VHDLL" is not allowed.
If you created your project using ISE Design Suite, and have run XST at least once from
ISE Design Suite, you can switch to XST command line mode and use the script and
project files that were created by ISE Design Suite.
To run XST from the command line, run the following command from project directory:
xst -ifn <top_level_block>.xst -ofn <top_level_block>.syr
Setting Up an XST Script Using the Run Command

This section discusses Setting Up an XST Script Using the Run Command, and includes:
• About the Run Command
• Writing a Script File
• XST Specific Non-Timing Related Options
• Online Help
• Supported Families
• Commands for a Specific Device
• Run Command Options and Values (Virtex-5 Devices)
About the Run Command

The run command:
• Is the main synthesis command.
• Allows you to run synthesis in its entirety, beginning with the parsing of the
Hardware Description Language (HDL) files, and ending with the generation
of the final netlist.
• Can be used only once per script file.
• Begins with a keyword run, which is followed by a set of options and its values:
run option_1 value option_2 value ...
Note Xilinx does not support or recommend the use of multiple run commands in a
single script.

Writing a Script File

Observe the following rules when writing a script file:
• Place each option-value pair on a separate line.
• Use the pound (#) character to comment out options, or place additional comments
in the script file.
run
option_1 value
# option_2 value
option_3 value
• The first line contains only the run command without any options.
• There are no blank lines in the middle of the command.
• Each option name begins with dash. For example: -ifn, -ifmt, -ofn.
• Each option has one value. There are no options without a value.
• The value for a given option can be one of the following:
– Predefined by XST (for instance, yes or no)
– Any string (for instance, a file name or a name of the top level entity). Options
such as -vlgincdir accept several directories as values. Separate the directories
by spaces, and enclose them in braces ({}):
-vlgincdir {c:\vlg1 c:\vlg2}
For more information, see Names With Spaces in Command Line Mode.
– An integer
XST Specific Non-Timing Related Options

The following topics summarize XST specific non-timing related options, including
run command options and their values:
• XST Specific Non-Timing Options: XST Command Line Only
Online Help
XST provides online Help from the command line. The following information is
available by typing help at the command line. The XST help function provides a list of
supported families, available commands, options and their values for each supported
device family.
To see a detailed explanation of an XST command, use the following syntax.
help -arch family_name -command command_name
where:
• family_name is a list of supported Xilinx® families in the current version of XST
• command_name is one of the following XST commands:
– run
– set
– elaborate
– time

Supported Families
To see a list of supported families, type help at the command line prompt with no
argument. XST issues the following message.
--> help
ERROR:Xst:1356 - Help : Missing "-arch <family>".
Please specify what family you want to target
available families:
acr2
aspartan3
aspartan3a
aspartan3adsp
aspartan3e
avirtex4
fpgacore
qrvirtex4
qvirtex4
spartan3
spartan3a
spartan3adsp
spartan3e
virtex4
virtex5
xa9500xl
xbr
xc9500
xc9500xl
xpla3
Commands for a Specific Device

To see a list of commands for a specific device, type the following at the command
line prompt with no argument.
help -arch family_name
For example:
help -arch virtex
Run Command Options and Values (Virtex-5 Devices)

Use the following command to see a list of options and values for the run command for
Virtex®-5 devices.
--> help -arch virtex5 -command run

This command gives the following output:

-mult_style : Multiplier Style
block / lut / auto / pipe_lut
-bufg : Maximum Global Buffers
*
-bufgce : BUFGCE Extraction
YES / NO
-decoder_extract : Decoder Extraction
YES / NO
....
-ifn : *
-ifmt : Mixed / VHDL / Verilog
-ofn : *
-ofmt : NGC / NCD
-p : *
-ent : *
-top : *
-opt_mode : AREA / SPEED
-opt_level : 1 / 2
-keep_hierarchy : YES / NO
-vlgincdir : *
-verilog2001 : YES / NO
-vlgcase : Full / Parallel / Full-Parallel
....
Setting Up an XST Script Using the Set Command

XST recognizes the set command.
Set Command Options

Option Description Values
-tmpdir Location of all temporary files Any valid path to a directory
generated by XST during a session
-xsthdpdir Work Directory — location of all Any valid path to a directory
files resulting from VHDL or Verilog
compilation
-xsthdpini HDL Library Mapping File (.INI File) file_name
Setting Up an XST Script Using the Elaborate Command

Use the elaborate command to:
• Pre-compile VHDL and Verilog files in a specific library, or
• Verify Verilog files without synthesizing the design
Since compilation is included in the run, the elaborate command is optional.

Elaborate Command Options

Option Description Values
-ifn Project File file_name
-ifmt Format vhdl, verilog, mixed
-lso Library Search Order file_name.lso
-work_lib Work Library for Compilation — library name, work
where the top level block was compiled
-verilog2001 Verilog-2001 yes, no
-vlgpath Verilog Search Paths Any valid path to directories separated by spaces, and
enclosed in double quotes ("...")
-vlgincdir Verilog Include Directories Any valid path to directories separated by spaces, and
enclosed in braces ({...})
Running XST in Script Mode (VHDL)

To run XST in script mode in VHDL:
1. Open a new file named stopwatch.xst in the current directory.
2. Put the previously executed XST shell command into this file and save it.
run -ifn watchvhd.prj -ifmt mixed -top stopwatch -ofn watchvhd.ngc
-ofmt NGC -p xc5vfx30t-2-ff324 -opt_mode Speed -opt_level 1
3. From the tcsh or other shell, enter the following command to begin synthesis:
xst -ifn stopwatch.xst
Files Created During Run (VHDL)

During this run, XST creates the following files.
• watchvhd.ngc
An NGC file ready for the implementation tools
• xst.srp
The XST log file
Saving XST Messages in a Different Log File (VHDL)

To save XST messages in a different log file, run the following command:
xst -ifn stopwatch.xst -ofn <filename>.log
Following is an example using watchvhd.log:
xst -ifn stopwatch.xst -ofn watchvhd.log

For this example, stopwatch.xst appears as follows:

run
-ifn watchvhd.prj
-ifmt mixed
-top stopwatch
-ofn watchvhd.ngc
-ofmt NGC
-p xc5vfx30t-2-ff324
-opt_mode Speed
-opt_level 1
Improving Readability (VHDL)

Observe the following rules to improve the readability of the stopwatch.xst file,
especially if you use many options to run synthesis:
• Each option with its value is on a separate line.
• Each line except the first begins with a dash.
Leading Spaces (VHDL)

An error occurs if a leading space is entered in the value field.
ISE® Design Suite automatically strips leading spaces from a process value. Accordingly,
the .xst file written by ISE Design Suite is not affected by leading spaces.
If you hand-edit the .xst file and run XST from the command line, manually delete
any leading spaces.

Running XST in Script Mode (Verilog)

This section discusses Running XST in Script Mode (Verilog), and includes:
• How to Run XST in Script Mode (Verilog)
• Files Created During Run (Verilog)
• Saving XST Messages in a Different Log File (Verilog)
• Improving Readability (Verilog)
How to Run XST in Script Mode (Verilog)

To run XST in script mode:
1. Open a new file called design.xst in the current directory. Put the previously
executed XST shell command into this file and save it.
run
-ifn watchver.prj
-ifmt mixed
-ofn watchver.ngc
-ofmt NGC
-opt_mode Speed
-opt_level 1
2. From the tcsh or other shell, enter the following command to begin synthesis.
xst -ifn design.xst
For the previous command example, the design.xst file should look like the following:
run
-ifn watchver.prj
-ifmt mixed
-top stopwatch
-ofn watchver.ngc
-ofmt NGC
-opt_mode Speed
-opt_level 1
Files Created During Run (Verilog)

During this run, XST creates the following files.
• watchvhd.ngc
• design.srp
The XST script log file
Saving XST Messages in a Different Log File (Verilog)

To save XST messages in a different log file (for example, watchver.log), run:
xst -ifn design.xst -ofn watchver.log

Improving Readability (Verilog)

To improve the readability of the design.xst file, especially if you use many options
to run synthesis, place each option with its value on a separate line. Observe the
following rules:
• Each line (except the first one) begins with a dash (-).

Running XST in Script Mode (Mixed Language)

This section discusses Running XST in Script Mode (Mixed Language), and includes:
• How to Run XST in Script Mode (Mixed Language)
• Files Created During Run
• Saving XST Messages in a Different Log File (Mixed Language)
• Improving Readability (Mixed Language)
How to Run XST in Script Mode (Mixed Language)

To run XST in script mode:
1. Open a new file called stopwatch.xst in the current directory. Put the previously
executed XST shell command into this file and save it.
run
-ifn watchver.prj
-ifmt mixed
-top stopwatch
-ofn watchver.ngc
-ofmt NGC
-ofn watchver.ngc
-ofmt NGC
-opt_mode Speed
-opt_level 1
2. From the tcsh or other shell, enter the following command to begin synthesis.
xst -ifn stopwatch.xst
For the previous command example, the stopwatch.xst file should look like:
run
-ifn watchver.prj
-ifmt mixed
-ofn watchver.ngc
-ofmt NGC
-opt_mode Speed
-opt_level 1
Files Created During Run (Mixed Language)

During this run, XST creates the following files:
• watchver.ngc
• xst.srp
The XST script log file

Saving XST Messages in a Different Log File (Mixed Language)

To save XST messages to a different log file (for example, watchver.log) run:
xst -ifn stopwatch.xst -ofn <filename>.log
Following is an example using watchver.log:
xst -ifn stopwatch.xst -ofn watchver.log
Improving Readability (Mixed Language)

To improve the readability of the stopwatch.xst file, especially if you use many
options to run synthesis, place each option with its value on a separate line. Observe
the following rules:
• Each line (except the first one) begins with a dash.
Synthesizing VHDL Designs Using Command Line Mode

This section discusses Synthesizing VHDL Designs Using Command Line Mode, and
includes:
• VHDL Design Files and Entities
• Example Using Command Line Mode
• Synthesizing the Design
• Library Names
• XST File Order Warning
The following coding example shows how to synthesize a hierarchical VHDL design for
a Virtex® device using command line mode.
VHDL Design Files and Entities

The example uses a VHDL design called watchvhd. The files for watchvhd are
located in the ISEexamples\watchvhd directory of the ISE® Design Suite installation
directory.
This design contains seven entities:
• stopwatch
• statmach
• tenths (a CORE Generator™ software core)
• decode
• smallcntr
• cnt60
• hex2led

Example Using Command Line Mode

Following is an example of how to synthesize a VHDL design using command line mode.
1. Create a new directory named vhdl_m.
2. Copy the following files from the ISEexamples\watchvhd directory of the ISE
Design Suite installation directory to the newly created vhdl_m directory.
• stopwatch.vhd
• statmach.vhd
• decode.vhd
• cnt60.vhd
• smallcntr.vhd
• tenths.vhd
• hex2led.vhd
3. To synthesize the design, which is now represented by seven VHDL files, create
a project.
Synthesizing the Design

XST supports mixed VHDL and Verilog projects. Xilinx® recommends that you use the
new project format, whether or not it is a real mixed language project. This example uses
the new project format. To create a project file containing only VHDL files, place a list of
VHDL files preceded by keyword VHDL in a separate file. The order of the files is not
important. XST can recognize the hierarchy, and compile VHDL files in the correct order.
For the example, perform the following steps:
1. Open a new file called watchvhd.prj
2. Enter the names of the VHDL files in any order into this file and save the file:
vhdl work statmach.vhd
vhdl work decode.vhd
vhdl work stopwatch.vhd
vhdl work cnt60.vhd
vhdl work smallcntr.vhd
vhdl work tenths.vhd
vhdl work hex2led.vhd
3. To synthesize the design, execute the following command from the XST shell or
the script file:
run -ifn watchvhd.prj -ifmt mixed -top stopwatch -ofn
watchvhd.ngc -ofmt NGC -p xc5vfx30t-2-ff324 -opt_mode Speed
-opt_level 1
You must specify a top-level design block with the -top command line option.
To synthesize just hex2led and check its performance independently of the other blocks,
you can specify the top-level entity to synthesize on the command line, using the -top
option.
run -ifn watchvhd.prj -ifmt mixed -ofn watchvhd.ngc -ofmt NGC -p
xc5vfx30t-2-ff324 -opt_mode Speed -opt_level 1 -top hex2led

Library Names
During VHDL compilation, XST uses the library work as the default. If some VHDL files
are to be compiled to different libraries, add the library name before the file name. For
example, to compile hexl2led into the library my_lib, write the project file as follows:
vhdl work statmach.vhd vhdl work decode.vhd vhdl work
stopwatch.vhd vhdl work cnt60.vhd vhdl work smallcntr.vhd vhdl
work tenths.vhd vhdl my_lib hex2led.vhd
XST File Order Warning

If XST does not recognize the file order, it issues the following warning:
WARNING:XST:3204. The sort of the vhdl files failed, they will
be compiled in the order of the project file.
In this case, you must:
• Put all VHDL files in the correct order.
• Add the -hdl_compilation_order option with value user to the XST run command:
run -ifn watchvhd.prj -ifmt mixed -top stopwatch -ofn
watchvhd.ngc -ofmt NGC -p xc5vfx30t-2-ff324 -opt_mode Speed
-opt_level 1 -top hex2led -hdl_compilation_order user
Synthesizing Verilog Designs Using Command Line Mode

This section discusses Synthesizing Verilog Designs Using Command Line Mode, and
includes:
• Verilog Design Files and Modules
• Synthesizing HEX2LED
The following coding example shows the synthesis of a hierarchical Verilog design for a
Virtex® device using command line mode.
Verilog Design Files and Modules

The example uses a Verilog design called watchver. These files are found in the following
directory of the ISE® Design Suite installation directory:
ISEexamples\watchver
The files are:
• stopwatch.v
• statmach.v
• decode.v
• cnt60.v
• smallcntr.v
• tenths.v
• hex2led.v

This design contains seven modules:

• stopwatch
• statmach
• tenths (a CORE Generator™ software core)
• decode
• cnt60
• smallcntr
• hex2led

1. Create a new directory named vlg_m.
2. Copy the watchver design files from the ISEexamples\watchver directory of
the ISE Design Suite installation directory to the newly created vlg_m directory.
Specify the top-level design block with the -top command line option.

To synthesize the design, which is now represented by seven Verilog files, create a
project. XST now supports mixed VHDL and Verilog projects. Therefore, Xilinx®
recommends that you use the new project format whether it is a real mixed language
project or not. In this example, we use the new project format. To create a project file
containing only Verilog files, place a list of Verilog files preceded by the keyword verilog
in a separate file. The order of the files is not important. XST can recognize the hierarchy
and compile Verilog files in the correct order.
1. Open a new file, called watchver.v.
2. Enter the names of the Verilog files into this file in any order and save it:
verilog work decode.v
verilog work statmach.v
verilog work stopwatch.v
verilog work cnt60.v
verilog work smallcntr.v
verilog work hex2led.v
3. To synthesize the design, execute the following command from the XST shell or a
script file:
run -ifn watchver.v -ifmt mixed -top stopwatch -ofn
watchver.ngc -ofmt NGC -p xc5vfx30t-2-ff324 -opt_mode Speed
-opt_level 1
Synthesizing HEX2LED
To synthesize just HEX2LED and check its performance independently of the other
blocks, specify the top-level module to synthesize in the command line, using the -top
option.
run -ifn watchver.v -ifmt Verilog -ofn watchver.ngc -ofmt NGC -p
xc5vfx30t-2-ff324 -opt_mode Speed -opt_level 1 -top HEX2LED

Synthesizing Mixed Designs Using Command Line Mode

This section discusses Synthesizing Mixed Designs Using Command Line Mode, and
includes:
• File Order
This example shows the synthesis of a hierarchical mixed VHDL and Verilog design for
a Virtex® device using command line mode.

1. Create a new directory named vhdl_verilog.
2. Copy the following files from the ISEexamples\watchvhd directory of the ISE®
Design Suite installation directory to the newly-created vhdl_verilog directory.
• stopwatch.vhd
• statmach.vhd
• decode.vhd
• cnt60.vhd
• smallcntr.vhd
• tenths.vhd
3. Copy the hex2led.v file from the ISEexamples\watchver directory of the ISE
Design Suite installation directory to the newly created vhdl_verilog directory.
[

The design is now represented by six VHDL files and one Verilog file. To synthesize
the design, create a project. To create a project file, place a list of VHDL files preceded
by keyword vhdl, and a list of Verilog files preceded by keyword verilog in a
separate file.
File Order
The order of the files is not important. XST recognizes the hierarchy and compiles
Hardware Description Language (HDL) files in the correct order.


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XST User Guide for Virtex-4,

Virtex-5, Spartan-3, and Newer

UG627 (v 14.5) March 20, 2013

Chapter 2 Introduction to Xilinx Synthesis Technology (XST)...............................13

Chapter 3 XST HDL Coding Techniques ..................................................................15

Frontmatter Send Feedback

Chapter 5 XST CPLD Optimization .........................................................................253

Chapter 6 XST Design Constraints .........................................................................261

Chapter 7 XST General Constraints .......................................................................285

Send Feedback Frontmatter

Chapter 8 XST HDL Constraints .............................................................................315

Frontmatter Send Feedback

Send Feedback Frontmatter

Chapter 10 XST CPLD Constraints (Non-Timing)..................................................391

Chapter 11 XST Timing Constraints .......................................................................397

Chapter 12 XST Implementation Constraints ........................................................409

Chapter 13 XST Supported Third Party Constraints .............................................413

Frontmatter Send Feedback

Chapter 14 XST VHDL Language Support .............................................................417

Chapter 15 XST Verilog Language Support ...........................................................463

Chapter 16 XST Behavioral Verilog Language Support........................................483

Send Feedback Frontmatter

Chapter 17 XST Mixed Language Support.............................................................515

Chapter 18 XST Log File ..........................................................................................523

Chapter 19 XST Naming Conventions ....................................................................551

Chapter 20 XST Command Line Mode ...................................................................553

Frontmatter Send Feedback

Send Feedback Frontmatter

About This Guide

Frontmatter Send Feedback

Send Feedback Frontmatter

Introduction to Xilinx Synthesis

Setting XST Options

Frontmatter Send Feedback

For more information, see:

Send Feedback Frontmatter

XST HDL Coding Techniques

Frontmatter Send Feedback

Signed and Unsigned Support in XST

Send Feedback Frontmatter

Registers HDL Coding Techniques

Registers Log File

Registers Log File Example

Synthesizing Unit <registers_5>.

Frontmatter Send Feedback

Registers Related Constraints

Registers Coding Examples

Flip-Flop With Positive-Edge Clock Diagram

Flip-Flop With Positive-Edge Clock Pin Descriptions

Flip-Flop With Positive Edge Clock VHDL Coding Example

architecture archi of registers_1 is

Send Feedback Frontmatter

When using VHDL for a positive-edge clock, instead of using:

module v_registers_1 (C, D, Q);

reg qtemp = ’b1 ;

Frontmatter Send Feedback

architecture archi of registers_1 is

Flip-Flop With Negative-Edge Clock and Asynchronous Reset

Flip-Flop With Negative-Edge Clock and Asynchronous Reset

Send Feedback Frontmatter

Flip-Flop With Negative-Edge Clock and Asynchronous Reset VHDL

architecture archi of registers_2 is

process (C, CLR)