Digital Arithmetic Using Analog Arrays
Saeid Sadeghi-Emamchaie, G.A. Jullien, V. Dimitrov and W.C. Miller
VLSI Research Group, University of Windsor, Ontario, Canada N9B 3P4
Abstract
This paper describes techniques for using locally con-
nected analog Cellular Neural Networks (CNNs) to imple-
ment digital arithmetic arrays; the arithmetic is
implemented using a recently disclosed Double-Base Num-
ber System (DBNS). The CNN arrays are targeted for low
power low-noise DSP applications where lower slew rate
during transitions is a potential advantage. Specifically,
we demonstrate that a CNN array, using a simple nonlin-
ear feedback template, with hysteresis, can perform arbi-
trary length arithmetic with good performance in terms of
stability and robustness. The principles presented in this
paper can also be used to implement arithmetic in other
number systems such as the binary number system.
1. Introduction
A Cellular Neural Network (CNN) is a large scale
array of locally connected non-linear analog cells [1]-[2].
Since their initial disclosure in 1988, numerous applica-
tions of CNNs have been proposed. In this paper we use
CNNs to implement large arithmetic arrays where continu-
ous speed/power trade-offs and lower slew rates (lower
noise) are advantageous. Due to their local connectivity
the VLSI implementation of such networks is quite prom-
ising [3]-[4].
CNNs are introduced in section 2. In section 3 we
first briefly introduce DBNS addition and explain the con-
ditions required to guarantee carry-free addition by the
application of two simple reduction rules. In section 4 we
propose methods for designing CNN arrays to implement
DBNS addition. We describe the sets of simple conditions
that must be met in order to force transition of the state
voltage of the cells by switching sourcing or sinking cur-
rents in the cell. These conditions ensure stability and syn-
chronous transitions of the output voltages of the cells
during the application of reduction rules and also prevent
participation of a cell in more than one reduction at the
same time. In section 5 we discuss implementation proce-
dures and present basic CMOS circuits of the DBNS cell.
In section 6 we provide an illustrative example of DBNS
reduction to guarantee carry-free addition.
2. Cellular Neural Networks
Our definition of CNNs is based on the most general
case presented in [5]. Here we recall only the main results
related to our application. The cell located at ( i, j ) in a
M × N array is denoted by C ij and its r -neighborhood N ij
is defined by:
N ij = C kl max { k – i , l – j } ≤ r; 1 ≤ k ≤ M , 1 ≤ l ≤ N (1)
where r is a positive integer. The state of the cell C ij at
time t is denoted by x ij ( t ) (with initial condition
x ij ( 0 ) ≤ 1 ) and the output by y ij ( t ) . The state equation of a
cell C ij ( 1 ≤ i ≤ M , 1 ≤ j ≤ N ) is shown in eqn. (2), where,
for convenience and without loss of generality, we assume
that R = C = 1 :
ẋ ij ( t ) = –x ij ( t ) +∑ A i, j, k, l ( x k, l ( t ), y k, l ( t ) ) (2)
C kl ∈ N ij
The { A i, j, k, l } are nonlinear functions of the state
x i + k, j + l and output y i + k, j + l voltages of the cells in N ij ,
including the cell itself.
The output equation is given by eqn. (3):
1
y ij ( t ) = f ( x ij ( t ) ) = --- ( x ij ( t ) + 1 – x ij ( t ) – 1 ) (3)
2
Note that y ij ( t ) ≤ 1 for all t ≥ 0 . The functions { A i, j, k, l }
are assumed to be space invariant, so that
A i, j, k, l = A k – i, l – j . For a r -neighborhood, the values of
A k – i, l – j are usually shown as a ( 2r + 1 ) × ( 2r + 1 ) matrix
known as feedback template, A. (we are using a modified
definition for the feedback template).
The input signal is loaded as the initial state voltages of the
cells x ij ( 0 ) and after transient time the result (output sig-
nal) is available from the output state variables y ij ( ∞ ).
3. Double-Based Number System (DBNS)
The double base number representation has the form
of eqn. (4), where the digits d i, j ∈ ( 0, 1 ) .
j j+1 j j+1
2 2 2 2
∑ d i, j 2 3
i j
x = (4)
i, j

Clearly the binary number system is a special case of the i i

3 3
above representation. The DBNS has an unusually simple
i+1 i+1
2-D geometric interpretation, suitable for implementation 3 3
via CNNs. Representation of numbers using the minimal
number of ones is called canonic or minimal form. Corre-
sponding to a DBNS number, an image or map can be con- Fig. 2 Reduction Rule 1
sidered. Fig. 1 represents two numbers, 79 and 110, in
DBNS image or map form. The cells with d i, j = 1 are Reduction rule 2:
black; these are known as active cells. In cases that the position (i + 1, j) is occupied, we
apply rule 2 (see eqn. (8) and Fig. 3).
i j i j+1 i+1 j i+1 j+1
1 2 4 8 1 2 4 8 32 +32 +3 2 = 3 2 (8)
1 1
j j+1 j j+1
2 2 2 2
3 3
9 9
i i
27 27 3 3
i+1 i+1
79 110 3 3
Fig. 1 Number representation in the DBNS map

3.1 Addition and multiplication Fig. 3 Reduction rule 2.

It is clear that the multiplication process simply cor-

Let Ix (i,j) and Iy(i,j) be the DBNS -maps of the inte-
gers x and y, represented in the canonic form. The image
Iz(i,j) of the DBNS -map of the number z = x + y can be
obtained by the following two steps:
I z ( i, j + 1 ) = I x ( i, j ) ∧ I y ( i, j )
(5)
I z ( i, j ) = I x ( ( i, j ) ⊕ I y ( i, j ) )
where ∧ and ⊕ represent the logic OR and XOR func-
tions respectively. Note, in the canonic presentation:
if I x ( i, j ) = 1 then I x ( i, j + 1 ) = 0 (6)
and therefore carry-free addition can be accomplished. The
resulting image, Iz, however is not in canonic form and can
not be used in carry-free addition since it might have adja-
cent active cells in a row (violation of the condition
defined in eqn. (6)). To satisfy this condition the following
two reduction rules should be applied to Iz [7].
Reduction rule 1:
Using the simple identity:
i j i j+1 i+1 j
32 +32 = 3 2 (7)
the two adjacent active cells at position (i, j) and
(i, j + 1) can be replaced by a cell at (i + 1, j) (see Fig. 2).
responds to 2D shifts and DBNS additions, in an equiva-
lent way to that performed using binary arithmetic. The
promise here, however, is that the number of operations is
considerably reduced based on the sparseness of the repre-
sentation. Obviously as a result of the application of rules
1 and 2, to a number I z , new adjacent active cells in a row
might be created (corresponding to ‘carry propagation’ in
binary addition), which requires these two rules to be
applied successively until there are no adjacent active cells
in a row. In [7] it is shown that in worst case after
n
---------- ≈ 0.630925n time, the resulting map will have no adja-
lg 2 3
cent active cells.
4. DBNS arithmetic using CNNs
The addition defined in eqn. (5) can be easily imple-
mented using a CNN to perform simple local Boolean
operations. The application of the reduction rules is some-
what more complicated, and so we concentrate on their
implementation in the remainder of the paper. We consider
a N × M CNN corresponding to the N × M image I z
resulting from completion of step a and b. We set the ini-
tial values of the state voltages of the cells of our CNN to
the values of the corresponding cells in I z (‘-1’ and ‘1’
corresponding to ‘0’ and ‘1’ in I z ).
For convenience we refer to the cells (positions)
involved in reduction rule ‘1’ with A,B and C (Fig. 4 a)
and the cells (positions) participating in reduction rule 2
one set of two sets of conditions A C and A G (correspond-
ing to the positions C in reduction rule 1 and G in reduc-
tion rule 2) must be met. Each of these sets of conditions
consists of two groups of conditions.
Group 1 conditions
Considering a cell at an

...
with D,E,F and G (Fig. 4 b). j
arbitrary position (i, j)
i with three of its neighbors
...

...
... ... at positions (i, j – 1) ,
A B D E (i + 1, j – 1) and (i + 1, j) in
.. ... ... ... our CNN (Fig. 6)
δ C ϕ λ F G

...
We define the following
functions:
...
...

Fig. 6 Cell at position (i, j)

a) b) and its three neighbors
Fig. 4 Reduction rule 1 a) and reduction rule 2 b)

The state voltage of the cells at positions δ , ϕ and λ H i, j ;w = f ( y i, j – y i, j – 1 ) (9)

as we will see later, will be used to define conditions
H i, j ;sw = f ( y i, j – y i + 1, j – 1 ) (10)
required for the proper applications of rules ‘1’ and ‘2’.
During the application of these two rules the output H i, j ;s = f ( y i, j + y i + 1, j ) (11)
voltage of the cells with initial value of ‘1’ (A,B,D,E and
F) continuously fall from ‘+1’ to ‘-1’ and at the same time
the output voltage of the cells with initial value of ‘-1’ (C The function f ( u )
f (u)
and G) rise from ‘-1’ to ‘+1’. represents has the hys-
teresis characteristic 1
Circuit diagram of a cell:
shown in Fig. 7.
Fig. 5 shows the simplified circuit diagram of a cell
C i, j :
Referring to Fig. 4
x ij I snk y ij a), for the application of u
R reduction rule 1, the fol-
I src lowing conditions are 0.1 0.3
C I sf necessary: Fig. 7 Hysteresis charac-
A A, A B, A D , A E , A F teristic of f ( u )
AC , AG

Fig. 5 Simplified Circuit Diagram of a cell

H B, w = f ( y B – y A ) = 1 (12)
I sf = k x ij is the self-feedback current. To have
H A, s = f ( y A + y C ) = 1 (13)
binary outputs ( ± 1 ), k > 1 [1]. During transitions, we set k
to a larger value than its value at the saturation voltages Referring to Fig. 4 b), for application of reduction
( ± 1 ); this allows fast transitions [9]. The current sources rule 2 the following conditions are necessary:
I snk = – k ( 1 + x ij ) and I src = k ( 1 – x ij ) are used to force H E, w = f ( y E – y D ) = 1 (14)
the state voltage of the cell to change; normally these two H E, sw = f ( y E – y F ) = 1 (15)
current sources are switched off. For I snk to be switched
H E, s = f ( y E + y G ) = 1 (16)
on, at least oneof five sets of conditions
A A, , A B ,, A D ,, A E , and A F , (corresponding to the positions These hysteresis functions provide a simple tools to
locate the patterns of cells which have necessary condi-
A and B in reduction rule 1 and D, E, and F in reduction
tions to participate in reductions, to ensure stability of the
rule 2) must be satisfied. For I src to be switched on, at least
cell during switching of I snk , I src and also to guarantee
synchronous transitions of the state voltages of the cells Case 3c
during the application of reduction rules 1 and 2. An active cell can par- j

...
Group 2 conditions ticipate at position A (Fig.
4 a)) in reduction rule 1 and i
Considering the map of a DBNS number, each square
position E (Fig. 4 b)) in
(cell) has a specific value, and participation of any active ... ...
reduction rule 2 at the same
cell in more than one reduction at the same time leads to
time. (see Fig. 12).
incorrect results. Therefore in cases where two or more
reduction patterns have a cell in common, only one of

...
them is allowed. This requirement is forced using group 2
conditions. Participation of an active cell in more than one Fig. 12 Case 3c
reduction can occur in the following cases:
Case 1 As we see, choosing one reduction set over the other
The active cell at leads to different but equivalent representations of the
j
DBNS number (nonuniqueness property of the DBNS [7]).
...
position ( i, j ) can partici-
pate in two applications of However, in a CNN implementation of these five cases, we
i
reduction rule 1, in the left must select the appropriate design in terms of complexity
and speed of operation. In our design, minimum hardware
set shown by the broken ... ...
line or in the right set complexity and higher speed are achieved by selecting the
shown by the solid line. set shown by the solid line in each case using the group 2
conditions. By checking the output voltage of the cells at
Case 2 positions δ , ϕ and λ (Fig. 4 a) and b)) and comparing
...

Fig. 8 Case 1 them with threshold values we select the sets shown by the
The active cell at j solid lines over the sets shown by the broken lines (see Fig.
...

position ( i, j ) can partici-
pate in two applications of
reduction rule 2, in the
upper set shown by the
broken line or in the lower
set shown by the solid line.
8-12). The group 2 conditions comprise the following:
y ϕ ≥ 0.9, y δ ≥ 0.9, y λ < 0.7 (17)
i ... ... Now we define conditions required for switching Isnk
(Isrc) on. The following five sets ( A A , A B , A D , A E , A F )
of conditions are required to be satisfied for Isnk to be
...

Case 3a switched on. Each of these sets of conditions corresponds

Fig. 9 Case 2 to the position of one of the cells ( A , B , D , E , or F ) with
An active cell can j falling state voltage during the application of rule 1 or 2
participate at position B
...

(see Fig. 4 a) and b)).

(Fig. 4 a)) in reduction
rule 1 and position F (Fig. Reduction rule 1
4 b)) in reduction rule 2 at i ... ... H i, j + 1 ;w = H i, j ;s = 1
the same time. (see Fig.
A A: & (18)
10)
y i + 1, j + 1 ≥ 0.9
...

Case 3b
Fig. 10 Case 3a H i, j ;w = H i, j – 1 ;s = 1
An active cell can j AB : & (19)
...

participate at position B y i + 1, j – 2 ≥ 0.9

(Fig. 4 a)) in reduction i
rule 1 and position D (Fig. Reduction rule 2
4 b)) in reduction rule 2 at ... ...
H i, j + 1 ;w = H i, j + 1 ;sw = H i, j + 1 ;s = 1
the same time. (see Fig.
11) AD : & (20)
y i + 1, j – 1 < – 0.7
...

Fig. 11 Case 3b
 H i, j ;w = H i, j ;sw = H i, j ;s = 1
AE : & (21) VDD
y i + 1, j – 2 < – 0.7
Vb2
M5
M8
A F : H i – 1, j + 1 ;w = H i – 1, j + 1 ;sw = H i – 1, j + 1 ;s = 1 (22) Vb1

and a set of conditions required for Isrc to be switched on: M1 M2

M7
M6
Vr
Reduction Rule 1
M9 M3 M4
H i – 1, j + 1 ;w = H i – 1, j ;s = 1
AC : & (23) Vb3
Vr

y i, j + 1 ≥ 0.9
M1 2 M13
Reduction Rule 2
_ _ __
M10 M11
Vs r c Vsr c
H i – 1, j ;w = H i – 1, j ;sw = H i – 1, j ;s = 1
AG : & (24)
y i, j – 2 < – 0.7 VDD

M15
As we see, the dynamic of a cell is determined by its inter-
action with the other cells in the 5 × 5 neighborhood. M1 4 M1 6
Vb4

5. Implementing the cell

M1 7 M19 _ __ _
Vs nk Vs nk

I snk and I src have values – k × ( 1 + x ij ) and M18 Vb5

k × ( 1 – x ij ) respectively. These can be decomposed into

two parts: – k – k x ij and k – k x ij . The first part is a con-
stant current source and the second part is the negative of
the self-feedback current. Since at most one of the two
sourcing or sinking currents are active, the circuit diagram
of any given cell in our CNN during the activity of I snk or
I src can be simplified as shown in Fig. 13.
Fig. 14 shows the CMOS circuit used for SPICE sim-
ulations of the basic adder cell. A differential pair consist-
ing of transistors M1-M4 is used to realize the nonlinear
output characteristic (eqn. (3)). The cell resistor is built
with an NMOS and PMOS transistor in parallel (M6 and
M7). M8 and M9 (diode connected) are used to realize the
nonlinear behavior of I sf . These two transistors are off
during the transition of the output (state) voltage from ± 1
to −+ 1 .
x ij
R
±k
C and C=0.4pF to provide a time-constant of 13nS for each
Fig. 13 Cell during application of Rule1 or Rule2
Fig. 14 CMOS circuit of a cell
As soon as the state voltage passes the output saturat-
ing voltages ( ± 1 ), M8 or M9 turns on and forces the state
voltage to be close to the output voltage. I src ( I snk ) is pro-
vided by the sub-circuit consisting of M14, M15 and M16
(M17, M18 and M19) which is controlled by V src ( V snk ).
The self-feedback current source is applied to the state
capacitor through M13 and M14. As soon as the conditions
of one of the elements of the feedback template are met
V src = 1 ( V snk = 1 ), the self-feedback path is opened by
turning M13 (M14) off, the output of the differential pair is
loaded with a temporary load M10 (M11) in order to main-
tain the proper function of the differential pair in providing
the nonlinear characteristic, and finally I src ( I snk ) is
applied to the state capacitor.
y ij
6. Simulation results:
In this example simulation, we have used R=32.5KΩ
cell. We tested our method on a non-canonic representa-
tion of the number 54 represented in a 4 × 3 map. Fig. 15
shows the initial values (left) and final values of the state sourcing or sinking currents in the cells. These conditions
voltages, which is correct. The simulations were per- ensure stability and synchronous transitions of the output
formed using HSPICE. Fig. 16 shows the state voltages of voltages of the cells during swithching of the current
the cells during processing. sources. These conditions also serve as simple tool to guar-
antee proper application of reduction rules which are nec-
essary for carry-free addition
1 2 4 8 1 2 4 8
The implementation provides us with a continuous
1 1 speed/power trade-off mechanism, and reduced system
3 3 noise compared to switching logic gates. The technique
appears promising for low bandwidth networks where both
9 9 power and low supply voltages are a major concern.
27 27
8. Acknowledgments
54 54
Fig. 15 Initial and final values of the state voltages
The authors wish to acknowledge financial support
from the Natural Sciences and Engineering Research
1 Council of Canada, and the Micronet Network of Centres
s11 s12 s13 of Excellence. Simulation tools, design workstations and
access to the MOSIS technology have been provided by
0 the Canadian Microelectronics Corporation.

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Arithmetic Arrays using Cellular Neural Network” Proceed-
In this paper, we have introduced the concepts behind ings of 31th Asilomar conference on Signals, Systems and
a novel CNN-based processor for implementing digital Computer, Asilomar, California Nov. 1997
arithmetic arrays in a Double-Base number system. We
have presented sets of simple conditions that are required
to force the transition of the state voltage by switching