SESHADRIRAOGUDLAVALLERU ENGINEERING COLLEGE

(An Autonomous Institute with Permanent Affiliation to JNTUK, Kakinada)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
M.TECH – II SEMESTER – I MID EXAMINATIONS, JUNE -2023.
SoC Design(EC3919)
(VLSI Design and Embedded Systems)
Time: 90min. Max.Marks: 30
Date: 21-6-2023.
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1. a) With the help of architecture design explain the concept of core libraries. (6M)
b) What do you understand by Cosyma co design flow in SoC design? (4M)

2. a) Briefly explain about interlaced co development design methodology of

logic cores with neat diagram. (5M )
b) Explain about deliverable and system integration of soft and firm cores. (5M)

3. a) What are the different guidelines to be considerable for design reuse? (6M)
b) Explain the Hardware Software co-design in architecture design. (4M)

GUDLAVALLERU ENGINEERING COLLEGE

 (An Autonomous Institute with Permanent Affiliation to JNTUK, Kakinada)
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
M.TECH. – II SEMESTER – I MID EXAMINATIONS, October -2020
SoC Design
(Embedded Systems)
Time: 2 Hours Max.Marks: 40
Date: 9-10-2020.
____________________________________________________________________________________

1. a)Explain the various design issues of SoC (6M)

b) What are the different cores used for SoC design? (4M)

2. What is design reuse and discuss the various guidelines for design reuse. (10M)

3. a)Explain the system integration of soft and firm cores.(5M)

b) What are the different guidelines to be considerable for design reuse?(5M)

4. a) Define compiler and explain about memory compiler. (5M)

b) Explain the basic structure of SRAM and DRAM cells(5M).