Name: ID No. Roll No.

Birla Institute of Technology and Science – Pilani, Hyderabad Campus. Second Semester 2021-22
CS/ECE/EEE/INSTR F241: Microprocessors and Interfacing, Comprehensive Examination (Closed Book)
Time: 9:00AM-12:00PM Date: 6th May 2022 Total marks: 120
Instructions:
1. Write your Name, ID No. and Roll No. in the space provided on top of every sheet.
SET B
2. Write your answers in the space provided for each question ONLY.
3. This paper contains 2 sections, each carrying 60 marks. Unanswered questions will be awarded 0 marks. Section-wise
instructions have been provided, where necessary.
4. Any missing data may be assumed, in which case the assumption and the corresponding justification needs to be written
explicitly next in the space near the question.

SECTION I

1. [15M] Consider the scenario where four stepper motors drive the wheels of a Mars Rover. Assume that each
wheel has a radius of 5⁄𝜋 meters and all the stepper motors have a 1.8 degrees stepping angle when used in
full-step model of operation. Since all wheels are to move synchronously, all four stepper motors receive the
same excitation sequence from Port A of 8255. All unused ports are declared to be output ports and 8255 is
to be used in Mode 0. Consider the following code executed by 8086 to carry out the above task. Answer
the following questions in the given box ONLY. Note that the circumference of a circle having radius 𝑟 is
𝐶 = 2 𝜋 𝑟. Assume that a sub-routine named “DELAY” is available to generate the required delay.
a. [3M] What should be the value of “CW” (in
.MODEL SMALL
.DATA Hexadecimal number system) given in the code
FORWARD DB ? for intended operation of the system, as
BACKWARD DB ? described?
.CODE
.STARTUP
CW =
CR EQU 0C6H ; Port address of Control Register
PA EQU 0C0H ; Port address of Port A b. [4M] Suppose 𝑁1 = 5 and 𝑁2 = 4 in the given
MOV AL, CW code. What is the value of 𝑁 (in decimal number
OUT CR, AL system) such that the Mars Rover traverses a
MOV CX, 𝑵 ; 𝑵 is immediate data distance of 30 meters in the forward direction
MOV FORWARD, 𝑵𝟏 ; 𝑵𝟏 is immediate data
before halting?
MOV BACKWARD, 𝑵𝟐 ; 𝑵𝟐 is immediate data
MOV AL, 88H .𝑁 =
AGAIN:
MOV BL, FORWARD c. [3M] For the Mars Rover to traverse in the
UP1: backward direction, how should 𝑁1 and 𝑁2 be
ROR AL, 1 related to each other? Provide the inequality.
OUT PA, AL
CALL DELAY
DEC BL
JNZ UP1
d. [5M] For the Mars Rover to traverse a distance of
MOV BL, BACKWARD
UP2: 30 meters in the backward direction before
ROL AL, 1 coming to a halt, what equation (in terms of 𝑁1
OUT PA, AL and 𝑁2 ) should be satisfied? Given 𝑁 = 200.
CALL DELAY
DEC BL
JNZ UP2
LOOP AGAIN
.EXIT
END
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 2. [15M] For the following code, assume the initial values: CS = 0000H, IP = 0000H, DS = 0000H.
Answer the following questions in the provided box ONLY. Note: The machine opcode for
unconditional branch instruction “JMP” is E9H. Note that, when used as an instruction, JMP 𝑥, the 𝑥
refers to displacement.
.MODEL SMALL
.DATA
a. [5M] The instruction MUL AX is executed
ORG 000EH
N DB E9H number of times.
N1 DW 3 b. [5M] The final value in the register AX (as a Hexadecimal
.CODE
MOV AX, CS ; 2 byte
MOV DS, AX ; 2 byte value) is .
MOV AX, 0001H ; 4 bytes
MOV BX, OFFSET N1 ; 4 bytes
MOV CX, AX ; 2 byte
c. [5M] Before the termination of the code, the instruction queue
ORG 17
MOV CL, 5 ; 3 bytes is flushed number of times.
UP:
MUL AX ; 2 bytes
ADD AX, BX ; 2 bytes
DEC CL ; 1 byte
JNZ UP ; 2 bytes
.EXIT
END

3. [30M] Consider the following diagram, wherein a Timer 8254 and a Module 𝑋, via an 8255, are interfaced
with 8086. All unused ports of 8255 are to be declared as output ports, and 8255 is to be used in Mode 0.
The working of Module 𝑋 can be described as follows: Module 𝑋 receives 8 bits of data (𝐷0 − 𝐷7 ) from
8086, via Port A of 8255, and produces an output voltage given by the equation: 𝑂𝑢𝑡𝑝𝑢𝑡 =
𝐷 𝐷1 𝐷2 𝐷
𝑉𝑟𝑒𝑓 ( 20 + + 7
+ ⋯ + 256 ). Assume that the output of Module 𝑋 changes as soon as the input bits
4 8
change and remains same as long as the input bits remain same.
Assume that 8254 and 8255 are addressed using 8-bit port address. The address lines 𝐴1 and 𝐴5 of 8086 are
connected to 𝐴0 and 𝐴1 of 8255, respectively. The remaining 6 address lines of 8086 among 𝐴0 through 𝐴7
are given as inputs to a 6-input NAND gate, whose output generates the 𝐶𝑆̅̅̅̅ signal for 8255. Similarly, the
address lines 𝐴0 and 𝐴6 of 8086 are connected to 𝐴0 and 𝐴1 of 8254, respectively. The remaining 6 address
lines of 8086 among 𝐴0 through 𝐴7 are are each inverted using 6 distinct NOT gates and the inverted values
are given as inputs to a 6-input NAND gate, whose output generates the 𝐶𝑆̅̅̅̅ signal for 8254.
For the following code(s), answer the given questions in the provided box ONLY. Assume that the main
program and the ISR share the data segment, and that the ISR is for interrupt caused by 8254. Also, assume
that GATE0 is held at Logic 1 throughout the duration of operation and CLK0 is provided a square wave
input with duty cycle 50% and frequency 1 KHz while the 𝑉𝑟𝑒𝑓 of Module 𝑋 is connected to a +8V supply.

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 Name: ID No. Roll No.

Main program: ISR for INTR interrupt: a. [3X5=15M] For the intended
.MODEL SMALL
CMP LOOPCOUNT, 0 operation of 8255 and 8254 as
.DATA
JE L1 described above, the following
COUNT DW 1000
LOOPCOUNT DB 2 MOV AL, LOOPCOUNT values are to be (in Hexadecimal
.CODE OUT PA, AL number system):
.STARTUP
STI ; Set the Interrupt Flag MOV AL, 30H
MOV AL, CW8255
OUT CR8255, AL
OUT CR8254, AL Variable Value (in Hex)

MOV AL, 30H MOV AX, COUNT CW8255

OUT CR8254, AL SHL AX, 1
MOV COUNT, AX CR8255
MOV AX, COUNT OUT CNT0, AL
OUT CNT0, AL
MOV AL, AH MOV AL, AH PA
OUT CNT0, AL OUT CNT0, AL
DEC LOOPCOUNT CR8254
MOV AL, 04H IRET
OUT PA, AL L1: CNT0
MOV AL, 00H
HERE:
JMP HERE OUT PA, AL
.EXIT IRET
END

b. [15M] Draw the output voltage waveform in the box provided below (for the entire duration indicated),.
While drawing the output waveform, assume that the time taken for the execution of the code can be ignored
in comparison to the timescale of the output waveform. Note: Appropriate partial marks will be provided for
various components involved in the desired output.

Space to draw the output voltage waveform:

6
Output Voltage (in Volts)

0 1 2 3 4 5 6 7 8 9 10
Time (in Seconds)

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 SECTION II

Instructions:
1. This section has 20 MCQs each carrying 3 Marks for Correct answers and -1 Marks for wrong/illegible/overwritten answers.
Unanswered questions will be awarded zero marks.
2. Answers marked anywhere other than the box provided below will NOT be evaluated.
Answers: **Write the answers (correct option, i.e., A, B, C or D) for Section II in the box given below ONLY.**
Q. No. Answer (To be Marks (To be Q. No. Answer (To be Marks (To be
filled by the filled by the filled by the filled by the
student) evaluator) student) evaluator)
1 11
2 12
3 13
4 14
5 15
6 16
7 17
8 18
9 19
10 20

1. Consider a square wave signal with 50% duty cycle and frequency 𝑓 (with time period is 𝑇 = 1⁄𝑓 )
provided at GATE0. CLK0 will be provided with a square wave signal with 50% duty cycle and frequency
2 KHz. A value of 𝑁 = 1000 is loaded into Counter 0, which is configured to operate in Mode 1
(Programmable one shot mode). For which of the parameter values 𝑓 (or 𝑇) of the signal provided at
GATE0 will the output OUT0 go low and remain low indefinitely thereafter?
A. f = 1 Hz B. f = 0.5 Hz
C. T = 0.25 s D. T = 4 s

2. Three 8259 PICs are interfaced with an 8086 processor with one acting as the master and the remaining
as slaves. The slaves are connected to the inputs IR3 and IR6 of the master 8259. For the slave 8259
connected to IR6 input of master 8259, ICW3 is

A. 01H B. 48H
C. 03H D. 06H

3. Select the factually correct statement regarding 8086.

A. There are a total of 16 unidirectional B. The data bus is unidirectional

address lines
C. All data lines are multiplexed with some D. No clock input is required for its operation
address lines

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Name: ID No. Roll No.

4. An address decoding circuit is designed such that each memory location in the memory chip has a unique
physical address. Which of the following statements is factually correct about such a scheme?

A. Such a circuit could possibly utilize B. It will exhibit fold back

multiple digital gates
C. It need not utilize all address lines D. None of the remaining
options

5. The decimal equivalent of the binary number 1001.011 is

A. 9.75 B. 9.375
C. 9.625 D. 9.25

6. When the following code snippet is executed, which of the flags will be set?
MOV AX, 53H
MOV CX, 24H
ADD AX, CX

A. Parity B. Overflow
C. Sign D. Zero

7. Consider the execution of the instruction MOV AX, PRICE, where PRICE has been defined as a word type
variable in the data segment. Choose the factually correct statement.

A. If the lower byte of data associated with PRICE is stored in 0000CFH, then the instruction will
take one bus cycle to load the AX register.
B. If the lower byte of data associated with PRICE is stored in 000020H, then the instruction will
take two bus cycles to load the AX register.
C. The addressing mode is Indirect Addressing mode since a memory location is accessed through
a variable name.
D. The addressing mode is Direct Addressing mode since a memory location is accessed through a
variable name.

8. When a programmer reads OCW1 of an 8259 PIC, the value 7DH is placed in the AL register. Select the
factually correct statement.

A. The type number associated with one of the interrupt request inputs is 7DH.
B. The interrupt request input IR1 of 8259 is not masked.
C. The interrupt request input associated with type number 7DH is currently being serviced by
8259.
D. The interrupt request input associated with type number 7DH has the highest priority.

9. The decimal equivalent of 25.01H (when rounded to 4 digits after the decimal point) is
A. 37.0625 B. 37.0664
C. 37.0039 D. 25.0100

10. If a counter in 8254 is configured to operate in Mode 0 (Interrupt on Terminal Count mode), then the
highest delay that can be obtained with a clock input of 1 MHz is
A. 65.537ms B. 65.536ms
C. 65.535ms D. None of the remaining options
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11. An 8254 timer chip is interfaced with 8086 and configured as follows: Counter 0 is configured in Mode 2
(Rate Generator mode) with count value 04H while Counter 1 is configured in Mode 3 (Square Wave
Generator mode) with count value 0AH. Counter 0 is provided with a 1 MHz clock signal at CLK0 input
whereas the OUT0 is connected to CLK1. Both GATE0 and GATE1 are held at Logic 1 for the entire
duration of the operation. The time period of the waveform obtained at OUT1 is
A. 500µs B. 50µs
C. 500ms D. 50ms

12. Upon executing the following code snippet, the values in SI and DI registers respectively are
MOV SI, 3000H
MOV DI, 5004H
A. 2FFAH and 4FFFH B. 3005H and 500AH
MOV CX, 05H
C. 2FFAH and 500AH D. 3005H and 4FFFH
UP:
CLD ; Clear Direction Flag
LODSB
STD ; Set Direction Flag
STOSB
LOOP UP
13. The value in the AL register after the execution of the following code snippet is
MOV AL, 68H
ADD AL, 32H
DAA

A. 9AH B. 100
C. 00H D. A9H

14. An 8254 timer chip is interfaced with 8086 and configured as follows: Counter 2 is configured in Mode 3
(Square Wave Generator mode) with count value 0FH while Counter 0 is configured in Mode 1
(Programmable One Shot mode) with count value 05H. Counters 0 and 2 are provided with a 1 MHz clock
signal at CLK0 and CLK2, respectively. OUT2 is connected to GATE0 whereas GATE2 is held at Logic 1
for the entire duration of the operation. Select the factually correct statement regarding the waveform
generated at OUT0.

A. The waveform is periodic with period 15µs.

B. The waveform is periodic with period 5µs.
C. The waveform corresponds to an aperiodic signal which goes from high to low and remains low
indefinitely.
D. The waveform corresponds to an aperiodic signal which goes from low to high and remains
high indefinitely.

15. Select the factually incorrect statement.

A. The offsets within the code segment are referenced using the Instruction Pointer (IP).
B. The execution unit computes the 20-bit physical address and places it on the address lines for
memory access operations.
C. It is possible to access the data in any order from the stack.
D. The source data used in the instruction having immediate mode of addressing is stored in the
code segment instead of data segment, and will be loaded into the instruction queue.

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 Name: ID No. Roll No.

16. Consider an interrupt request via 8259 PIC whose type number is 1DH. The vector address of this
interrupt is
A. 70H B. 74H
C. 70 D. 74

17. When an 8255 chip is configured to operate in Mode 1 (Strobed I/O or Handshaking mode), the handshaking
signals are available at
A. Port C B. Control Register
C. Port B D. Port A
18. An 8259 PIC chip is configured to operate with Automatic End of Interrupt (AEOI) with rotating priorities.
When the interrupt request received at the IR4 pin of this 8259 is deemed to be serviced, the corresponding
bit in the ISR register is reset. Thereafter, the interrupt request input that gets the highest priority is
A. IR4 B. IR5
C. IR6 D. IR0

19. The contents of the DS register is 23A7H and a total of 1KB of data is to be stored in the data segment
starting with offset 0000H. Then, the physical address of the last byte of data is
A. 23D7FH B. 23E7FH
C. 23D6FH D. 23E6FH
20. Suppose an 8259 PIC chip connected to 8086 processor is to handle interrupt requests from 8 distinct devices
connected via IR0 through IR7. At a certain time, assume that the ISR register of this 8259 contains the
value AAH. At this time, the 8259 receives the value 61H from 8086 into OCW2. Then, the revised value
of the ISR register will be (assume that, once the ISR register’s value is updated, no new interrupt requests
are received or any existing requests finish their service)
A. A2H B. A8H
C. 2AH D. 8AH

******************************** END OF PAPER **************************************

[Appendix from next page]

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 APPENDIX
FLAG register of 8086:

Control words for 8255:

Entity selection for 8255: Entity selection for 8254:

Control word for 8254:

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 Name: ID No. Roll No.

Waveform for Mode 0 of 8254: Waveform for Mode 2 of 8254:

Load Count

Waveform for Mode 1 of 8254: Waveform for Mode 3 of 8254:

Format for ICW2:

Format for ICW4:

Format for ICW1:

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 Format for OCW2:
Format for ICW3:

Format for OCW1:

Format for OCW3:

******************************** END OF APPENDIX **************************************

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