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  • ACFrOgDTcrHsd1p u2fy48NZlRduvDog2JCPiUgwvYcoTx7O98hnrq4vhD4tVUHDGqHUXSA1jBF0ejk3ZA0Xf68LV auZY4iO1lJG57yVctwvDTlXI30RFii5gIWinsRjBxKDDmdLYhd7WQU631V

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    Uday Kumar
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    The document contains 10 multiple choice and short answer questions about computer architecture topics like: 1. Which architecture is most power efficient - RISC or CISC. 2. Caches are commonly used to reduce memory access time. 3. Micro-instruction and micro-programmed control signals are used to generate control signals. 4. A write miss occurs if the required block is not present in the cache during a write operation. 5. The fraction of successful memory accesses is called the hit rate. The remaining questions cover the 8086 pin diagram, virtual memory, TLB, array vs vector processing, and arithmetic/instruction pipelines.

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    ACFrOgDTcrHsd1p-u2fy48NZlRduvDog2JCPiUgwvYcoTx7O98hnrq4vhD4tVUHDGqHUXSA1jBF0ejk3ZA0Xf68LV-auZY4iO1lJG57yVctwvDTlXI30RFii5gIWinsRjBxKDDmdLYhd7WQU631V

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    The document contains 10 multiple choice and short answer questions about computer architecture topics like: 1. Which architecture is most power efficient - RISC or CISC. 2. Caches are commonly used to reduce memory access time. 3. Micro-instruction and micro-programmed control signals are used to generate control signals. 4. A write miss occurs if the required block is not present in the cache during a write operation. 5. The fraction of successful memory accesses is called the hit rate. The remaining questions cover the 8086 pin diagram, virtual memory, TLB, array vs vector processing, and arithmetic/instruction pipelines.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    6 views1 page

    ACFrOgDTcrHsd1p u2fy48NZlRduvDog2JCPiUgwvYcoTx7O98hnrq4vhD4tVUHDGqHUXSA1jBF0ejk3ZA0Xf68LV auZY4iO1lJG57yVctwvDTlXI30RFii5gIWinsRjBxKDDmdLYhd7WQU631V

    Uploaded by

    Uday Kumar
    The document contains 10 multiple choice and short answer questions about computer architecture topics like: 1. Which architecture is most power efficient - RISC or CISC. 2. Caches are commonly used to reduce memory access time. 3. Micro-instruction and micro-programmed control signals are used to generate control signals. 4. A write miss occurs if the required block is not present in the cache during a write operation. 5. The fraction of successful memory accesses is called the hit rate. The remaining questions cover the 8086 pin diagram, virtual memory, TLB, array vs vector processing, and arithmetic/instruction pipelines.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 1

    Sugesstions on architecture:

    1. Which of the architecture is power efficient?


    a) RISC b) ISA c) IANA d) CISC

    2. To reduce the memory access time we generally make use of ______


    a) SDRAMs b) Heaps c) Caches d) Higher capacity
    RAMs

    3. ________ are the different type/s of generating control signals.


    a) Hardwired b) Micro-instruction c) Micro-programmed d) Both Micro-
    programmed and Hardwired

    4. During a write operation if the required block is not present in the cache then ______
    occurs.
    a) Write miss b) Write latency c) Write hit d) Write delay

    5. The number of successful accesses to memory stated as a fraction is called as _____


    a) Access rate b) Success rate c) Hit rate d) Miss rate

    6. Draw the Pin Diagram of 8086? And explain the pins?


    7. what is virtual memory? explain logical and physical address.
    8. write short note on TLB?
    9. write the difference between array and vector processing?
    10. what do you mean by arithmetic and instruction pipeline?

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