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Question 1
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We combine adjacent squares of the K-map that contain zeros to obtain which simplified
form of Boolean function?

Product of sums
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Question 2
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These are combinational circuits that perform the addition of three bits.

Full adder
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Question 3
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The following are equivalent functions
of F(A,B,C,D)=Σ(0,6,8,13,14)F(A,B,C,D)=Σ(0,6,8,13,14) with don't-care
conditions d(A,B,C,D)=Σ(2,4,10)d(A,B,C,D)=Σ(2,4,10), except one.

Select one:

a.
F=(B+D)′+(C′+D)′+(A+D)′+(A′+B′+C+D′)′F=(B+D)′+(C′+D)′+(A+D)′+(A′+B′+C+D′)′

b.
F=B′D′+CD′+A′D′+ABC′DF=B′D′+CD′+A′D′+ABC′D

c.
F=(D⊕ABC′)′F=(D⊕ABC′)′

d.
F=D⊕ABC′F=D⊕ABC′
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Question 4
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It is a logic circuit consisting of gates whose outputs at any time are a function of the
combination of inputs.

Select one:

a.
Parallel logic circuit

b.
Sequential logic circuit

c.
Combinational logic circuit

d.
Serial logic circuit
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Question 5
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It is a logic circuit composed of logic gates and storage elements. Its output is a function of
the inputs and the state of the storage elements.

Select one:

a.
Combinational logic circuit

b.
Parallel logic circuit

c.
Serial logic circuit

d.
Sequential logic circuit
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Question 6
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It is a table or diagram made up of squares which provides a simple way to minimize
Boolean functions.

Karnaugh map
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Question 7
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The following are steps involved in designing combinational circuits, except one:

Select one:

a.
Draw the diagram.

b.
Derive the truth table.

c.
Obtain the simplified Boolean functions of the output in terms of the input.

d.
Label the inputs and outputs with arbitrary symbols.
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Question 8
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Obtain the simplified Boolean expression for the output FF in terms of the input variables in
the circuit shown below. Give the expression only (no need to include F=F=), and do not
put spaces between the variables and operators.
 A'D+ABC
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Question 9
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Simplify the function F=wx′+y′z′+w′yz′F=wx′+y′z′+w′yz′ and express the simplified function
with OR operations.

Select one:

a.
F=(w+x′)+(y′+z′)+(y+z′)F=(w+x′)+(y′+z′)+(y+z′)

b.
F=(w′+x)+(y+z)+(w+z)F=(w′+x)+(y+z)+(w+z)

c.
F=(w+x′)′+(y′+z′)′+(y+z′)′F=(w+x′)′+(y′+z′)′+(y+z′)′

d.
F=(w′+x)′+(y+z)′+(w+z)′F=(w′+x)′+(y+z)′+(w+z)′
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Question 10
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TRUE OR FALSE: When adding negative numbers in two's complement system, signed
overflow occurs when there is a carry into and a carry out of the sign bit.

Select one:
True
False