LOGICAL OPERATIONS

LOGICAL OPERATIONS

C and Java logical operators and their corresponding ARM

instructions
Logical operations C operators Java Operators ARM instruction

Bit by bit AND & & AND

Bit by bit OR | | ORR

Bit by bit NOT ~ ~ MVN

Shift left << << LSL

Shift right >> >>> LSR

ARM implements NOT using a NOR with one operand

being zero
LOGICAL OPERATIONS (2)
AND is a bit-by-bit operation that leaves a 1 in the result only if
both bits of the operands are 1
If register r2 contains
0000 0000 0000 0000 0000 1101 1100 00002
and register r1 contains
0000 0000 0000 0000 0011 1100 0000 00002
then AND r5, r1, r2 ; reg r5 = reg r1 & reg r2
The value of register r5
0000 0000 0000 0000 0000 1100 0000 00002
ORR r5, r1, r2 ; reg r5 = reg r1 | reg r2
The value of register r5 0000 0000 0000 0000 0011 1101 1100
00002
LOGICAL OPERATIONS (3)
MVN r5, r1 ; reg r5 = ~ reg r1
Value of register r5 1111 1111 1111 1111 1100 0011 1111 11112
AND A logical bit-by bit operation with two operands that calculates a 1
only if there is a 1 in both operands
OR A logical bit-by bit operation with two operands that calculates a 1 if
there is a 1 in either operand
NOT A logical bit-by bit operation with one operand that inverts the bits;
that is, it replaces every 1 with a 0, and every 0 with a 1
MOV r6, r5 ; reg r6 = reg r5
Shifts - move all the bits in a word to the left or right, filling the emptied
bits with 0s
if register r0 contain
0000 0000 0000 0000 0000 0000 0000 10012 = 910
and the instruction to shift left by 4 , the new value would be:
0000 0000 0000 0000 0000 0000 1001 00002= 14410
LOGICAL OPERATIONS (4)
Shifting left by i bits gives the same result as multiplying by
2i, just as shifting a decimal number by i digits is equivalent
to multiplying by 10i
For example, the above LSL shifts by 4, which gives the
same result as multiplying by 24 or 16
The first bit pattern above represents 9, and 9 × 16 = 144, the
value of the second bit pattern
Dual of the shift left is shift right
ARM offers the ability to shift the second operand as part of
any data processing instruction
ARM hardware is designed such that adds with shift are no
slower than simple adds
MACHINE INSTRUCTION FOR LOGICAL OPERATIONS
ADD r5, r1, r2, LSL #2 ; r5 = r1+(r2 << 2)
MOV r6, r5, LSR #4 ; r6 = r5 >> 4
ARM allows shifting by value found in a register
MOV r6, r5, LSR r3 ; r6 = r5 >> r3
11 8 7 6 5 4 3 0
Shift_imm Shift 0 Rm
Rs 0 Shift 1 Rm

Con F I Opcode S Rn R Shift_imm Shift Rm

d d
Rs 0 Shift Rm
14 0 0 4 0 1 5 0 2 0 0 2
14 0 0 13 0 0 6 0 4 1 0 5
14 0 0 13 0 0 6 3 0 1 1 5