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Procedia Computer Science 173 (2020) 140–148
International Conference on Smart Sustainable Intelligent Computing and Applications under
ICITETM2020
International Conference on Smart Sustainable Intelligent Computing and Applications under
Design and Implementation ofICITETM2020
Fast Booth-2 Multiplier on Artix FPGA 
Abhinav Behla, Abhilasha Gokhaleb, Neelam Sharmac
Design and Implementation of Fast
RTL designer, Logic Booth-2
Fruit Technologies,
a Multiplier
Guru gram, Delhi on Artix FPGA 
AbhinavDepartment
Behla,ofAbhilasha
b&c Gokhaleb, Neelam Sharmac
Electronics and communication, MAIT, New Delhi
a
RTL designer, Logic Fruit Technologies, Guru gram, Delhi
b&c
Department of Electronics and communication, MAIT, New Delhi
Abstract

Now a day’s speed is very important to meet the requirement of user in today’s chips. We want faster smart phones, laptops and
other gadgets that can work at a speed even beyond our imagination. In this paper we have designed a fast multiplier which can
Abstract
provide better results. RBSD stands for Redundant Binary Signed Digit number system which enables fast computing by
Now a day’s
reducing speed
carry is very important
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This workmultiplier
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implemented imagination.
using VIVADOIn2019.2 this paper we have
version. The designed
multiplieraisfast multiplier which
implemented can
in VHDL
provide
language.better results.
Although thereRBSD stands
is a slight for Redundant
increase Binary
in the delay using Signed
VIVADO Digit number there
Multiplier, system
is awhich enables
significant fast computing
decrease by
in the number
reducing carryWepropagation
of LUT used. have used artixtimeFPGA
as carry is part
[4] with not number
propagated to later stages. This number system is signed digit number
xc7a200tisbv484.
representation. This RBSD multiplier is implemented using VIVADO 2019.2 version. The multiplier is implemented in VHDL
© 2020 The
language. Authors.there
Although Published by Elsevier
is a slight increaseB.V.
in the delay using VIVADO Multiplier, there is a significant decrease in the number
of LUT used. We have used artix FPGA[4] with part number xc7a200tisbv484.
This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
© 2020
© 2020 The Authors. Published by Elsevier B.V.
Peer-review under
This is an open responsibility
access article underofthe
theCCscientific
BY-NC-NDcommittee
licenseof(http://creativecommons.org/licenses/by-nc-nd/4.0/)
the International Conference on Smart Sustainable Intelligent
Computing
This
Peer-review and
is an open Applications
access
under responsibilityunder
article under ICITETM2020
thescientific
of the CC BY-NC-ND license
committee of the(http://creativecommons.org/licenses/by-nc-nd/4.0/
International. )
Keywords: RBSD
Peer-review - Redundant
under Binary of
responsibility Signed
the Digit; FPGA-
scientific Field Programmable
committee Gate Array. Conference on Smart Sustainable Intelligent
of the International
Computing and Applications under ICITETM2020

1. Introduction
Keywords: RBSD - Redundant Binary Signed Digit; FPGA- Field Programmable Gate Array.

Multiplication is the key circuit block in modern days chips. This block is used in digital computing systems, controllers, filters,
1. Introduction
signal processors and various logic blocks as well. Since technology is updating every moment it is our prime need to implement
fast multiplier in modern days VLSI chips. Presently there is high expansion in computer applications such as Artificial
Multiplication is the keygraphics,
intelligence, Computer circuit block in application
Filter modern daysandchips.
manyThis blockVLSI
more. is used in digital computing
technology has evolvedsystems, controllers,
in so many years filters,
which
signal
resultedprocessors and variousoflogic
in implementation blocks
complex as well. Since
technology technology
easily. A normalis multiplication
updating everyhas moment it is our prime
two operations first need
is to togenerate
implement
the
fast multiplier
partial products inandmodern
seconddays
is to VLSI chips.
add those Presently
partial there
products. is high
If we want expansion
to implementin computer applications
a fast multiplier then we such
mustasreduce
Artificial
the
intelligence, Computer
number of partial graphics,
products which Filter application
are generated, or and manymake
we must more.their
VLSI technology
addition much has evolved
faster. in soalgorithm
One such many years which
is Booth’s
resulted in implementation of complex technology easily. A normal multiplication has two operations first is to generate the
partial products and second is to add those partial products. If we want to implement a fast multiplier then we must reduce the
number of partial products which are generated, or we must make their addition much faster. One such algorithm is Booth’s
1877-0509 © 2020 The Authors. Published by Elsevier B.V.
This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Peer-review under responsibility of the scientific committee of the International Conference on Smart Sustainable Intelligent Computing and
Applications
1877-0509 ©under ICITETM2020
2020 The Authors. Published by Elsevier B.V.
This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Peer-review under responsibility of the scientific committee of the International Conference on Smart Sustainable Intelligent Computing and
Applications under ICITETM2020

1877-0509 © 2020 The Authors. Published by Elsevier B.V.

This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Peer-review under responsibility of the scientific committee of the International.
10.1016/j.procs.2020.06.018
 Abhinav Behl et al. / Procedia Computer Science 173 (2020) 140–148 141
2 Abhinav Behl/ Procedia Computer Science 00 (2019) 000–000

algorithm; in this we can represent a group of bits by a symbol. In following section, we will discuss about the modified booth’s
algorithm. The partial products which are generated are of the booth’s form and need to be added by booth adder only.

2. Designing of Multiplier

In this multiplier, we majorly have four blocks which will perform the actual multiplication. These four blocks
are as follows: -

1) Binary to RBSD Converter

2) Partial Product generator

3) Radix-4 RBSD Adder

4) RBSD-Binary Converter

3. RBSD number representation

RBSD i.e. Redundant Binary Signed Digit Representation was designed to perform an addition in which carry is
resolved in initial stages only. In this number system we have different radix possible. Radix is a value which
represent number of different characters which will be used to represent the number. In the traditional number
system, each digit can assume only r values ‘r’ representing the radix of number system, r=10 for decimal system,
r=2 for binary. In RBSD number system, each digit can take more than r values. A signed digit can take (2θ, +1)
values.

∑r= (-θ... -1, 0, 1...θ)

4. Radix-4 Booth’s Encoding

Radix-4 Booth’s encoding which is also known as Booth-2 encoding. Now since the encoding will be performed
in parallel the logic will divide the multiplier into overlapping sets of 3 bits. The selection of multiplicand(M) is
based on the table which is provided in this section. Xi represent the present bit, Xi+1 represent the next high order
bit and Xi-1 represent the lower order bit. The encoding will be done parallelly giving the RBSD output. The
number of partial products is reduced to a significant number. They are reduced to approximately half. All the
multiples are obtained shifting of bits to the multiplicand.

Table 1. Multiple selection

Multiplier bits Multiple

Xi+1Xi Xi-1 selection
00 0 0
00 1 +M
01 0 +M
01 1 +2M
10 0 -2M
10 1 -M
11 0 -M
11 1 0

4.1. Example 1

Let us consider an example to convert a number to RBSD form. Let us convert (13)10 i.e. 1101 to its RBSD
form. Firstly, we will start from lowest three bits (i.e. 101 in this case) and select its corresponding multiple from
142 Abhinav Behl et al. / Procedia Computer Science 173 (2020) 140–148
Abhinav Behl/ Procedia Computer Science 00 (2019) 000–000 3

Table 2 shown above. For first three lower bits, it is „-M‟. Now we will consider next three bits i.e. 110 and its
corresponding multiple is „–M‟ again. We will follow the procedure till the MSB is not covered.

Hence for 001101 (appending two zeros on the left):

1 0 1 -M

1 1 0 -M

0 1 1 +2M

0 0 1 +M
So (13)10 or (1101)2 becomes {+M, +2M, -M, -M} in RBSD form. It can easily be converted

back by considering the weight of each position i.e.

1 X ( -1 ) + 2 X ( -1 ) + 4 X ( +2 ) + 8 X ( +1 ) = - 1 - 2 + 8 + 8 = 13.

4.2. Example 2

For 001001 (appending two zeros on the left):

0 0 1 +M

1 0 0 -2M

0 1 0 +M

0 0 1 +M

So (9)10 or (1001)2 becomes {+M, +2M, -2M, +M} in RBSD form. It can easily be converted back by
considering the weight of each position i.e.

1 X ( +1 ) + 2 X ( -2 ) + 4 X ( +1 ) + 8 X ( +1 ) = + 1 - 4 + 4 + 8 = 9

5. RBSD Booth Multiplier

As discussed in previous section, we require four blocks to carry the multiplication. These blocks are Partial
Product Generator, Carry Free Adder, Carry propagator and RBSD converter. The function of the blocks is to add
the partial product and generate carry according to the intermediate partial products.
 Abhinav Behl et al. / Procedia Computer Science 173 (2020) 140–148 143
4 Abhinav Behl/ Procedia Computer Science 00 (2019) 000–000

Fig.1. Booth -2 multiplier implementation

5.1. Example 1

Now let us consider a multiplication of two numbers i.e. (13)10 x (9)10 or (1101)2 x (1001)2. According to the
algorithm, we will first convert one number to RBSD form and then multiply it with the binary number which will
generate the partial products in between. And finally, after adding the partial products, we will get the multiplication
result in the RBSD form. Then it will be converted to binary again. This algorithm is useful for the large numbers,
but we will understand it by the above example. So, let’s get started:

As from the previous example, (1101)2 is converted to {+M, +2M, -M, -M} in RBSD form so we will multiply it
to (1001)2 to get the answer
1001

x +M +2M -M -M

-----------------------------------------------
-M 0 0 -M

-M 0 0 -M x

+2M 0 0 +2M x x
144 Abhinav Behl et al. / Procedia Computer Science 173 (2020) 140–148
Abhinav Behl/ Procedia Computer Science 00 (2019) 000–000 5

+M 0 0 +M x x x

-----------------------------------------------

+M +2M -M 0 +2M -M -M

-----------------------------------------------

The result after multiplication is {+M, +2M, -M, 0, +2M, -M, -M, } and now after multiplying these values to
the corresponding weights, we will get the final answer.

{+M, +2M, -M, 0, +2M, -M, -M, }

2 2 2 2 2 2 2

6 5 4 3 2 1 0

i.e. 64x (+1) + 32x (+2) + 16x (-1) + 0 + 4x (+2) + 2x (-1) + 1x (-1) = 64+64-16+8-2-1 = (117)10

Hence the correct answer is obtained!

5.2. Example 2

Now let us consider another multiplication of two numbers i.e. (6)10 x (9)10 or (0110)2 x (1001)2. According to
the algorithm, we will first convert one number to RBSD form and then multiply it with the binary number which
will generate the partial products in between. And finally, after adding the partial products, we will get the
multiplication result in the RBSD form. Then it will be converted to binary again. This algorithm is useful for the
large numbers, but we will understand it by the above example. So, let’s get started:

As from the previous example, (1001)2 is converted to {+M, +M, -2M, +M} in RBSD form so we will multiply
it to (1001)2 to get the answer.

0110

x +M +M -2M +M

-------------------------------------

0 +M +M 0

0 -2M -2M 0 x

0 +M +M 0 x x

0 +M +M 0 x x x
--------------------------------------

0 +M +2M -M -M +M 0

--------------------------------------
The result after multiplication is {+M, +2M, -M, -M, +M, 0} and now after multiplying these values to the
corresponding weights, we will get the final answer.

{+M, +2M, -M, -M, +M, 0 }

2 2 2 2 2 2
 Abhinav Behl et al. / Procedia Computer Science 173 (2020) 140–148 145
6 Abhinav Behl/ Procedia Computer Science 00 (2019) 000–000

5 4 3 2 1 0

i.e. 32x (+1) + 16x (+2) + 8x (-1) + 4x (-1) + 2x (+1) + 0 = 32 + 32 - 8 -4 +2 = (54)10

Hence the correct answer is obtained!

6. FPGA Implementation

FPGA do not support signed numbers hence we cannot represent +m or +2m or -2m directly on the FPGA.
Hence, we need to discover further possibilities in fpga for this scenario. In the FPGA we used a combination of
three bits to represent RBSD numbers. And addition is also in the form of three buts only. We have used One hot
encoding for these bits so that we can get faster result.

“000”→0

“001”→+M

“010”→+2M

“101”→-M

“110”→-2M

7. VIVADO Synthesis

Vivado is a software provide by XILINX. It is a very powerful tool for generating bit file. This tool can help us to
generate the bit file, compare timing and see timing for each path, and even allow us to add constraint to our design.
The simulator used is Vivado simulator only. In the synthesis report [5] we can see the number of LUT that have been
used for the design. It also generates timing reports. We can also see elaborated design. Vivado also provide on
board debugging tools such as ILA. As per XILINX Vivado 2019.3 also provide support for system Verilog
construct though we cannot have coverage report. Vivado also shows setup and hold time violation if they occur in
our design.

8. Simulation Result

The above design was verified on vivado simulation environment. The simulation screen shots are attached. Data
is entered in hexadecimal format.
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Abhinav Behl/ Procedia Computer Science 00 (2019) 000–000 7

Fig.2. Simulation result

9. Timing and Utilization comparison

Vivado provides a feature to synthesize our design and see timing for the design. This means we can check
timing[6] for our design in the software itself. The timing is different for different paths. We looked for the Data path
delay that was added in the design when we used RBSD multiplier and when we used vivado generated multiplier.

The logic delay is for the longest path only. It was observed that when we used vivado multiplier the delay was
more. The above observations are only for 8-bit multiplier. In binary multiplier the if the carry is generated at the
first stage it will be carried to next all stages and hence it will add a delay to the logic. We must wait for the carry.
As a result, the logic will be delayed, and multiplier will not be fast. Since FPGA are much slower as compared to
ASIC hence it is not possible to get the maximum clock frequency on which both the design (RBSD multiplier and
binary multiplier) can work.

Vivado also shows the synthesis report. In the report we can see the number of flip flops that are used for the
design. We can also see the number of LUT that are used in the FPGA and how much resources are utilized in the
design. As per the observation it is evident that there is a tradeoff between area and timing. If we want good timing
result, then we can use RBSD multiplier but if we do not have area on the chip and timing is not an issue then we
can go with the binary multiplier design. If we are using FPGA then we can obviously use binary multiplier for
small number of bits multiplication because FPGA do not run on such high speeds that such a small difference will
be an issue in an FPGA.

Table 2. Timing and synthesis Analysis

Timing Logic delay Net delay

Vivado multiplier 2.230 ns 1.713 ns
RBSD multiplier 1.044 ns 0.800 ns
Synthesize LUT used Flip-Flop used
Vivado multiplier 71 16
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8 Abhinav Behl/ Procedia Computer Science 00 (2019) 000–000

RBSD multiplier 1591 16

Acknowledgments

Abhinav Behl had passed B. Tech (ECE) from Maharaja Agrasen Institute of Technology, GGSIPU in 2019 and
currently working with Logic Fruit Pvt Ltd. His areas of interest are VLSI, Digital electronic and embedded
systems. He loves to gain knowledge and explore unexplored areas. He is learning FPGA a want to work in the same
field. He is oriented towards technical knowledge and love to work in the field of Semiconductors.

Abhilasha Gokhale completed her B.E. (ECE) from Marathwada University, Aurangabad with distinction. She
passed M.Tech. (EC) from Delhi College of Engineering, Delhi University. She had worked on two papers which
were published in international general and had also contributed 7 papers in both international and national
conferences. She has guided more than 55 undergraduate students in their projects in the field of Micro controllers
and Embedded Systems. Her areas of interest include Computer Architecture, Switching Theory and Logic Design,
Microprocessors and Micro controllers and Embedded Systems

Neelam Sharma has completed her Ph.D. in Electronics Engineering from U.P. Technical University , Lucknow.
She did her B.E. (Hons.) in ECE from Thapar Institute of Engg. And Tech. in 1985 and has guided 5 Ph.D’s. and
many Dissertations and Projects. Guru Nanak Dev University , Amritsar has awarded her the Gold Medal for
topping Class 12th Examinations in the state of Punjab. VLSI Design & Technology, Nanotechnology, CAD, VHDL
and Computer Architecture are her Research areas. She has published 75 papers and 5 books and has Completed
many Projects in Collaboration with World Bank, AICTE ,MHRD and GGSIPU.

References

[1]”A Novel Redundant Binary Signed Digit (RBSD) Booth’s Encoding”, R. G. Deshmukh; Florida Institute of Technology, Melbourne, FL;
Nurettin Besli, Florida Institute of Technology; Melbourne, FL

[2] “Multiplier Design using RBSD Number System”, A. A. S Awwal and J. U. Ahmed, Wright State University, Computer Science &
Engineering Department, Dayton, Ohio

[3] “High Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree”, H. Yasuura, N.Takagi and S.Yajima, IEEE Trans.
Comp., C-34, pp. 789-795, 1985
148 Abhinav Behl et al. / Procedia Computer Science 173 (2020) 140–148
Abhinav Behl/ Procedia Computer Science 00 (2019) 000–000 9

[4] “On-Line Error Detectable High-Speed Multiplier using Redundant Binary Representation and Three-Rail Logic”, N. Takagi and S. Yajima,
IEEE Tran. Comp, Vol. C-36, No. 11, Nov. 1987.

[5] “Fast Computing using Signed Digit Number System”, Neelam Sharma, Reena Rani and L.K. Singh, IEEE Explorer2009.

[6] “ Design of Fast Pipelined Multiplier using Modified Redundant Adder”, Rakesh Kumar Saxena, Neelam Sharma and A. K. Wadhwani,
International Journal of Intelligent Systems and Applications (IJISA), MECS Publisher Hongkong.