ESSAY

QUESTION 1
 FLOWCHART

START

MOVS R0, #0
MOVS R1, #4
MOVS R2, #1
LDR R3 =0x037A

MULS R2, R1, R2

SUBS R2 #1
NO

R0=5

YES

SUBS R2, R2, R3

END
Describe the main features of the Cortex M3 processor core: architecture, instruction
set, instruction execution, pipe-line, major internal core blocks and operating modes.

ChatGPT
The Cortex-M3 processor core, developed by ARM, is a widely used 32-bit embedded
microcontroller core. It is designed to be power-efficient and provide high-
performance processing capabilities for a variety of applications. Here are the main
features of the Cortex-M3 processor core:

Architecture: The Cortex-M3 core follows a Harvard architecture, which means it has
separate instruction and data buses. It features a 3-stage pipeline, allowing for
efficient instruction fetching, decoding, and execution.

Instruction Set: The Cortex-M3 core uses the Thumb-2 instruction set, which
combines 16-bit and 32-bit instructions to provide a balance between code density
and performance. It supports a rich set of instructions optimized for embedded
applications, including arithmetic operations, logical operations, data transfer
instructions, control flow instructions, and more.

Instruction Execution: The Cortex-M3 core employs a 3-stage pipeline for instruction
execution. It includes an instruction fetch stage, an instruction decode stage, and an
execution stage. This pipeline design helps to minimize pipeline stalls and maximize
instruction throughput.

Pipeline: The Cortex-M3 core's pipeline consists of three stages: fetch, decode, and
execute. The fetch stage retrieves instructions from memory, the decode stage
decodes the instructions, and the execute stage performs the actual computation or
operation specified by the instruction.

Major Internal Core Blocks: The Cortex-M3 core includes various internal blocks that
contribute to its functionality, such as:

CPU Core: This is the main processing unit responsible for executing instructions
and controlling the overall operation of the core.
Memory Protection Unit (MPU): The MPU provides memory access control and
protection mechanisms, allowing for secure and isolated execution environments.
Nested Vectored Interrupt Controller (NVIC): The NVIC manages interrupts and their
priorities, ensuring efficient handling of interrupt requests.
Bus Interfaces: The core includes interfaces to connect with various bus protocols,
such as the Advanced High-performance Bus (AHB) or Advanced Peripheral Bus
(APB), enabling communication with external devices.
Debug and Trace Support: The Cortex-M3 core provides debugging and trace
capabilities, allowing developers to analyze and troubleshoot code execution.
Operating Modes: The Cortex-M3 core supports multiple operating modes to optimize
power consumption and performance. The main operating modes include:

Thread Mode: This is the normal operating mode where the core executes application
code.
Handler Mode: When an interrupt or exception occurs, the core switches to this mode
to handle the event and prioritize its execution.
Sleep Mode: The core can enter a low-power sleep state to conserve energy when no
active processing is required.
Deep Sleep Mode: This is an even lower-power sleep state that allows for extended
periods of inactivity.
QUESTION 2

RCC->IOPENR |=(1UL<< 0|1UL<< 2);

GPIOA->MODER &=~(1UL<<10|1UL<<11) | (1UL<<12|1UL<<13);
GPIOA->MODER |=(1UL<< 10|1UL<<12 );
GPIOA->OTYPER &=~(1UL<<5 | 1UL<<6);
GPIOA->OSPEDER &=~(1UL<<10|1UL<<11) | (1UL<<12|1UL<<13);

GPIOC->MODER &=~(1UL<<26|1UL<<27) | (1UL<<28|1UL<<29);

WHILE
{
y=GPIOC->IDR & (1UL<<13);
x=GPIOC->IDR & (1UL<<14);

if (y==1 && x==1);

{
GPIOA-> ODR &=~(1UL<<5 | 1UL<<6);
}
else (y==1 || x==0);
{
GPIOA->ODR |=(1UL<<5);
//blink 2 times
GPIOA->ODR |=(1UL<<6);
HAL_Delay (1000);
GPIOA->ODR &=~(1UL<<6);
HAL_Delay (1000);
GPIOA->ODR |=(1UL<<6);
HAL_Delay (1000);
GPIOA->ODR &=~(1UL<<6);
HAL_Delay (1000);
}
else (y==0|| x==1);
{
GPIOA->ODR |=(1UL<<5);
//blink 3 times
GPIOA->ODR |=(1UL<<6);
HAL_Delay (1000);
GPIOA->ODR &=~(1UL<<6);
HAL_Delay (1000);
GPIOA->ODR |=(1UL<<6);
HAL_Delay (1000);
GPIOA->ODR &=~(1UL<<6);
HAL_Delay (1000);
GPIOA->ODR |=(1UL<<6);
HAL_Delay (1000);
GPIOA->ODR &=~(1UL<<6);
HAL_Delay (1000);

}
else (y==0 || x==0);
{
GPIOA->ODR |=(1UL<<5);
//blink 4 times
GPIOA->ODR |=(1UL<<6);
HAL_Delay (1000);
GPIOA->ODR &=~(1UL<<6);
HAL_Delay (1000);
GPIOA->ODR |=(1UL<<6);
HAL_Delay (1000);
GPIOA->ODR &=~(1UL<<6);
HAL_Delay (1000);
GPIOA->ODR |=(1UL<<6);
 HAL_Delay (1000);
GPIOA->ODR &=~(1UL<<6);
HAL_Delay (1000);
GPIOA->ODR |=(1UL<<6);
HAL_Delay (1000);
GPIOA->ODR &=~(1UL<<6);
HAL_Delay (1000);

}
}