FPGA Lab

CEA Report

Name Class Enrollment Mail

Muhammad BEE-6C 01-133202-074 01-133202-
Ibrahim 074@student.bahria.edu.pk
Mahmood

Submitted To: Sir Talha Shakil

Project title: Implementation of 16 Bit processor on FPGA

Department of Electrical Engineering

Bahria School of Engineering and Applied
Sciences H-11 Campus, Islamabad
Abstract:

A processor is the logic circuitry that responds to and processes the basic instructions that drive a computer.
The processor is seen as the main and most crucial integrated circuitry (IC) chip in a computer, as it is
responsible for interpreting most of the computer’s commands. CPUs will perform most basic arithmetic,
logic, and I/O operations, as well as allocate commands for other chips and components running in a computer.

The implementation of a 16-bit processor on an FPGA can be done in a number of ways. One common
approach is to use a pre-designed processor core. There are a number of commercial and open-source
processor cores available, which can be implemented on an FPGA using a variety of tools.

Another approach is to design the processor core from scratch. This can be a more challenging task, but it can
also give the designer more control over the final implementation.

Once the processor core has been designed, it can be implemented on the FPGA using a hardware description
language (HDL) such as Verilog or VHDL. The HDL code is used to describe the functionality of the
processor in a way that can be understood by the FPGA synthesis tools.

The synthesis tools will then generate the physical circuit that implements the processor core. This circuit can
then be programmed into the FPGA using a programming tool.

Once the processor core has been programmed into the FPGA, it can be used to execute instructions. The
instructions are typically stored in a memory device, such as a ROM or RAM. The processor will fetch
instructions from memory, decode them, and execute them.

The execution of an instruction may involve a number of different operations, such as arithmetic operations,
logical operations, or memory accesses. The processor will use the ALU to perform arithmetic and logical
operations, and it will use the memory controller to access memory.

The processor will continue to execute instructions until it reaches the end of the program or until it is
interrupted by an external event.

16-bit processor:

To design a 16-bit processor with the given requirements, we can start with a simplified architecture using
minimal hardware resources. Here's a basic outline of the processor design:

Instruction Register (IR): This register stores the current instruction being executed.

Memory Address Register (MAR) and Memory Data Register (MDR): These registers are used to fetch
and store data from memory. MAR holds the memory address, and MDR stores the data being read from or
written to memory.

Arithmetic Logic Unit (ALU): The ALU performs arithmetic and logical operations.

General-Purpose Registers: We can include a small number of general-purpose registers to store temporary
data during processing.

Based on the provided instructions, we can define the opcode values for each instruction:

ADD: Opcode 00
SUBTRACT: Opcode 01
MOV: Opcode 10
COMPLIMENT: Opcode 11
Here's how the execution of each instruction would work:

ADD Instruction:

Fetch the instruction from memory into the IR.

Decode the opcode to identify the ADD instruction.
Fetch the two operands from the specified memory locations using MAR and MDR.
Perform addition using the ALU.
Store the result in a distinct memory location.

SUBTRACT Instruction:

Fetch the instruction from memory into the IR.

Decode the opcode to identify the SUBTRACT instruction.
Fetch the two operands from the specified memory locations using MAR and MDR.
Perform subtraction using the ALU.
Store the result in a distinct memory location.

MOV Instruction:

Fetch the instruction from memory into the IR.

Decode the opcode to identify the MOV instruction.
Fetch the data from the specified memory location or register using MAR and MDR.
Move the data to the desired memory location or register.

COMPLIMENT Instruction:

Fetch the instruction from memory into the IR.

Decode the opcode to identify the COMPLIMENT instruction.
Fetch the data from the specified memory location using MAR and MDR.
Compute the one's complement of the data.
Store the complement at a distinct memory location.

Verilog code:
Test bench:
The provided Verilog test bench code is used to verify the functionality of the processor module. Let's go
through the code and explain its different sections:

timescale 1ns / 1ps: This line defines the time units for the simulation.

module processor_tb;: This line declares the test bench module.

Signal Declarations: The following lines declare the input and output signals of the processor module:
reg clk;: Clock signal.
reg reset;: Reset signal.
reg[15:0] data_in;: Input data signal.
reg[15:0] addr1;: Address 1 signal.
reg[15:0] addr2;: Address 2 signal.
reg[1:0] opcode;: Opcode signal.
wire[15:0] data_out;: Output data signal.
wire[15:0] addr_out;: Output address signal.
Instantiation: The processor module is instantiated with the name dut, and its input and output signals are
connected to the corresponding signals in the test bench module.

Clock Generation: The always #5 clk = ~clk; line generates a clock signal with a 10 ns period, flipping its
value every 5 ns.

Initial Block: The initial block contains the test cases that simulate the behavior of the processor module:

clk = 1;: Sets the initial value of the clock signal to 1.

reset = 1;: Sets the initial value of the reset signal to 1.
#10 reset = 0;: After a delay of 10 ns, sets the reset signal to 0.
#10;: Waits for an additional delay of 10 ns.
The following lines set the input values for each test case:

opcode = 2'b00;: Sets the opcode for the ADD instruction.

data_in = 16'b0001001000110100;: Sets the input data for the ADD instruction.
addr1 = 16'b0000000000000000;: Sets the address 1 for the ADD instruction.
addr2 = 16'b0000000000000000;: Sets the address 2 for the ADD instruction.
#10;: Waits for a delay of 10 ns before proceeding to the next test case.
The same process is repeated for the remaining three instructions: SUBTRACT, MOV, and COMPLIMENT.

$finish;: Terminates the simulation.

Conclusion:

In this proposal, I have outlined my plan for implementing a 16-bit processor on an FPGA. The processor will
have the following features:

Four instructions: ADD, SUBTRACT, MOV, and COMPLIMENT

16-bit data path
Finite state machine control logic
The processor will be implemented using the Verilog hardware description language. The HDL code will be
written using the Vivado design suite.

The processor will be implemented on a Xilinx Spartan-7 FPGA. The FPGA will be programmed using the
Xilinx Vivado programming tool.
The processor will be tested using a variety of test cases. The test cases will cover all of the possible inputs
and outputs of the processor.

The processor will be evaluated using a variety of metrics, including its time complexity and its space
complexity.