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    VENKATRAMAN
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    This document contains code to set up a design environment and configure design-for-test (DFT) signals for a Verilog design of an up-down counter. It reads in the Verilog file, links the design, and sets up scan chain configuration. It then creates DFT signals like ScanClock, reset, and TestMode. Input and output ports are created and associated with ScanDataIn and ScanDataOut signals. A single scan chain is specified and DFT DRC is run.

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    This document contains code to set up a design environment and configure design-for-test (DFT) signals for a Verilog design of an up-down counter. It reads in the Verilog file, links the design, and sets up scan chain configuration. It then creates DFT signals like ScanClock, reset, and TestMode. Input and output ports are created and associated with ScanDataIn and ScanDataOut signals. A single scan chain is specified and DFT DRC is run.

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    32 views1 page

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    Uploaded by

    VENKATRAMAN
    This document contains code to set up a design environment and configure design-for-test (DFT) signals for a Verilog design of an up-down counter. It reads in the Verilog file, links the design, and sets up scan chain configuration. It then creates DFT signals like ScanClock, reset, and TestMode. Input and output ports are created and associated with ScanDataIn and ScanDataOut signals. A single scan chain is specified and DFT DRC is run.

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    of 1

    #set project_path /data/dft/scan_labs/week1_labs

    set search_path [list . $lib_path ]


    lappend search_path "/tools/libraries/28nm/SAED32_EDK/lib/stdcell_lvt/db_nldm
    /tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/db_nldm
    /tools/libraries/28nm/SAED32_EDK/lib/stdcell_hvt/db_nldm
    /tools/libraries/28nm/SAED32_EDK/tech/milkyway "
    set_app_var target_library {saed32lvt_ss0p95v125c.db saed32rvt_ss0p95v125c.db
    saed32hvt_ss0p95v125c.db}
    set_app_var link_library {* saed32lvt_ss0p95v125c.db saed32rvt_ss0p95v125c.db
    saed32hvt_ss0p95v125c.db}

    read_file inputs/counter_hack.vs -format verilog

    -format verilog
    set current_design up_down_counter

    link

    set_scan_configuration -style multiplexed_flip_flop


    compile -scan
    write_file -format verilog -output outputs/compile_scan.v

    set_dft_signal -view existing_dft -type ScanClock -port clk -timing [list 40 60]
    set_dft_signal -view existing_dft -type reset -port reset -active_state 0

    set_dft_signal -view existing_dft -type TestMode -port TestMode -active_state 1

    create_port -dir in SCAN_EN


    set_dft_signal -view spec -type ScanEnable -port SCAN_EN

    create_port -dir in SCAN_IN


    set_dft_signal -view spec -type ScanDataIn -port SCAN_IN

    create_port -dir out SCAN_OUT


    set_dft_signal -view spec -type ScanDataOut -port SCAN_OUT

    set_scan_path chain1 -view spec -scan_data_in SCAN_IN -scan_data_out SCAN_OUT


    set_scan_configuration -chain_count 1

    create_test_protocol
    dft_drc

    AUTOFIX__________________

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