Winter Semester 2022-2023

MVLD602L Lowpower IC Design

SLOT : A1 + TA1

Submitted to
School of Electronics Engineering
Vellore Institute of Technology

Submitted by
Name- ARTHI S
Register No. : 22MVD0133
M.Tech. VLSI Design
To obtain low power:
8-bit ring counter:

RTL Code:
module ring(in,clk,count);
output reg [7:0] count;
input clk,in;
always@(posedge clk)
begin
if(in)
count <=8'b10000000;
else
count <= {count[6:0],count[7]};
end
endmodule

script file:
script file

set_svf "logic.svf"

## Point to the new 32nm SAED libs

set DESIGN_REF_PATH "/home/synopsys/SAED32_EDK/lib"

set SEARCH_PATH " ./ \

${DESIGN_REF_PATH}/stdcell_rvt/db_nldm \
${DESIGN_REF_PATH}/stdcell_lvt/db_nldm \
${DESIGN_REF_PATH}/stdcell_hvt/db_nldm "

set LINK_LIBRARY_FILES "* \

${DESIGN_REF_PATH}/stdcell_rvt/db_nldm/saed32rvt_tt1p05v125c.d
b \
${DESIGN_REF_PATH}/stdcell_lvt/db_nldm/saed32lvt_tt1p05v125c.d
b \
${DESIGN_REF_PATH}/stdcell_hvt/db_nldm/saed32hvt_tt1p05v125c.d
b "

set TARGET_LIBRARY_FILES " \

${DESIGN_REF_PATH}/stdcell_rvt/db_nldm/saed32rvt_tt1p05v125c.d
b \
${DESIGN_REF_PATH}/stdcell_lvt/db_nldm/saed32lvt_tt1p05v125c.d
b \
${DESIGN_REF_PATH}/stdcell_hvt/db_nldm/saed32hvt_tt1p05v125c.d
b "

##############################################################
########
# Logical Library Settings
##############################################################
########
set_app_var search_path "$SEARCH_PATH"
set_app_var target_library "$TARGET_LIBRARY_FILES"
set_app_var link_library " $LINK_LIBRARY_FILES "
read_verilog count.v
current_design ring

set_operating_conditions tt1p05v125c
link
## Generating intermediate technology independet (GTECH)
design ###########
write_file -format verilog -output ./counter_gtech.vs
# check design quality
check_design
source ./con.sdc
check_timing
set_wire_load_model -name "8000"
set_wire_load_mode segmented
compile_ultra
report_area
report_power
report_timing
report_constraint -verbose
report_qor
report_clock_gating
change_names -rule verilog -hier
write -hierarchy -format verilog -output ./logic_opt.v
write_sdc ./logic.sdc

con.sdc:
reset_design
#virtual clock
create_clock -name clk -period 0.17 -waveform {0 0.085}
[get_ports clk]

#set_clock_latency -source -max 0.7 [get_clocks clk]

#set_clock_latency -max 0.3 [get_clocks clk]

#set_clock_uncertainty -setup 0.15 [get_clocks clk]

#set_clock_transition 0.12 [get_clocks clk]

#input delay

set_input_delay -max 0.01 -clock clk [get_ports in]

#ouput delay

set_output_delay -max 0.01 -clock clk [get_ports count]

Power:
Clock gated RTL Code:
module ring(in,clk,en,count);
output reg [7:0] count;
input clk,in,en;
wire d;
and(d,en,clk);
always@(posedge d)
begin
if(in)
count <=8'b10000000;
else
count <= {count[6:0],count[7]};
end
endmodule

Power:

Inference:
Hence for the above circuit generated the total power which as high power so here used clock gating
to reduce the power and obtained the reduction while clock gating to reduce high power to low power