An Introduction to DFT

Application Aspects | Topic 10 of 10

 “ Abstract
After knowing what is DFT, fault models, Pattern generation & typical DFT methods it is
necessary to understand how these ideas are actually implemented in designs; also what are
the different aspects which are required to incorporate DFT scan methods, how things are
analyzed, and most importantly what is done when a discrepancy is observed? there exist a
few terminologies which are essential for a design point of view and can be a criterion for
signing off a certain design while moving a design from RTL-Gate level representation to
physical design aspects; in this section, we’ll briefly try to understand the said things
1

Where We are?

Fault Models Pattern Generation DFT Techniques

• Stuck at faults • Pattern • Scan Insertion
• Bridging faults generation • Scanned
• Delay faults • Fault simulation Flipflop
• Switch level • ATPG • Boundary scan
• Pattern (JTAG)
faults
generation • BIST
algorithms

Extra topic: Application Aspects in DFT

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2

Recall of design hierarchy

Specs Floorplan
JTAG,
BIST
Placement Discard
RTL Design

CTS
Verification Match Accept
Pattern ?
Genaration Routing
Synthesis Pattern
Fabrication Fabrication application
Scan Fabrication
Insertion ATE

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3

Recall of design hierarchy

• We have discussed that DFT activity is done parallely with the design flow starting from
RTL design
• At the RTL stage, for a digital design, many circuitries are used (and inserted) which
essentially are active during only testing of a design and must unaffect the required

-
functionality when not tested (functional mode) for example,
If we use a scan-insertion mechnaism we must use a test mode clock in design which is active

-
only during test mode and not used during normal functioning, and hence a MUXing is needed
If a memory is used, a MBIST logic has to be created around the memory etc.
• When the gate level information is avaliable after synthesis there the internal scan chain
has to be inserted in the design and to operate the scan chain, there are a few supporting
designs has to be made arround it, simulteneously the appropriate patterns has to be
generated for the design during this stage

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4

DFT coverage Matrices

• At this stages, while sign-off at each flow of design, a few metrices are calculated to
check how much portion of a design is actually testable?
• Test Coverage: It is a measure of test quality of DFT, is the percentage of faults detected
from among all testable faults. This is the number of most concern when we consider the
testability of the design

ö逷  ( )= 100%
ö逷 X 逷 逷 G逷ö
逷 逷 G ö逷 X G逷ö− 逷ö逷 逷G G逷ö

• Fault Coverage: It consists of the percentage of faults detected from among all the faults
that the test patterns generated by the ATPG, as there could be some design elements
which are not a part of DFT analysis,
ö逷 X 逷 逷 G逷ö
G逷  ( ) = 100%
逷 逷 G ö逷 X G逷ö

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 5

Reading a DFT coverage report

Total No. of faults considered = 302778
Faults detected during simulation = 202752
Faults detected by using methods apart form Simulation
(includes test vetcors in scanned operations) = 75601
The
Faults untestable by tool = UU+TI+BL+RE =
percentage
4984+1076+12+1072 = 7144
of faults
that are Usually contents macros, black boxes whose internal logic
resolvable is not known to tool
278369 (202752 + 7560 + 16)
by the
= 100% = 94.16 %
(302778 − 7144)
ATPG
process
278369 (202752 + 7560 + 16)
= 100% = 91.93 %
302778
Note: TC is a better coverage matrics
Credit: vlsispace.wpcomstaging.com/

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6

DFT coverage Matrices

• Apart from TC & FC, there exist a few types of coverage analysis where the calculation of
coverage is done w.r.t type of faults, for example, stuck-at fault coverage or transitional fault
coverage
• Stuck-at fault coverage: It is percentage of stuck-at faults which are detected during
analysis
• Transitional fault coverage: It is percentage of transitional faults which are detected during
analysis
• Ideally, for a purely digital design the Stuck-at TC sould be 100 % and Transitional TC
should be very close to 100 % (but not exactly 100%)

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7

Coverage Improvement

• The coverage must be as high as possible, otherwise it signifies that there are a percentage
of out design which we can’t test (within the considered faults),and we have to assume that
design would work properly which is extremly dangeruous
• If a lower coverage is found we should try to improve by increasing the controlability &
observability of the design
• Every DFT tool usually reports the places of design which are non-testable by the tool, by
carefully oberving & providing controlablity or observabilty we can improve the coverage
metrices
• Coverage improvement can be achived by either Improving Observability at a net (usually
at input) or by Improving the Controllability at a cetain net (usually at input)

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8

Improving Observability

Un-observable point Observable flop addition

An observable flop can
increase the Test
Some Some coverage as it is able to
logic logic observe the un-
observable point during
Large Fan out
test mode by the
If a Blackbox & D Q
application of the test
not be able to
clock, also it is not going
insert internal-
Extra logic added test clock to alter the functionality as
scan chain can
reset during functional mode
lead to coverage
flop is not clocked
drop due to lack
of observability

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 9

Improving controlability
Controlable flop CF1 now can control the previously
uncontrolled input of gate G1 & will improve the
D Q Easily controlable coverge
F1 through internal-
functional clock D Q
scan chain
F1
functional clock
Some G1
logic Some G1
0
logic 1
Hard to control
Di
D Q
shift in Si

scan enable CF1

test clock Extra logic
added

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10

Stuck-at fault testing scenario

-
{1,1}
The pattern for testing SA/0 is {1,1}
1
Step1(Shift-in): put Se =1, signifying test
mode is on Insert serially {1,1} through SA/0
Sip Fire two pulses of test clock so that 1
G1
Y
{SFF1, SFF2} = {1,1}, also A & B input of B 0
1
gate G1 is {1,1}, but due to SA/0 output
remains 0 not 1

1
1
ClkT = test clock, ClkF = functional clock, Se = scan
enable
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11

Stuck-at fault testing scenario

-
{1,1}
The pattern for testing SA/0 is {1,1}
1
Step2 (Capture): Change Se =0,
signifying test mode is off and functional SA/0
mode is on, allow only 1 clock pulse of 0
G1
Y
functional clock, which allows Y output to B
1 0
be avaliable at SFF3

0
0

ClkT = test clock, ClkF = functional clock, Se = scan

enable
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12

Stuck-at fault testing scenario

-
{1,1}
The pattern for testing SA/0 is {1,1}
1
Step3 (shift-out): Change Se =1, allow
only 1 clock pulse of functional clock, SA/0
which allows Y output to be avaliable at 1
G1
Y
Di and give 1 test clock to get out the B
1 0
response of Y in the next serial flop, (but
here since Sop is our output, the
response can be recorded here without 1
1
test clock pulse) 1

ClkT = test clock, ClkF = functional clock, Se = scan

enable
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13

Delay fault testing

• Compared to static testing with the stuck-at fault model, delay fault testing requires a test pattern with

-
two parts-

-
The first part initializes the net, and
The second part launches a logic transition value at the net

• Now, after the launch the transition, after a specified time determined by the system clock speed, the
response is compared, in this case either of the following can happen:
1. If the circuit is having no fault, then the transition will propagate to the end of the path in time and the correct value
will be captured
2. else, a delay causes a slow propagation, the transition from launch to capture cell will be slow, an erroneous value
will be captured, and the defect will be detected

• For example, the pattern's launch event may propagate a 0-to-1 (rising edge) transition along a specific
path while holding all other conditions constant, If the “high” value was not detected at the capture point
in time, the path fails the test and is considered to have a “slow-to-rise” defect.

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14

Delay fault testing Scenario

We wanted to perform a delay testing on G1, and
for that we need two vectors V1 = {1,0} & V2 = {1},
let us assume the gate G1 is having a normal
propagation delay of 2 ns, and if the gate has a 1 A
delay fault it is able to produce output after 9ns, so G1
Y
we must check if the gate has produced output B
0
after 2ns and before 9ns
This requires a test clock which is fast enough to
sample the transitioning data atleast 2ns
1
The test mode clocks are typically operated within
1
40-100 MHz, which gives a time resulation of 10ns
ClkT = test clock, ClkF = functional clock, Se = scan
which is not suitable for checking a transition of
enable
2ns
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15

Delay fault testing Scenario

• For a time resulation of 2 ns we required a
{1,0,0}
Vector (v1)
clock of 500 MHz which can be created by
using a PLL inside the dice 1
• In this case the shifting operation of test vector
A
V1 is done by using a test clock which is nearly 1
G1
50-100 MHz of frequency Y
B
• The capture of response is always done by
0
using the high speed PLL clock in TD testing 0
but for the launching we have two options:
1. Launch-from-Capture 1
2. Launch-off-shift 1
ClkT = test clock, ClkF = functional clock, Se = scan
enable
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16

Launch-from-capture (LOC)
• The 1st vector (v1) is loaded through the scan path of
Vector (v2)
the design when the SE = 1,
• Then quickly SE switches to Functional mode where the Vector (v1)
2nd vector is launched with the help of functional clock,
so functional clock pulse 1 launches the 2nd vector and
the immediate functional clock pulse is also captures the
response from the CUT
• So, essentially 2 clocks are involved and in this case
there must me some mechanism to quickly switching
between two clocks
Test clock Functional Test clock
• Here, the 2nd vector has to be provided through Active clock Active Active
functional path, as lauch is done using functional clock

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17

Launch-off-shift (LOS)
• The 1st vector (v1) is loaded through the scan path of
Vector (v2)
the design when the SE = 1,
• But, the 2nd vector is also launched in test mode using Vector (v1)
the test clock, then quickly the SE changes to 0, i.e., in
functional mode and tries to capture the response
• So, in this case as well there must me some mechanism
to quickly switching between two clocks
• Here, the 2nd vector has to be provided through test
path, unlike the LOC mechanism, only capture is done
using functional clock
Test clock Test clock
Active Functional Active
clock Active
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18
LOC vs. LOS
LOC
• In LOC, V2 is generated by applying functional
clock from V1
• Launch transition is done on functional path
• LOC techniques uses sequential engine during
automatic test pattern generation (ATPG)
• Here, the controllability of launching transition at
fault site is less ( its depends on the functional
response of logic blocks to initialize vector)
• In LOC, after all slow clocks for loading there is
dead clock zone so, scan enable signal can
easily make transition from high to low
LOS
• V2 is shifted vector of V1.
• launch transition on shift path is very easy than
to launch transition on functional path
• LOS uses combination engine for ATPG
• Here, the fault activation path or scan path is
fully
• controllable from the input of scan chain
• LOS, fast scan enable signal must design to
make transition between two high speed clocks
means scan enable signal must operate at full
speed.
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19

Clock considerations | OCCC

• In a typical design the testing of transmission delays are usually

considered to be at-speed testing, where more than one clocks are
involved
• In SoC, there is something which is called an On Chip Clock controller
(OCC), which actually responsible for contolling functional clock, test
clock and other clocks (if exists) in different modes of operations
• On -chip clock controller is the logic inserted on the SOC for controlling
clocks during silicon testing for defects on ATE (Automatic test
Equipment)

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20

Clock considerations | OCCC

• OCC enables the AT-speed/Transition testing of the Logic by generating

two clock pulses at speed during capture phase. So OCC enables the
pulse control of the clock during Test mode through clock chain (chain
comprising all the OCC logic flops in a chain)
• Without OCC we need to provide At-speed pulses through Top pins
called PADS. But Pads has limitation in terms of maximum frequency they
can support. OCC on other hand uses internal PLL clock for generating 2
pulses for test.

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 21

A Basic OCCC

• We will be discussing about a very basic OCC design with the sole purpose of demonstrating
how it work. However industry standard OCCs are much more advanced and robust to ‘clock
glitches’ than the OCC discussed here

test_clk
shift register
scan_en scan_en
test_clk
pll_clk
pll_clk_en
cgc_clk_out pll_clk_en
pll_clk
PLL CGC cgc_clk_out
out_clk
out_clk
PLL = Phase Lock Loop, CGC = Clock Gating Cell
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 22

A Basic OCCC

• If we observe the waveform of out_clk it is clear that it resembles a LOC clocking where, launching
& capturing is done using a high speed clock (pll_clk here)
• Again this is just one example of OCCC structure & could be more advanced in modern day SoC

test_clk
shift register
scan_en scan_en
test_clk
pll_clk
pll_clk_en
cgc_clk_out pll_clk_en
pll_clk
PLL CGC cgc_clk_out
out_clk
out_clk
PLL = Phase Lock Loop, CGC = Clock Gating Cell
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23

Embedded Deterministic Test (EDT)

• Modern day SoC has multiple of operations with hundreds and even
thousands of I/O operations performed per dice of Si
• Hence, there we need huge ammount of patterns to be applied onto the
design and makes it difficult for the ATE to store them with limited
memory
• If the patterns are generated in a compressed manner from an ATE and
de-compressed before applying in DUT again, the responses are
compressed & send it to the ATE for comparison, that would solve the
stated problems

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24

Embedded Deterministic Test (EDT)

• Embedded deterministic test (EDT) is a manufacturing test paradigm that

combines the compression & de-compression techniques to reduce the
number of comparisons for a ATE (Automatic Test Equiepment), Test
compression involves compressing the amount of test data (both stimulus
and response) that must be stored on automatic test equipment (ATE) for
testing with a deterministic (automatic test pattern generation [ATPG]-
generated) test set. This is done by adding some additional on-chip
hardware before the scan chains to decompress the test stimulus coming
from the ATE and after the scan chains to compress the response going
to the ATE
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25

Embedded Deterministic Test (EDT)

• The EDT architecture consists
of an on-chip decompressor
located between the external
scan input ports and the
internal scan chains, as well as
an onchip selective compactor
inserted between the internal
scan chains and the external
scan output ports

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26

Embedded Deterministic Test (EDT)

• The compressor & de-compressor are extra design units that acts at the boundary of an SoC they can be
designed at RTL level
• As the compression is a reversiable process (unlike compaction used in BIST), it is relatively easy to get
scan lines form compressed patterns and vice versa
• Many schemes for compressing test cubes have been proposed. They can be broadly classified into the
three categories shown below:
1. Code-based schemes: These schemes use data compression codes to encode the test cubes
2. Linear-decompression-based schemes: These schemes decompress the data using only linear
operations (e.g., linear feedback shift registers [LFSRs] and exclusive-OR [XOR] networks)
3. Broadcast-scan-based schemes: These schemes are based on broadcasting the same value to
multiple scan chains

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27

Embedded Deterministic Test (EDT)

• Going into each type of scheme is beyond the scope of this introductory course, but details
can be found in the reference mentioned below
• However what different kind of schemes are there in each category can be shown in the
table below:
Code-based schemes Linear-decompression-based Broadcast-scan-based
schemes schemes
1. Dictionary Code (Fixed-to- 1. Combinational Linear 1. Broadcast Scan
Fixed), Decompressors 2. Illinois Scan
2. Huffman Code (Fixed-to- 2. Fixed-Length/variable 3. Multiple-Input Broadcast
Variable), length Sequential Linear Scan etc.
3. Run-Length Code (Variable- Decompressors etc.
to-Fixed) etc.

Ref:VLSI TEST PRINCIPLES AND ARCHITECTURES DESIGN FOR TESTABILITY, Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen, Publisher: Elsvier

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28

Summary

• We have seen what is coverage, how it helps us for better sign-off

• Methods of getting better coverages, testpoint insertion
• considered stuck-at & transition testing scenarios, at-speed testing
• LOC & LOS with their comparison
• Concept of OCCC & a typical example of it
• What is EDT & its block diagram

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29

References for DFT further study

• Book: VLSI TEST PRINCIPLES AND ARCHITECTURES DESIGN FOR

TESTABILITY, Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen,
Publisher- Elsvier
• Online Lecture series: VLSI Testing,offered by prof. James Chien-Mo Li,
http://cc.ee.ntu.edu.tw/~cmli/VLSItesting/
• Video Lecture:
1. DFT lecture series by Prof. Indranil Sengupta, IIT Kharagpur,
2. https://nptel.ac.in/courses/117/105/117105137/

• Web content: https://technobyte.org/design-for-testability-course-vlsi-dft/

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THANKS!
Any questions?
You can find me at linkedin.com/in/dastanmoy92/ or
tancarrer.ece@gmail.com