AXI 3 VPlan DOC

AXI-3 VIP V-Plan
v0.1
AIonsi
Author:Chitaranjan Nayak
Siddeshwar Shenoy
Date: 22/12/2021
1 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

AXI-3 VIP V-Plan
Version Information
Sl.N Versio Date comment Issue Change Author

o n
1. v0.1 22.12.2021 Initial AXI-3 V-plan - - Chitaranjan/
Siddeshwar

Table of Contents:
Sl. No Page No
1. Stimulus. 7
1.1.Direct Stimulus. 7
1.2.Random Stimulus. 7
1.3.Constrain random stimulus. 7
2. Interface. 10
2.1 axi_interface 11
3. Features. 13
3.1Reset Features. 13
3.1.1. Start of simulation reset 13
3.1.2. On the fly reset 13
3.2 Burst-based transactions with only start address 14
3.2.1. Fixed burst 14
3.2.2. Incrementing burst 15
3.2.3. Wrapping burst 15
3.3 Separate read and write data channels 16
3.4 Multiple outstanding addresses 17
3.5 Out-of-order transaction completion 18
3.6 Unaligned data transfers using byte strobes 18
3.7 Atomic operations 19
3.7.1. Normal access 20
3.7.2. Exclusive access 20
3.7.3. Locked access 21
3.8 Protection unit support 22
3.9 System cache support 22
3.9.1. Bufferable (B) bit, ARCACHE[0] and AWCACHE[0] 23
3.9.2. Cacheable (C) bit, ARCACHE[1] and AWCACHE[1] 23
3.9.3. Read Allocate (RA) bit, ARCACHE[2] and AWCACHE[2] 24

3.9.4. Write Allocate (WA) bit, ARCACHE[3] and AWCACHE[3] 24
3.10 Siginaling Response 25
3.10.1. OKAY 25
3.10.2. EXOKAY 26
3.10.3. SLVERR 26
3.10.4. DECERR 26
4. TB Architecture. 28
4.1. TB Block. 28
4.2. Architecture Components. 29
4.2.1. Axi Master Agent 29
4.2.1.1. Axi Master driver 29
4.2.1.2. Axi Master monitor 29
4.2.1.3. Axi Master sequencer 29
4.2.1.4. Axi Master sequence 29
4.2.2. Axi Slave Agent 29
4.2.2.1. Axi Slave driver 29
4.2.2.2. Axi Slave monitor 30
4.2.2.3. Axi Slave sequencer 30
4.2.2.4. Axi Slave sequence 30
4.2.3. Rst Agent 30
4.2.3.1.rst driver 30
4.2.3.2. rst monitor 30
4.2.3.3. rst sequencer 31
4.2.3.4. rst sequence 31
4.2.4. clock Agent 31
4.2.4.1. clock driver 31
4.2.4.2. clock monitor 31
4.2.4.3. clock sequencer 31
4.2.4.4. clock sequence 31

4.2.5. ENV 31
4.2.5.1. Environment 31
4.2.5.2. Scoreboard 31
4.2.6. Test 31
4.2.7. Top 31
4.2.6.1. Interface 31
4.2.6.2. Test 32
4.2.6.3.Assertion 32
5. Checker. 32
5.1. Directed check. 32
5.1.1. Synchronous check. 32
5.1.2. Asynchronous check. 32
5.2. Reference logic check. 33
5.2.1. Synchronous check. 33
5.2.2. Asynchronous check. 33
6. Functional Coverage. 34
6.1. covergroup axi_master_cg 34
6.1.1.coverpoint AWID_cvg::AWID 34
6.1.2 coverpoint AWADDR_cvg::AWADDR 34
6.1.3.coverpoint AWLEN_cvg::AWLEN 34
6.1.4.coverpoint AWSIZE_cvg::AWSIZE 34
6.1.5.coverpoint AWBURST_cvg::AWBURST 34
6.1.6 coverpoint AWLOCK_cvg::AWLOCK 34
6.1.7 coverpoint AWCACHE_cvg::AWCACHE 34
6.1.8.coverpoint AWPROT_cvg::AWPROT 34
6.1.9 coverpoint WID_cvg::WID 34
6.1.10.coverpoint WDATA_cvg::WDATA 34
6.1.11. coverpoint WSTRB_cvg::WSTRB 34
6.1.12.coverpoint ARID_cvg::ARID 34

6.1.13 coverpoint ARADDR_cvg::ARADDR 34
6.1.14 coverpoint ARLEN_cvg::ARLEN 34
6.1.15.coverpoint ARSIZE_cvg::ARSIZE 34
6.1.16 coverpoint ARBURST_cvg::ARBURST 34
6.1.17.coverpoint ARLOCK_cvg::ARLOCK 34
6.1.18.coverpoint ARCACHE_cvg::ARCACHE 34
6.1.19.coverpoint ARPROT_cvg::ARPROT 34
6.1.20 coverpoint reset_cvg::reset 34
6.1.21 cross awburst_awlen_awsize 34
6.1.22 cross arbusrst_arlen_arsize 34
6.2. covergroup axi_slave_cg 34
6.2.1.coverpoint BID_cvg::BID 34
6.2.2. coverpoint BRESP_cvg::BRESP 34
6.2.3. coverpoint RID_cvg::RID 37
6.2.4.coverpoint RDATA_cvg::RDATA 37
6.2.5.coverpoint RRESP_cvg::RRESP 37
7. Assertion. 38

1.Stimulus
 Stimulus are the input data which we need to pass through sequence or
transaction class, to the driver class to drive it to DUT.
 VIP can pass either stimulus directly through sequence or it can generate
random stimulus through transaction class or it can have constraint to generate
random stimulus.
 So, based on all the above conditions we have three types of stimulus.
1.1 Direct stimulus

1.2 Random stimuls
1.3 Constraint Random stimuls
1.1 Direct stimulus(yes required)

 Here reset,AWVALID,AWREADY,WVALID,WREADY,WLAST,
BVALID,BREADY,ARVALID,ARREADY,RLAST,RVALID,
RREADY siginals are the direct stimuls.
 Signal Declaration:-
◦ bit ARESETn
◦ bit AWVALID
◦ bit AWREADY
◦ bit WVALID,
◦ bit WREADY,
◦ bit WLAST
◦ bit BVALID
◦ bit BREADY
◦ bit ARVALID,
◦ bit ARREADY,
◦ bit RLAST,
◦ bit RVALID,
◦ bit RREADY
1.2 Random stimuls(yes required)

 Here ARCACHE,AWCACHE, WDATA, RDATA, WSTRB is the
random stimuls.
rand bit [31:0] WDATA[];
rand bit [3:0] WSTRB[];
rand bit [31:0] RDATA;

rand bit [3:0] AWCACHE;
rand bit [3:0] ARCACHE;
1.3 Constraint Random stimuls(yes required)
 Constraint random stimuls are used to drive specific random data.
 Here AWID,AWADDR,AWLEN,AWSIZE,AWBURST,AWLOCK,
AWPROT,WID,BID,BRESP,ARID,ARADDR,ARLEN,
ARSIZE,ARBURST,ARLOCK,ARPROT,RID,RRESP
constraint random stimuls.
◦ rand bit [3:0] AWID;
◦ rand bit [31:0] AWADDR;
◦ rand bit [3:0] AWLEN;
◦ rand bit [2:0] AWSIZE;
◦ rand bit [1:0] AWBURST;
◦ rand bit [1:0] AWLOCK;
◦ rand bit [2:0] AWPROT;
◦ rand bit [2:0] WID;
◦ rand bit [3:0] BID;

◦ rand bit [1:0] BRESP;
◦ rand bit [3:0] ARID;

◦ rand bit [31:0] ARADDR;
◦ rand bit [3:0] ARLEN;
◦ rand bit [2:0] ARSIZE;
◦ rand bit [1:0] ARBURST;
◦ rand bit [1:0] ARLOCK;
◦ rand bit [2:0] ARPROT;
◦ rand bit [3:0] RID;
◦ rand bit [1:0] RRESP;
 Constraint:-
◦ constraint AW_ADDR_SIZE{AWSIZE inside {[0:7]};
AWADDR inside {[1:4090]};}
◦ constraint AR_ADDR_SIZE{ARSIZE inside {[0:7]};
ARADDR inside {[1:4090]};}
◦ constraint
BRUST_S{AWBURST!=2'b11; ARBURST!=2'b11;}
◦ constraint len_same{AWLEN==ARLEN;}

◦ constraint AW_LEN_VAL {
solve AWBURST before AWLEN;
if(AWBURST == 2'b00)
AWLEN inside { 0, 1 };
else if(AWBURST == 2'b10)
AWLEN inside {1, 3, 7, 15 };}
◦ constraint AR_LEN_VAL {
solve ARBURST before ARLEN;
if(ARBURST == 2'b00)
ARLEN inside { 0, 1 };
else if(ARBURST == 2'b10)
ARLEN inside { 1, 3, 7, 15 };}
◦ constraint lD_SAME{AWID == WID;}
◦ constraint wdata_size{WDATA.size==AWLEN+1'b1;}
◦ constraint wstrb_size{WSTRB.size==AWLEN+1'b1;}
◦ constraint ATOMIC_ACESS{ARLOCK!=2'b11;
AWLOCK!=2'b11;}
◦ constraint PROTECTION_S{AWPROT inside
{1,2,3};}
◦ constraint PROTECTION_S1{ARPROT inside
{1,2,3};}

2.Interface
The followings are Interface Siginals:
bit ARESETn;
bit ACLK;
logic [3:0]AWID;
logic [31:0]AWADDR;
logic [3:0]AWLEN;
logic [2:0]AWSIZE;
logic [1:0]AWBURST;
logic AWVALID;
logic AWREADY;
logic [3:0]WID;
logic [31:0]WDATA;
logic [3:0]WSTRB;
logic WLAST;
logic WVALID;
logic WREADY;
logic [3:0]BID;
logic [1:0]BRESP;
logic BVALID;
logic BREADY;
logic [3:0]ARID;
logic [31:0]ARADDR;
logic [3:0]ARLEN;
logic[2:0]ARSIZE;
logic[1:0]ARBURST;
logic ARVALID;
logic ARREADY;
logic [3:0]RID;
logic [31:0]RDATA;
logic [1:0]RRESP;
logic RLAST;

logic RVALID;
logic RREADY;
 Here we required one inteface i.e AXI_if interface.

 Inside the interface we need clocking block and modport for AXI driver and
monitor.
2.1 AXI_if interface

Siginals to DUT
 Inputs to DUT
◦ ARESETn;
◦ ACLK;
◦ [3:0]AWID;
◦ [31:0]AWADDR;
◦ [3:0]AWLEN;
◦ [2:0]AWSIZE;
◦ [1:0]AWBURST;
◦ AWVALID;
◦ [3:0]WID;
◦ [31:0]WDATA;
◦ [3:0]WSTRB;
◦ WLAST;
◦ WVALID;
◦ BREADY;
◦ [3:0]ARID;
◦ [31:0]ARADDR;
◦ [3:0]ARLEN;
◦ [2:0]ARSIZE;
◦ [1:0]ARBURST;
◦ ARVALID;
◦ RREADY;
 Outputs from DUT

◦ AWREADY;
◦ WREADY;
◦ [3:0]BID;
◦ [1:0]BRESP;
◦ BVALID;
◦ ARREADY;

◦ [3:0]RID;
◦ [31:0]RDATA;
◦ [1:0]RRESP;
◦ RLAST;
◦ RVALID;
Siginals to TB
 Output from TB
◦ ACLK;
◦ ARESETn;
◦ [3:0]AWID;
◦ [31:0]AWADDR;
◦ [3:0]AWLEN;
◦ [2:0]AWSIZE;
◦ [1:0]AWBURST;
◦ AWVALID;
◦ [3:0]WID;
◦ [31:0]WDATA;
◦ [3:0]WSTRB;
◦ WLAST;
◦ WVALID;
◦ BREADY;
◦ [3:0]ARID;
◦ [31:0]ARADDR;
◦ [3:0]ARLEN;
◦ [2:0]ARSIZE;
◦ [1:0]ARBURST;
◦ ARVALID;
◦ logic RREADY;
▪ Input to TB
◦ AWREADY;
◦ WREADY;
◦ [3:0]BID;
◦ [1:0]BRESP;
◦ BVALID;
◦ ARREADY;
◦ [3:0]RID;
◦ [31:0]RDATA;

◦ [1:0]RRESP;
◦ RLAST;
◦ RVALID;
3.Features
In smart register IP, the following are the features
3.1. Reset.
3.2. Burst-based transactions with only start address.
3.3 Separate read and write data channels.
3.4 Multiple outstanding addresses.
3.5 Out-of-order transaction completion.
3.6 Unaligned data transfers using byte strobes.
3.7 Atomic operations.
3.8 Protection unit support.
3.9 System cache support.
3.10 Siginaling Response
3.1 Reset
 ARESETn is active low reset,when ARESETn=0 all siginals goes zero.
 In this IP, reset have two feature
3.1.1. Start of simulation reset
3.1.2. On the fly reset
3.1.1. Start of simulation reset

 Description
At the start of simulation when ARESETn is zero, all siginals should be zero.
 Steps of implmentation
Steps-1:
At the start of simulation apply ARESETn=0;
Steps-2:-
 master interface must drive ARVALID, AWVALID, and WVALID
LOW
 slave interface must drive RVALID and BVALID LOW.
 All other signals can be driven to any value.

3.1.2. On the fly reset
 Description
When we are driving the stimuls that time we need to drive the reset and we
need to check all siginals should be zero or not.
Steps-1:
Drive stimuls,after that drive ARESETn=0;
Steps-2:-
• master interface must drive ARVALID, AWVALID, and WVALID LOW
• slave interface must drive RVALID and BVALID LOW.
• All other signals can be driven to any value.
3.2 Burst-based transactions with only start address
 AIX3 supports 3 types of burst operation.
3.2.1 Fixed burst
3.2.2 Incrementing burst
3.2.3 Wrapping burst
3.2.1 Fixed burst

 Description
In a fixed burst, the address remains the same for every transfer in the burst.
This burst type is for repeated accesses to the same location such as when
loading or emptying a peripheral FIFO.
ARBURST[1:0]/
AWBURST[1:0] Burst type Description Access
b00 FIXED Fixed-address burst FIFO-type
Steps-1:
For write
Apply AWBURST=’b0; AWLOCK=’b0; AWID,AWADDR,AWLEN,
AWSIZE, AWLOCK,AWCACHE,AWPROT,WID,WDATA,WSTRB are
constraint random data
For Read
Apply ARBURST=0; ARLOCK=’b0 ARID,ARADDR,ARLEN,

ARSIZE, ARBURST,ARLOCK,ARCACHE,ARPROT are constraint
random data.
Steps-2:-
For write
Check all the write chhannle siginals in slave,weather it same or not.
For Read
Check all the read chhannle siginals in slave,weather it same or not.
3.2.2 Incrementing burst

 Description
In an incrementing burst, the address for each transfer in the burst is an
increment of the previous transfer address. The increment value depends on
the size of the transfer. For example, the address for each transfer in a burst
with a size of four bytes is the previous address plus four.
ARBURST[1:0]/
b01 INCR Incrementing-address burst Normal
sequential
memory
Steps-1:
For write
Apply AWBURST=’b01;AWLOCK=’b0; AWID,AWADDR,AWLEN,
AWSIZE, AWLOCK,AWCACHE,AWPROT,WID,WDATA,WSTRB are
For Read
Apply ARBURST=’b01;ARLOCK=’b0; ARID,ARADDR,ARLEN,
ARSIZE,ARBURST,ARLOCK,ARCACHE,ARPROT are constraint
random data.
Steps-2:-
For write

For Read
3.2.3 Wrapping burst

 Description
A wrapping burst is similar to an incrementing burst, in that the address for
each transfer in the burst is an increment of the previous transfer address.
However, in a wrapping burst the address wraps around to a lower address
when a wrap boundary is reached. The wrap boundary is the size of each
transfer in the burst multiplied by the total number of transfers in the burst.
Two restrictions apply to wrapping bursts:

the start address must be aligned to the size of the transfer
the length of the burst must be 2, 4, 8, or 16.
ARBURST[1:0]/
b10 WRAP Incrementing-address Cache line
burst that wraps to a lower
address at the wrap boundary
Formulas for determining the address and byte lanes of transfers within a
burst. The formulas use the following variables:
Start_Address: The start address issued by the master.

Number_Bytes: The maximum number of bytes in each data
transfer.
Data_Bus_Bytes: The number of byte lanes in the data bus.
Aligned_Address: The aligned version of the start address.
Burst_Length: The total number of data transfers within a burst.
Address_N: The address of transfer N within a burst. N is an
integer from 2-16.
Wrap_Boundary: The lowest address within a wrapping burst.
Lower_Byte_Lane: The byte lane of the lowest addressed byte of a
transfer.
Uper_Byte_Lane: The byte lane of the highest addressed byte of a
transfer.
INT(x): The rounded-down integer value of x.

Use these equations to determine addresses of transfers within a burst:
Start_Address = ADDR
Number_Bytes = 2 SIZE
Burst_Length = LEN + 1
Aligned_Address = (INT( Start_Address / Number_Bytes ) ) x Number_Bytes
Use this equation to determine the address of the first transfer in a burst:
Address_1 = Start_Address .
Use this equation to determine the address of any transfer after the first
transfer in a burst:
Address_N = Aligned_Address + (N – 1) x Number_Bytes .
For wrapping bursts, the Wrap_Boundary variable is extended to account for

the wrapping
boundary:
Wrap_Boundary = ( INT ( Start_Address / ( Number_Bytes x Burst_Length )))

x ( Number_Bytes x Burst_Length ).
If Address_N = Wrap_Boundary + ( Number_Bytes x Burst_Length ), use this
equation:
Address_N = Wrap_Boundary .
Use these equations to determine which byte lanes to use for the first transfer
in a burst:
Lower_Byte_Lane = Start_Address - ( INT ( Start_Address /
Data_Bus_Bytes ))x Data_Bus_Bytes
Upper_Byte_Lane = Aligned_Address + ( Number_Bytes - 1) -

( INT ( Start_Address / Data_Bus_Bytes )) x Data_Bus_Bytes .
Use these equations to determine which byte lanes to use for all transfers after
the first
transfer in a burst:
 Lower_Byte_Lane = Address_N – ( INT ( Address_N / Data_Bus_Bytes
))
 x Data_Bus_Bytes
 Upper_Byte_Lane = Lower_Byte_Lane + Number_Bytes – 1.
 Data is transferred on:


 DATA[(8 x Upper_Byte_Lane ) + 7 : (8 x Lower_Byte_Lane )].

Steps-1:
For write
Apply AWBURST=’b10;AWLOCK=’b0; AWID,AWADDR,AWLEN,
AWSIZE,AWLOCK,AWCACHE,AWPROT,WID,WDATA,WSTRB are
/// aligned address
For Read
Apply ARBURST=’b10; ARLOCK=’b0;ARID,ARADDR,ARLEN,
random data.
Steps-2:-
For write
For Read
3.3 Separate read and write data channels
 AXI3 have separate read and write channels.
 Description
Master have the capability to do separete read and write.Master also do both
read and write operaion at same time.
Steps-1:
For write
Apply ARESETn=’b1;AWLOCK=’b0; AWID,AWADDR,AWLEN,
AWSIZE,AWLOCK,AWCACHE,AWPROT,WID,WDATA,WSTRB are
For Read
Apply ARESETn=’b1;ARLOCK=’b0; ARID,ARADDR,ARLEN,

random data.
Steps-2:-
For write
For Read
3.4 Multiple outstanding addresses
 The ability to issue multiple outstanding addresses means that masters can
issue transaction addresses without waiting for earlier transactions to complete.
This feature can improve system performance because it enables parallel
processing of transactions,.
 Description
The transactions which are yet to be completed are called outstanding
transactions.for example: Let us say we have 10 Write's initiated from Master
component. Out of 10, only 3 of them have received OKAY response from
slave.In such case, the rest of the 7 writes whose responses are yet to be
received are called outstanding transactions.
Steps-1:
Initiate 10-20 writes/reads.
Steps-2:-
Check the BRESP,BID for write response.(if it got 4-5 response and remening
are pending it is outstanding response).
3.5 Out-of-order transaction completion
 The ability to complete transactions out of order means that transactions to

faster memory regions can complete without waiting for earlier transactions to
slower memory regions. This feature can also improve system performance
because it reduces the effect of transaction latency.

 Description
Steps-1:
Initiate 3 write and read with different ID ex:-A11,A21,A31
Steps-2:-
Check the WDATA,RDATA order.
3.6 Unaligned data transfers using byte strobes

 The AXI protocol uses burst-based addressing, which means that each
transactionconsists of a number of data transfers. Typically, each data transfer
is aligned to the size of the transfer. For example, a 32-bit wide transfer is
usually aligned to four-byte boundaries. However, there are times when it is
desirable to begin a burst at an unaligned address.

 Description
For any burst that is made up of data transfers wider than one byte, it is
possible that the first bytes that have to be accessed do not align with the
natural data width boundary.For example, a 32-bit (four-byte) data packet that
starts at a byte address of 0x1002 is not aligned to a 32-bit boundary.
Steps-1:
Apply ADDR= Unaligned address, //siginals
Steps-2:-
check first transfer is unaligned and rest are aligned.
3.7 Atomic operations
 To enable the implementation of atomic access primitives, the ARLOCK[1:0]

AWLOCK[1:0] signal provides exclusive access and locked access. Below
shows the encoding of the ARLOCK[1:0] and AWLOCK[1:0] signals.
Atomic access encoding

ARLOCK[1:0]/
AWLOCK[1:0] Access type
b00 -------------------Normal access
b01--------------------Exclusive access
b10--------------------Locked access
b11--------------------Reserved
 Atomic access are 3 types

3.7.1 Normal access
3.7.2 Exclusive access
3.7.3 Locked access
3.7.1 Normal access

 Description
When ARLOCK/ AWLOCK is equal to zero AXI will normal operation.
Steps-1:
Apply ARLOCK/ AWLOCK=0, other siginals are constraint random
Steps-2:-

Check the write and read response it should be normal response.
3.7.2 Exclusive access
 Description
The exclusive access mechanism enables the implementation of semaphore
type operations without requiring the bus to remain locked to a particular
master for the duration of the operation. The advantage of exclusive access is
that semaphore type operations do not impact either the critical bus access
latency or the maximum achievable bandwidth.
The ARLOCK[1:0] or AWLOCK[1:0] signal selects exclusive access, and

the RRESP[1:0] or BRESP[1:0] signal indicates the success or failure of the
exclusive access.
Steps-1:
Apply ARLOCK/AWLOCK=1,
Steps-2:-
Do an exclusive read from an address location. All read chhannle siginals
are constraint random siginals.
Steps-3:-
At some later time, the master attempts to complete the exclusive operation by
performing an exclusive write to the same address location.All write
chhannle siginals are constraint random siginals.
Steps-4:-
check the RRESP[1:0] or BRESP[1:0].
3.7.3 Locked access

 Description

When the ARLOCK[1:0] or AWLOCK[1:0] signals for a transaction show
that it is a locked transfer then the interconnect must ensure that only that
master is allowed access to the slave region until an unlocked transfer from the
same master completes. The arbiter within the interconnect is used to enforce
this restriction.
When a master starts a locked sequence of either read or write transactions it
must ensure that it has no other outstanding transactions waiting to
complete.
Steps-1:
Apply ARLOCK/AWLOCK=’b10,others are constraint random.
Steps-2:-
apply lock sequence,do the operation to paticular slave address from master-
1.
Steps-3:-
After some time do the operation to same slave address from master-2.
Steps-4:-
Check master-2 should not get the access to that slave address.
3.8 Protection unit support

Special this protection support done by software unit,to control this protection unit we need extra
hardware
 Description
To support complex system designs, it is often necessary for both the
interconnect and other devices in the system to provide protection against
illegal transactions.
Protection encoding
ARPROT[2:0]
AWPROT[2:0] Protection level
0 1 = privileged access
0 = normal access
1 1 = nonsecure access
0 = secure access

2 1 = instruction access
0 = data access
3.9 System cache support

Support for system level caches and other performance enhancing components
is provided by the use of the cache information signals, ARCACHE and
AWCACHE.These signals provide additional information about how the
transaction can be processed.The ARCACHE[3:0] or AWCACHE[3:0] signal
supports system-level caches by providing the bufferable, cacheable, and
allocate attributes of the transaction.
3.9.1 Bufferable (B) bit, ARCACHE[0] and AWCACHE[0]

3.9.2 Cacheable (C) bit, ARCACHE[1] and AWCACHE[1]
3.9.3 Read Allocate (RA) bit, ARCACHE[2] and AWCACHE[2]
3.9.4 Write Allocate (WA) bit, ARCACHE[3] and AWCACHE[3]
Cache encoding
ARCACHE[3:0]
AWCACHE[3:0]
WA RA C B Transaction attributes
0 0 0 0 Noncacheable and nonbufferable
0 0 0 1 Bufferable only
0 0 1 0 Cacheable, but do not allocate
0 0 1 1 Cacheable and bufferable, but do not allocate
0 1 0 0 Reserved
0 1 0 1 Reserved
0 1 1 0 Cacheable write-through, allocate on reads only
0 1 1 1 Cacheable write-back, allocate on reads only
1 0 0 0 Reserved
1 0 0 1 Reserved
1 0 1 0 Cacheable write-through, allocate on writes only
1 0 1 1 Cacheable write-back, allocate on writes only
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Cacheable write-through, allocate on both reads andwrites
1 1 1 1 Cacheable write-back, allocate on both reads and writes
3.9.1 Bufferable (B) bit, ARCACHE[0] and AWCACHE[0]

 Description
When this bit is HIGH, it means that the interconnect or any component
can delay the transaction reaching its final destination for an arbitrary
number of cycles. This is usually only relevant to writes.
Steps-1:
Apply ARCACHE/AWCACHE=’4b0001,all siginals are constraint
random
Steps-2:-
check weather the transaction reaching its final destination with an arbitrary
number of cycles dalye or not.
3.9.2 Cacheable (C) bit, ARCACHE[1] and AWCACHE[1]
 Description
When this bit is HIGH, it means that the transaction at the final
destination does not have to match the characteristics of the original
transaction.
For writes this means that a number of different writes can be merged
together.
For reads this means that a location can be pre-fetched or can be fetched
just once for multiple read transactions.
To determine if a transaction should be cached this bit should be used in
conjunction with the Read Allocate (RA) and Write Allocate (WA) bits.
Steps-1:
Apply ARCACHE/AWCACHE=constraint random ,all siginals are
constraint random
Steps-2:-
For writes,check number of different writes can be merged together or not.
For reads,check that a location can be pre-fetched or can be fetched or not.
3.9.3 Read Allocate (RA) bit, ARCACHE[2] and AWCACHE[2]

 Description
When the RA bit is HIGH, it means that if the transfer is a read and it
misses in the cache then it should be allocated.
The RA bit must not be HIGH if the C bit is low.

Steps-1:
constraint random
Steps-2:-
check for read, weather the cheche is allocated or not.
3.9.4 Write Allocate (WA) bit, ARCACHE[3] and AWCACHE[3]

 Description
When the WA bit is HIGH, it means that if the transfer is a write and it
misses in the cache then it should be allocated.
The WA bit must not be HIGH if the C bit is low.
Steps-1:
constraint random
Steps-2:-
check for write, weather the cheche is allocated or not.
3.10 Response Signaling

The AXI protocol allows response signalling for both read and write transactions. For
read transactions the response information from the slave is passed alongside the
read data itself, however for writes the response information is conveyed along the
write response channel.
The AXI protocol responses are:

3.10.1 OKAY
3.10.2 EXOKAY
3.10.3 SLVERR
3.10.4 DECERR
RRESP[1:0]
BRESP[1:0] Response Meaning
b00 OKAY Normal access okay indicates if a normal access has been
successful. Can also indicatean exclusive access failure.

b01 EXOKAY Exclusive access okay indicates that either the read or write
portion of an exclusive access has been successful.
b10 SLVERR Slave error is used when the access has reached the slave
successfully, but the slavewishes to return an error condition to
the originating master.
b11 DECERR Decode error is generated typically by an interconnect
component to indicate that there is no slave at the transaction
address.
3.10.1 OKAY
 Description
The OKAY response indicates:
the success of a normal access
the failure of an exclusive access
an exclusive access to a slave that does not support exclusive access.
OKAY is the response for most transactions.

Steps-1:
Apply simple tranasction(all siginals are constraint random).
Steps-2:-
check BRESP/RRESP, it will give OKAY.
3.10.2 EXOKAY
 Description
The EXOKAY response indicates the success of an exclusive access.
Steps-1:
Apply ARLOCK/AWLOCK=1
Steps-2:-
check BRESP/RRESP, it will give EXOKAY
3.10.3 SLVERR
 Description
The SLVERR response indicates an unsuccessful transaction.
slave error conditions are:

 FIFO/buffer overrun or underrun condition
 unsupported transfer size attempted
 write access attempted to read-only location

 timeout condition in the slave
 access attempted to an address where no registers are present
 access attempted to a disabled or powered-down function.
To simplify system monitoring and debugging, it is recommended that error

responses are used only for error conditions and not for signaling normal,
expected events.
Steps-1:
Apply any above condition.(stimulus should be constraint random)
Steps-2:-
check BRESP/RRESP, it will give SLVERR
3.10.4 DECERR
 Description
In a system without a fully-decoded address map, there can be addresses at
which there are no slaves to respond to a transaction. In such a system, the
interconnect must provide a suitable error response to flag the access as illegal
and also to prevent the system from locking up by trying to access a
nonexistent slave.
Steps-1:
Apply out of bound address.(siginals are constraint random)
Steps-2:-
check BRESP/RRESP, it will give DECERR

4. TB Architecture
Tb architecture provides all the information about vip componets.
4.1 TB Block

N:B:-
In this VIP clock agent and reset agent are not consider
4.2 Architecture Components

The componets are
4.2.1. Master Agent
4.2.2. Slave Agent
4.2.3. Rst Agent
4.2.4 clock Agent
4.2.5. ENV
4.2.6. Test
4.2.7. Top
4.2.1.Axi Master Agent

The following componets are present inside the input Agent
4.2.1.1. Axi Master driver
4.2.1.2. Axi Master monitor
4.2.1.3. Axi Master sequencer
4.2.1.4. Axi Master sequence
4.2.1.1. Axi Master driver

 Master driver is used drive all input siginal to DUT.
4.2.1.2. Axi Master monitor

 Master monitor will collect all the input siginal from DUT and send to
scorboard through tlm analysis fifo.
4.2.1.3. Axi Master sequencer

 Master sequencer send the randomize data to Master driver.
4.2.1.4. Axi Master sequence

 Master sequence will randomize the input siginal and give to
seq_item_port.
4.2.2. Axi Slave Agent

The following componets are present inside the input Agent
4.2.1.1. Axi Slave driver
4.2.1.2. Axi Slave monitor
4.2.1.3. Axi Slave sequencer
4.2.1.4. Axi Slave sequence
4.2.1.1. Axi Slave driver

 Slave driver is used drive all input siginal to DUT.
4.2.1.2. Axi Slave monitor
 Slave monitor will collect all the output siginal from DUT and send to
4.2.1.3. Axi Slave sequencer

 slave sequencer send the randomize data to slave driver.
4.2.1.4. Axi Slave sequence

 Slave sequence will randomize the input siginal and give to seq_item_port.
4.2.3. rst Agent

The following componets are present inside the Rst Agent
4.2.3.1.rst driver
4.2.3.2. rst monitor
4.2.3.3. rst sequencer
4.2.3.4. rst sequence
4.2.3.1. rst driver

 rst driver is used drive the rst siginal to DUT.
4.2.3.2. rst monitor

 rst monitor will collect the rst siginal from DUT and send to scorboard
through tlm analysis fifo.
4.2.3.3. rst sequencer

 rst sequencer send the randomize data to rst driver.
4.2.3.4. rst sequence

 rst sequence will randomize the rst siginal and give to seq_item_port.
4.2.4. clock Agent
The following componets are present inside the Rst Agent

4.2.4.1.clock driver
4.2.4.2. clock monitor
4.2.4.3. clock sequencer
4.2.4.4. clock sequence
4.2.3.1. clock driver

 clock driver is used drive the clock siginal to DUT.
4.2.3.2. clock monitor
 clock monitor will collect the clock siginal from DUT and send to
4.2.3.3. clock sequencer
 clock sequencer send the randomize data to rst driver.
4.2.3.4. clock sequence
 clock sequence will randomize the clock siginal and give to
seq_item_port.
4.2.5. ENV
The following componets are present inside the Environment
4.2.4.1. Environment
4.2.4.2. Scoreboard
4.2.4.3. Virtual sequencer
4.2.4.4. master coverage
4.2.4.5. slave coverage
4.2.4.1. Environment
 Environment contains all the agents and scoreboard,virtual
sequncer,coverage collector.
4.2.4.2. Scoreboard
 Scoreboard will collect all the transction from monitor.
 Scoreboard will compare Excepted output with autual output after
receive the excepted output from referance logic and autual from DUT.
4.2.4.3. Virtual sequencer
 A virtual sequence is a container to start multiple sequences on different
sequencers in the environment.
4.2.4.4. master coverage
 master coverage is used to keep a track of master functionality.
4.2.4.5. slave coverage
 slave coverage is used to keep a track of slave functionality.
4.2.6. TEST
Test contain all the test cases to verify the dut.

4.2.7. TOP
The following componets are present inside the TOP
4.2.6.1. Interface
4.2.6.2. Test
4.2.6.3.Assertion
4.2.6.1. Interface
 Interface is connect AXI VIP to AXI IP
4.2.3.2. Test
 Test contain all AXI IP test cases
4.2.3.3. Assertion
 Assertion is used to check all the AXI IP protocols.
5.Checker
 Checkers are used to cross check the functionality of the dut and automate the
check.
 There are two types of checker.
5.1. Direct Check
5.2. Referance logic Check
5.1. Direct Check(yes required)

 In direct check, scorboard will get both the monitor data and compare them.
 Here we need direct check.
 Direct checks are two type
5.1.1 Synchronous check.
5.1.2 ASynchronous check.

 If any processing delay is there we need synchronous check.
 For synchronous check we need tlm analysis fifo.
 Here we need synchronous direct check
 Following check are required to verify the functionality of axi.

◦ Reset check
◦ Burst-based transactions with only start address check
◦ Separate read and write data channels check
◦ Multiple outstanding addresses check
◦ Out-of-order transaction completion check

◦ Unaligned data transfers using byte strobes check
◦ Atomic operations check
◦ Protection unit support check
◦ System cache support check

 If there is no processing delay we need Asynchronous check.
 For for Asynchronous check we need tlm analysis port.
5.2. Referance logic Check(Not required)

 In referance logic check , scorboard will compare expected output with actual
output with referance logic.
 Here referance logic check is not applicable.
 Referance logic check is two type

 If any processing delay is there we need synchronous check.
 for synchronous check we need tlm analysis fifo.

 If there is no processing delay we need Asynchronous check.
 For for Asynchronous check we need tlm analysis port.

6.Functional Coverage
 Functional Coverage is the determination of how much functionality of a
design has been exercised by a verification environment.
 To track the smart_register IP we need two covergroup.
 Two covergroups are
6.1. covergroup axi_master_cg
6.2. covergroup axi_slave_cg
6.1 covergroup axi_master_cg

 Covergroup contains all the coverpoints and cross.
 coverpiont are
6.1.1.coverpoint AWID_cvg::AWID
6.1.2. coverpoint AWADDR_cvg::AWADDR
6.1.3. coverpoint AWLEN_cvg::AWLEN
6.1.4. coverpoint AWSIZE_cvg::AWSIZE
6.1.5. coverpoint AWBURST_cvg::AWBURST
6.1.6. coverpoint AWLOCK_cvg::AWLOCK
6.1.7. coverpoint AWCACHE_cvg::AWCACHE
6.1.8. coverpoint AWPROT_cvg::AWPROT
6.1.9. coverpoint WID_cvg::WID
6.1.10. coverpoint WDATA_cvg::WDATA
6.1.11. coverpoint WSTRB_cvg::WSTRB
6.1.12.coverpoint ARID_cvg::ARID
6.1.13. coverpoint ARADDR_cvg::ARADDR
6.1.14. coverpoint ARLEN_cvg::ARLEN
6.1.15. coverpoint ARSIZE_cvg::ARSIZE
6.1.16. coverpoint ARBURST_cvg::ARBURST
6.1.17. coverpoint ARLOCK_cvg::ARLOCK

6.1.18. coverpoint ARCACHE_cvg::ARCACHE
6.1.19. coverpoint ARPROT_cvg::ARPROT
6.1.20. coverpoint reset_cvg::reset
 cross are
6.1.21 cross awburst_awlen_awsize
6.1.22 cross arbusrst_arlen_arsize
6.1.1.coverpoint AWID_cvg::AWID
 Defaut bins are enough.
6.1.2. coverpoint AWADDR_cvg::AWADDR

 We need define following bins
low,mid1,mid2,mid3,mid4,mid5,high
6.1.3. coverpoint AWLEN_cvg::AWLEN
 Default bins are enough.
6.1.4. coverpoint AWSIZE_cvg::AWSIZE

6.1.5. coverpoint AWBURST_cvg::AWBURST

 we need to define following bins
 fix,inc.wrap bins
6.1.6. coverpoint AWLOCK_cvg::AWLOCK

 normal,lock,exclusive
6.1.7. coverpoint AWCACHE_cvg::AWCACHE

 Noncacheable_bufferable,Bufferable,Cacheable_not_allocate
 Cacheable_write_through_allocate_reads,Cacheable_
write_back_allocate_reads
 Cacheable_write_through_allocate_writes,Cacheable_write_b
ack_allocate_writes
 Cacheable_write_through_allocate_reads_writes
 Cacheable_write-back_allocate_reads_writes
6.1.8. coverpoint AWPROT_cvg::AWPROT

 privileged_normal
 sucure_nonscure
 instruction_data
6.1.9. coverpoint WID_cvg::WID

6.1.10. coverpoint WDATA_cvg::WDATA
◦ low,mid1,mid2,mid3,mid4,mid5,high
6.1.11. coverpoint WSTRB_cvg::WSTRB

6.1.12.coverpoint ARID_cvg::ARID
6.1.13. coverpoint ARADDR_cvg::ARADDR

◦ low,mid1,mid2,mid3,mid4,mid5,high
6.1.14. coverpoint ARLEN_cvg::ARLEN
6.1.15. coverpoint ARSIZE_cvg::ARSIZE
6.1.16. coverpoint ARBURST_cvg::ARBURST

◦ fix,inc.wrap
6.1.17. coverpoint ARLOCK_cvg::ARLOCK
◦ normal,lock,exclusive
6.1.18. coverpoint ARCACHE_cvg::ARCACHE
 Noncacheable_bufferable,Bufferable,Cacheable_not_allocate
 Cacheable_write_through_allocate_reads,Cacheable_
write_back_allocate_reads
 Cacheable_write_through_allocate_writes,Cacheable_write_b
ack_allocate_writes
 Cacheable_write_through_allocate_reads_writes
 Cacheable_write-back_allocate_reads_writes
6.1.19. coverpoint ARPROT_cvg::ARPROT
 privileged_normal
 sucure_nonscure
 instruction_data
6.1.20. coverpoint reset_cvg::reset
 default bins are enough
6.2 covergroup axi_slave_cg

 Covergroup contains all the coverpoints and cross.
 This covergroup is used for the output data_out and input rd_en,rd_ptr.
 Here 3 coverpoints are enough.
 Not required to cross.
 There coverpiont are
6.2.1.coverpoint BID_cvg::BID
6.2.2. coverpoint BRESP_cvg::BRESP
6.2.3. coverpoint RID_cvg::RID
6.2.4. coverpoint RDATA_cvg::RDATA
6.2.5. coverpoint RRESP_cvg::RRESP
6.2.1.coverpoint BID_cvg::BID
 Default bins are enough
6.2.2 coverpoint BRESP_cvg::BRESP
6.2.3 coverpoint RID_cvg::RID
6.2.4 coverpoint RDATA_cvg::RDATA
 We need to defne following
◦ low,mid1,mid2,mid3,high
6.2.5 coverpoint RRESP_cvg::RRESP

7.Assertion (yes required)
 check whether all write address channel remains stable after AWVALID is
asserted
 check whether all write data channel remains stable after WVALID is asserted
 check whether all write response channel remains stable after BVALID is
asserted
 check whether all read address channel remains stable after ARVALID is
asserted
 check whether all read data channel remains stable after RVALID is asserted
 check VALID-READY handshking
 check reset siginals w.r.t valid,ready & all siginals

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AXI-3 VIP V-Plan

1 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

Sl.N Versio Date comment Issue Change Author

2 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

3 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

4 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

5 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

6 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

1.1 Direct stimulus

1.1 Direct stimulus(yes required)

1.2 Random stimuls(yes required)

7 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

◦ rand bit [2:0] WID;

◦ rand bit [3:0] BID;

◦ rand bit [3:0] ARID;

8 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

◦ constraint lD_SAME{AWID == WID;}

9 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

10 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

 Here we required one inteface i.e AXI_if interface.

2.1 AXI_if interface

 Outputs from DUT

11 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

12 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

3.1.1. Start of simulation reset

13 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

3.2.1 Fixed burst

14 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

3.2.2 Incrementing burst

15 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

3.2.3 Wrapping burst

Two restrictions apply to wrapping bursts:

Start_Address: The start address issued by the master.

16 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

For wrapping bursts, the Wrap_Boundary variable is extended to account for

Wrap_Boundary = ( INT ( Start_Address / ( Number_Bytes x Burst_Length )))

Upper_Byte_Lane = Aligned_Address + ( Number_Bytes - 1) -

17 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

3.3 Separate read and write data channels

 AXI3 have separate read and write channels.

18 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

3.4 Multiple outstanding addresses

3.5 Out-of-order transaction completion

 The ability to complete transactions out of order means that transactions to

19 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

3.6 Unaligned data transfers using byte strobes

20 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

3.7 Atomic operations

 To enable the implementation of atomic access primitives, the ARLOCK[1:0]

Atomic access encoding

 Atomic access are 3 types

3.7.1 Normal access

21 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

3.7.2 Exclusive access

The ARLOCK[1:0] or AWLOCK[1:0] signal selects exclusive access, and

3.7.3 Locked access

22 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

3.8 Protection unit support

23 AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

3.9 System cache support

3.9.1 Bufferable (B) bit, ARCACHE[0] and AWCACHE[0]

3.9.1 Bufferable (B) bit, ARCACHE[0] and AWCACHE[0]