Preliminary PT8921
Smart Audio Combo-Station with USB
Mini-Host & SD/MMC Host Interface Controller
DESCRIPTION
The PT8921 is a cost-efficient single chip for audio
mini-combo play-station application. The chip integrated
the USB2.0 FS host controller, SD/MMC host controller,
Sigma-Delta Audio-DAC and WAV/MP3/WMA/AAC
Audio-Decoder in one chip. Only few external components
needed in application circuits makes it suite for the audio
play-station system with USB2.0 FS host, SD/MMC host
and i-Pod audio control interfaces.
The I/O interfaces are totally following the USB2.0 FS host
class interface specification and SD/MMC card
specification. The stand alone audio play-station and no
special driver software need to install on this system by
user in the recent market. The PT8921 is a truly plug and
play audio play-station controller with USB2.0 FS host and
SD/MMC host interfaces. There are some extended
functions for the different audio sources and applications.
The embedded 8 pins provide the player function key and
other adjustment feature. The 5 GPIO-pins support the
other control function for customer application.
APPLICATIONS
• Portable Audio Play-Station
• Car Audio Combo-Station
• Home Audio Play-Station
BLOCK DIAGRAM
Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
FEATURES
• Built-in USB 2.0 FS Mini-Host interface.
• Compliant with USB Mass-storage class specification.
• Built-in SD/MMC Host interface.
• Compliant with SD/SDIO Card specification Version 2.0.
• Compliant with MMC Card specification Version 4.2.
• Support FAT12, FAT16 and FAT32 file system.
• Built-in 8051 base MCU with 8K ROM.
• Support ISP (In-System-Programmable) Interface for
external program Flash-ROM.
• Built-in WAV/MP3 WMA/AAC Format Audio-Decoder.
• Support MPEG1/2/2.5 layer III audio decoding.
• Built-in Flat/Pop/Jazz/Classic/Rock processing function.
• Built-in Digital Volume control function
• Built-in SNR=85dB (A-Weighted) Sigma-Delta DAC,
PWM Output.
• Built-in IIC Master/Slave Control Interface.
• Built-in UART Interface to communicate with i-Pod.
• Built-in external IIS input for optional audio input
sources, and support one IIS output connecting an
external advanced audio controller or stand-alone
sigma-delta DAC controller.
• Packages: 100 Pins LQFP
 PT8921

SYSTEM APPLICATION DIAGRAM

FM AM Power Amp.
Audio Process IC
RF/IF/MPX 0.5W
Electronic vol.
Press EQ 2W
XBass 5W
Function Switch 20W

Radio & Audio Block

Select Option

iPod CD Mech. IR-RX

Master MCU Remote
Control
EEPROM
SD/MMC
I2 S Main Block

USB/SD/MMC Jog-dial
iPod
USB Device MP3/WMA/AAC/WAV
Certified
Audio Decoder Panel Key
Σ−Δ DAC Max. 24 keys
PT8921
Dot Matrix
Display

FLASH ROM

USB/SD/MMC/iPod Key Control &

Host Decoder Block Display Block

PRE1.2 2 September 2010

 PT8921

ORDER INFORMATION
Valid Part Number Package Type Top Code
PT8921-LQ 100-PIN LQFP PT8921-LQ

PIN CONFIGURATION

PRE1.2 3 September 2010

 PT8921

PIN DESCRIPTION
Pin Name I/O Type Description Pin No.
OSCO O 12MHz Oscillator Output for System Processing 1
OSCI I 12MHz Oscillator Input for System Processing 2
VCC3_PLL APWR PLL IO Analog 3.3V Power 3
VSS3_PLL APWR PLL IO Analog Gound 4
VREG_18 PWR_O Regulator 1.8V for Core Power, connect to external capacitor 5
VCC3_REG APWR Regulator 3.3 Power 6
VSS3_REG APWR Regulator Ground 7
USB_DM IO USB2.0 FS differential data minus 8
USB_DP IO USB2.0 FS differential data plus 9
VCC3_USB APWR USB2.0 FS PHY Analog 3.3V Power 10
VSS3_USB APWR USB2.0 FS PHY Analog Ground 11
VSS18_C1 CPWR Internal Core Ground 12
VSS3_D1 DPWR Digital Ground 13
RESETN I System reset input (active low) 14
SDH_WP IO SD/MMC Host Interface Card Write Protection 15
SDH_CD I SD/MMC Host Interface Card Detection Input 16
SDH_CMD IO SD/MMC Host Interface Command 17
SDH_CLK O SD/MMC Host Interface Output Clock 18
SDH_DAT0 IO SD/MMC Host Interface Data-0 19
Configure to be GPIO_A9 or External Program ROM Address-16 or
GPIO_A9 IO 20
Master MCU INT (MINT)
PWD_TRIG I Power Down Mode Trigger Function 21
VCC3_D1 DPWR Digital 3.3V Power 22
VCC3_D2 DPWR Digital 3.3V Power 23
IIS_DOUT O IIS Interface Output Data 24
IIS_MCKO O IIS Interface Master Clock Output 25
IIS_WSO O IIS Interface Right/ Left Channel Switch Output 26
IIS_BCKO O IIS Interface Output Clock 27
TEST_EN I Test Enable Pin, “1” indicate in test Mode 28
IIC_ CLK_S IO IIC Slave Interface Input Clock 29
IIC_DAT_S IO IIC Slave Interface Data Pin 30
IIC_ADR_S I IIC Slave Interface Address Pin 31
VSS3_D2 DPWR Digital Ground 32
VSS18_C4 CPWR Internal Core Ground 33
VSS3_D3 DPWR Digital Ground 34
GPIO_A0 IO Configure to GPIO_A0 or PLAY/PAUSE 35
GPIO_A1 IO Configure to GPIO_A1 or STOP 36
GPIO_A2 IO Configure to GPIO_A2 or Volume Up 37
GPIO_A3 IO Configure to GPIO_A3 or Volume Down 38
GPIO_A4 IO Configure to GPIO_A4 or Mute 39
GPIO_A5 IO Configure to GPIO_A5 or Preview 40
GPIO_A6 IO Configure to GPIO_A6 or BACK 41
GPIO_A7 IO Configure to GPIO_A7 or Mode (USB/SD/IIS/i-Pod) 42
GPIO_A8 IO Configure to GPIO_A8 or External Program ROM Reset or ISP_LED 43
VCC3_D3 DPWR Digital 3.3V Power 44
UART_RX I UART Interface Receive Pin 45
UART_TX O UART Interface Transmit Pin 46
IIC_ CLK_M IO IIC Master Interface Output Clock 47
IIC_DAT_M IO IIC Master Interface Data Pin 48
EMM_ADR14 O External Program ROM Address-14 49
EMM_ADR13 O External Program ROM Address-13 50
EMM_ADR12 O External Program ROM Address-12 51
EMM_ADR11 O External Program ROM Address-11 52
EMM_ADR10 O External Program ROM Address-10 53
VSS3_D4 DPWR Digital Ground 54

PRE1.2 4 September 2010

 PT8921
Pin Name I/O Type Description Pin No.
GPIO_B0 IO Configure to GPIO_B0 55
GPIO_B1 IO Configure to GPIO_B1 56
VSS18_C3 CPWR Internal Core Ground 57
GPIO_B2 IO Configure to GPIO_B2 58
GPIO_B3 IO Configure to GPIO_B3 59
VSS3_D5 DPWR Digital Ground 60
EMM_ADR9 O External Program ROM Address-9 61
EMM_ADR8 O External Program ROM Address-8 62
EMM_ADR7 O External Program ROM Address-7 63
EMM_ADR6 O External Program ROM Address-6 64
EMM_ADR5 O External Program ROM Address-5 65
EMM_ADR4 O External Program ROM Address-4 66
EMM_ADR3 O External Program ROM Address-3 67
EMM_ADR2 O External Program ROM Address-2 68
EMM_ADR1 O External Program ROM Address-1 69
VCC3_D4 DPWR Digital 3.3V Power 70
EMM_ADR0 O External Program ROM Address-0 71
EMM_DAT7 IO External Program ROM DATA-7 72
EMM_DAT6 IO External Program ROM DATA-6 73
EMM_DAT5 IO External Program ROM DATA-5 74
EMM_DAT4 IO External Program ROM DATA-4 75
EMM_DAT3 IO External Program ROM DATA-3 76
EMM_DAT2 IO External Program ROM DATA-2 77
EMM_DAT1 IO External Program ROM DATA-1 78
EMM_DAT0 IO External Program ROM DATA-0 79
VSS3_D6 DPWR Digital Ground 80
GPIO_B4 IO Configure to GPIO_B4 81
PWM_RN O PWM Right-Channel Negative Output 82
PWM_RP O PWM Amplifier Right-Channel Positive Output 83
VSS3_DAC APWR Sigma-Delta DAC Analog Ground 84
VCC3_DAC APWR Sigma-Delta DAC Analog Power 85
PWM_LP O PWM Left-Channel Positive Output 86
PWM_LN O PWM Left-Channel Negative Output 87
VSS18_C2 CPWR Internal Core Ground 88
VCC3_D5 DPWR Digital 3.3V Power 89
EMM_ADR15 O External Program ROM Address-15 90
EMM_WEB O External Program ROM Write-Operation Enable 91
EMM_OEB O External Program ROM Output Enable 92
EMM_CEB O External Program ROM Chip Enable 93
IIS_MCKI I IIS Interface Master Clock Input 94
IIS_DIN I IIS Interface Input Data 95
IIS_WSI I IIS Interface Right/Left Channel Switch Input 96
IIS_BCKI I IIS Interface Input Clock 97
TEST_MD0 I Test Pin, “1” indicate test-mode 0 98
Set “1”, enable ISP-Mode to update the new firmware to external
ISP_EN I 99
Programmable Flash-ROM
VSS3_D7 DPWR Digital Ground 100

PRE1.2 5 September 2010

 PT8921

FUNCTION DESCRIPTION
USB 2.0 FS PHY AND HOST CONTROLLER
PT8921 implements a hi-speed USB2.0 FS host interface that can communicate with other USB audio devices. This
behavior conforms to the USB2.0 FS Host interface specification. The host-controller is designed for processing
efficiency with hardware implementing the USB Host Protocol, and other critical functions and is competitive in
performance and area usage. The standard USB2.0 FS host transceivers can be used through the SIE controller’s
interface s available. The host-controller’s system connection is through the 8-bit MCU control interface and the
DMA-channel. The USB host controller is capable of control transfer mode and bulk transfer mode. Generally, this
setting should be satisfying for most practical needs.

SD/MMC HOST CONTROL INTERFACE

PT8921 integrates the SD/MMC host control interface. The SD/MMC host interface was compatible with SD card
specification Ver. 2.0 and MMC-card specification Ver. 4.2 or before ones. The SD/MMC host interface provides the high
performance access-rate to or from the SD/MMC card. The audio sources might be restored in the SD/MMC card and
play out by PT8921.

MCU CORE
PT8921 integrates an 8-bit MCU. Instruction set is compatible with 8051. Process capability is controlled by software up
to 48 MHz. PT8921 includes 8K bytes on-chip ROM.

SFR
SFR means “Special Function Register” which is the interface to communicate with the system blocks. With SFR, the
system MCU can handshake with the USB controller, configure the MP3/WMA/AAC audio-decoder and sigma-delta
DAC.

UART
The PT8921 provides UART interface to communicate with i-Pod. With the specified commands and setting through the
certificated chip to access the audio playing behaviors of i-Pod by PT8921 UART interface. The detail command protocol
will be defined on the Apple’s i-Pod control protocol specification.

INTERNAL PROGRAM ROM

The PT8921 provides the internal program 8K ROM. It can be storage the executive program for the functions of “MCU
test”, “testing mode setup”, “system start operation” and “ISP mode control”.

EXTERNAL PROGRAM ROM CONTROL INTERFACE

The PT8921 provides the ISP interface to communicate with external program ROM. The engineer/customer may
update the firmware for PT8921 by modifying the ROM code through USB storage devices. The acceptable external
Flash ROM would be the maximum 128K x 8-bit data width.

PRE1.2 6 September 2010

 PT8921

AUDIO DECODER
The PT8921 provides Audio decoder to take any WAV/MP3/WMA/AAC bit-stream, automatically detects the header and
extracts all header/side information, and then uses the information to decode uncompressed WAV and compressed
MP3/WMA/AAC bit-stream. The output is 16 bits PCM samples. These PCM output samples can be transferred to the
built-in Sigma-Delta audio DAC or external audio DAC. It supports a configurable control interface for the 8-bit MCU to
access the audio format information and working status.

FLAT/ROCK/JAZZ/POP/CLASSIC MODES EQUALIZER

There are five modes song equalizer embedded in PT8921 function.

DIGITAL VOLUME CONTROL

The PT8921 provides the internal digital volume control with 64 steps control for volume-up and volume-down.

SAMPLE FREQUENCY CONTROL

The PT8921 provides the 8/11.025/12/16/22.05/24/32/44.1/48K Hz sampling frequencies for MPEG and WAV format
bit-steam.

SIGMA-DELTA DAC
PT8921 has built-in an on-chip SNR=85dB (A-Weighted) Sigma-Delta DAC. The DAC interface supports sample rate of
32 KHz, 44.1 KHz and 48 KHz.

GENERAL PURPOSE IO PORTS

PT8921 has five GPIO-pins, GPIO_B4, GPIO_B3, GPIO_B2, GPIO_B1 and GPIO_B0. Support the other control
function for customer application.

PLAYER FUNCTION KEY CONFIGURATION

PT8921 has eight pins for function key control, GPIO_A7, GPIO_A6, GPIO_A5, GPIO_A4, GPIO_A3, GPIO_A2,
GPIO_A1, and GPIO_A0. Support the player function key and other adjustment feature.

DMA CONTROLLER
PT8921 supports one configurable DMA controller. The DMA controller can control the data exchanged to be accessed
between the Memory/ FIFO and I/O-Interface. The DMA controller can be configured with 8-bit MCU interface.

OSCILLATOR AND PLLS

PT8921 requires a single 12MHz crystal as input source of the internal low jitter and high performance PLLs. One PLL is
used to generate internal/external DAC Master Clock (256fs) and system clock of internal 16-bit Sigma-Delta DAC. The
other PLL is used to generate frequency for other system blocks such as USB2.0 FS SIE, SD/MMC host interface, DMA
controller, embedded MCU, audio decoder, etc.

IIC INTERFACE
PT8921 provides the master/slave IIC capability. In master mode, it generates the clock source (IIC_SCL) and initiates
data-transactions on the data line (IIC_SDA). Data-transaction on the IIC bus is byte oriented. In slave mode, it
communicates with the master MCU. With the specified baud rate setting, the master MCU can issue the system
command to control the behavior of PT8921 by IIC control interface. See the IIC_Bus_Specification_1995 for detailed
information.

PRE1.2 7 September 2010

 PT8921

AUDIO SERIAL DATA OUTPUT INTERFACE (IIS INTERFACE)

PT8921 supports a serial audio input and serial audio output interfaces. It was designed to interface with the standard
digital audio components and to accept a number of serial data formats. The PT8921 can be acted as a slave when
receiving audio input from standard digital audio components. Serial data for two channels is provided using the 3 input
pins: left/right clock IIS_WKI, serial input clock IIS_CKI, and serial input data IIS_DIN. It can be acted as a master when
transmit audio output to external digital audio processor. Serial data for two channels is provided using 3 output pins: left/
right clock IIS_WKO, serial output clock IIS_CKO, and serial output data IIS_DOUT.

IIS INPUT INTERFACE

The numbers of Sampling Frequency supported by IIS Input Interface are total 3, they are: 32 KHz/44.1KHz/48KHz. It
also supports Standard IIS Data Format, Right-Justified Data Format and Left-Justified Data Format. BCK may be
operated at 32, 40, 48, or 64 times the Sampling Frequency. Date Length is able to be 16-Bit, 20-Bit, 24-Bit or 32-Bit.

IIS OUTPUT INTERFACE

The number of Sampling Frequency supported by IIS Output Interface are total 9, they are: 8KHz, 11.025KHz, 16KHz,
22.05KHz, 24KHz, 32KHz, 44.1KHz and 48KHz. Its available output formats are 16-bit/32-bit Standard IIS Data, 16-bit
/32-bit Left-Justified Data and 16-bit/18-bit/20-bit/24-bit/32-bit Right-Justified Data. BCK may be operated at either 32 or
64 times the Sampling Frequency.

EXTERNAL NOR FLASH

PT8921 supports the Parallel NOR Flash ICs, for example MX29LV040. Customers are able to cross-reference other
providers as shown on Table 1. The software command sequence of Parallel NOR Flash must be defined and followed
by Table 2.

Table 1: NOR Flash Memory

Density Voltage Package SST ATMEL MXIC
2M SST29VF020 -- MX29LV002C/002NC T/B
2.7~3.6V 32-TSOP
4M SST29VF040 AT49BV040B MX29LV040C

Table 2: Command Sequence

1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus
Command
Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle
Sequence
Address Data Address Data Address Data Address Data Address Data Address Data
Byte-Program 555H AAH 2AAH 55H 555H A0H Address Data
Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

PRE1.2 8 September 2010

 PT8921

ABSOLUTE MAXIMUM RATINGS

DVDD = 3.3V, AVDD = 3.3V
Parameter Symbol Min. Max. Unit
Operating Temperature Range TA -40 +125 °C
Storage Temperature Range TSTG -65 +150 °C

PRE1.2 9 September 2010

 PT8921

PACKAGE INFORMATION
100-PIN, LQFP, 14x14mm

Symbol Min. Nom. Max.

A - - 1.600
A1 0.050 - 0.150
A2 1.35 1.40 1.450
b 0.170 0.220 0.270
c 0.090 - 0.200
D 16.00 BSC.
D1 14.00 BSC.
E 16.00 BSC.
E1 14.00 BSC.
e 0.50 BSC.
L1 1.00 REF
θ 0o 3.5 o 7o
Notes:
1. Refer to JEDEC MS-026BED
2. All dimensions are in millimeter.

PRE1.2 10 September 2010

 PT8921

IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and to discontinue any product without notice at any time.
PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No
circuit patent licenses are implied.

Princeton Technology Corp.

2F, 233-1, Baociao Road,
Sindian, Taipei 23145, Taiwan
Tel: 886-2-66296288
Fax: 886-2-29174598
http://www.princeton.com.tw

PRE1.2 11 September 2010