Maestro-2ETM
PCI Audio Accelerator
DESCRIPTION
The Maestro-2ETM PCI audio accelerator, a high-
performance 500-MIPS-equivalent PCI audio processor,
uses the high-bandwidth PCI bus and an AC’97 CODEC
to deliver advanced PC audio features. These features
include HRTF 3-D positional audio, high-quality
64-channel wavetable music synthesis with downloadable
wavetable samples, and DVD AC-3 5.1-to-2 speaker
virtualization.
The Maestro-2E implements multi-stream DirectSound
and DirectSound3D acceleration and Windows 95 and
Windows 98 stream acceleration with digital mixing and
sample rate conversion. The Maestro-2E maintains full
DOS legacy audio compatibility over a standard PCI 2.1
bus. The Maestro-2E is designed for high-performance
consumer multimedia PC, notebook PC, and add-in card
applications.
The Maestro-2E, based on a dual-engine, 64-channel,
pipelined Wave Processor and a programmable audio
signal processor, provides simultaneous support for
multiple audio streams of different types. Its core
architecture is designed to handle complex signal
processing tasks with a bus-mastering PCI interface and
built-in dedicated DMA engine supporting a DSP core.
The support functions ensure efficient transfer of audio
data streams to and from system memory buffers,
providing a system solution with maximum performance
and minimal host CPU loading. The architecture enables
implementation of communications over the Internet from
multiple sources.
The Maestro-2E has a variety of audio interfaces. It has
two 20-bit AC’97 CODEC interfaces that can be enabled
simultaneously for notebook docking implementation. The
secondary AC’97 CODEC interface can be programmed to
handle multiple serial CODEC interfaces which, together
with the primary AC’97 CODEC, can provide full-featured
AC-3 speaker outputs. The Maestro-2E also supports a
consumer IEC958 S/PDIF output that provides high-
quality digital audio and MIDI.
The Maestro-2E, which operates at 3.3 volts, has several
special features for notebook operation. It is compliant
with the Advanced Power Management (APM) 1.2,
Advanced Configuration and Power Interface (ACPI) 1.0,
and PCI Power Management Interface (PPMI) 1.0. It has
multiple power-saving modes (D0, D1, D2, and D3) for
power-efficiency when the audio system is both active and
idle. It provides a high-quality docking solution that is
backward compatible to the ES978 docking station
ESS Technology, Inc.
Data Sheet
interface, and also supports an AC-link based digital
docking solution with its secondary 20-bit AC-link.
CLKRUN# pin support can be used to stop the PCI
interface clock. This helps achieve the lowest power
consumption in D3hot mode.
The Maestro-2E supports full DOS game compatibility for
both PC motherboard and add-in card solutions through
three hardware implementations: PC/PCI, Distributed
DMA (DDMA), and Transparent DMA (TDMA). While PC/
PCI and DDMA are industry-standard protocols for legacy
support, ESS’ TDMA technology implements DOS game
compatibility over the standard PCI 2.1 bus without
additional sideband signals.
The Maestro-2E PCI audio accelerator is pin-to-pin
compatible to the Maestro-2, and is available in an
industry-standard 100-pin Thin Quad Flat Package
(TQFP).
FEATURES
High-Performance PCI Audio Acceleration
• 500-MIPS-equivalent dual-engine PCI audio accelerator
• 64-Channel wavetable synthesis
• HRTF 3-D positional audio acceleration
• Multi-Stream DirectSound and DirectSound3D
acceleration
• Hardware acceleration for DirectMusic, ActiveMovie, and
DirectInput API
• DVD AC-3 speaker virtualization
• Enhanced effects (reverb, chorus, flange, treble, bass,
and 3D stereo expander)
• Advanced platform for interactive 3-D gaming, DVD
movie playback, and Internet communications
Legacy DOS Game Support
• Full DOS game compatibility through three hardware
implementations: PC/PCI, DDMA, and TDMA
• TDMA needs no sideband signals, full DOS game
compatibility achieved in standard PCI 2.1 bus
• Serial IRQ support
Complete Audio Solution for Notebook PCs
• Compliance with APM 1.2, ACPI 1.0, and PPMI 1.0
• Compliance with Intel’s “Mobile Power Guideline”
• 3.3 volt operation with multiple power-saving modes
SAM0151-091198 1
 MAESTRO-2E DATA SHEET
MAESTRO-2E BLOCK DIAGRAMS

MAESTRO-2E BLOCK DIAGRAMS

System
Chipset CPU
DRAM

PCI BUS

Mic in
3.3 V PCI Line in
WaveCache
master Aux 1 (CD audio)
C24
Aux 2 (DVD)
RING BUS

APM 1.2
AC’97 CODEC Aux 3 (digital TV)
SB Pro ACPI 1.0 AC-Link
PPMI 1.0 Phone
legacy Line out
audio Headset out
20-Bit
AC-Link #1 Mono_out
64-Channel ES978 docking interface
ES978 digital I/F
Wave
Processor EEPROM interface EEPROM for device I/O customization

S/PDIF output Digital audio output

Effect synth DSP interface DSP serial interface

I2S/ZV MPEG audio

HRTF 3-D
Game port Analog/digital joystick
positional
audio HW volume Vol up, vol down, mute

MPU-401 MIDI keyboard

Audio
signal 20-Bit AC-Link #2/
processor Multiple serial
CODEC interface

ROM SRAM

Maestro-2E

Figure 1 Maestro-2E Block Diagram

4 SAM0151-091198 ESS Technology, Inc.

MAESTRO-2E DATA SHEET
DOCKING APPLICATIONS

PCI Wave Wave CODEC

Interface Cache Looping Interface

Command
FIFO

64 Streams
Multi-stream
Interface
64
Source Envelope Filter Effects
Sum

Figure 2 Wave Processor Portion

DOCKING APPLICATIONS

Mic in
Maestro-2E Line in
ES978 Mode-3 Line out
20-Bit 5
AC’97 2
Line out
XA1,XA3
AC-link Differential CD
CODEC
CD audio
2 XA0,XA2 Transceiver
Aux 2 (L,R) Aux B
ES978 2
Digital Interface Line in
XSC Digital
XSD Controller Mic

I2S Zoomed Video Hardware Volume

MIDI GPIO
Portable Unit Docking Unit Joystick

Figure 3 Docking Interface – Backward Compatible to the ES978

Maestro-2E 5 AC’97
20-Bit
CODEC
AC-link #1
ext. 1.03/2.00
Line out
AC’97 Line in
20-Bit 5
CODEC Mic in
AC-link #2 ext. 2.00
CD audio
MIDI
GPIO
ES978 2
ES978 Analog joystick
Digital Interface Hardware volume
I2S Zoomed Video
Portable Unit Docking Unit

Figure 4 Digital Docking Interface

ESS Technology, Inc. SAM0151-091198 5

 MAESTRO-2E DATA SHEET
PINOUT

PINOUT

G P I O 11 / S I R Q # / S P D I F O

G P I O 8 / I D ATA ( I 2S D ATA )

G P I O 6 / I S C L K ( I 2S C L K )
GD7 / VOLDN / ECLK
GD6 / VOLUP / EDIN

G P I O 7 / I L R ( I 2S L R )
GPIO10 / PCREQ#

SDFS3 / DOCKED
GPIO9 / PCGNT#
GD5 / EDOUT

SDFS2
SCLK2
OSCO

SDO2
OSCI

SDI2
GND

GND
VCC

VCC
GD4
GD3
GD2
GD1
GD0

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SCLK1 76 50 GPIO5 / VOLUP / R1#
SDFS1 77 49 GPIO4 / VOLDN / GS1
SDI1 78 48 GPIO3 / ILR / SPDIFO
SDO1 79 47 GPIO2 / IDI / R0#
XSC / TxD 80 46 GPIO1 / IDO / GS0
XSD / RxD 81 45
GPIO0 / ISCLK
GND 82 44
GND
C24 83 43
CLKRUN# / ECS
RST# 84 42 PME#
INT# 85 41 GND
VCC 86 40 AD0
PCICLK
GND
87

88 Maestro-2E 39

38
AD1
AD2
GNT# 89 37 AD3
REQ# 90 100-Pin TQFP 36 AD4
GND 91 35 AD5
AD31 92 34 AD6
AD30 93 33 AD7
AD29 94 32 VCC
AD28 95 31 C/BE0#
AD27 96 30 AD8
AD26 97 29 AD9
AD25 98 28 AD10
AD24 99 27 A D 11
VCC 100 26 AD12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
C/BE3#
IDSEL
GND
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
VCC
C/BE2#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
LOCK#
PA R
C/BE1#
GND
AD15
AD14
AD13

Figure 5 Maestro-2E Pinout

6 SAM0151-091198 ESS Technology, Inc.

MAESTRO-2E DATA SHEET
PIN DESCRIPTION

PIN DESCRIPTION
Name Number I/O Definition
C/BE[3:0]# 1,13,21,31 I/O Multiplexed command/byte enable. These pins indicate cycle type during the address phase of a
transaction. They indicate active-low byte enable information for the current data phase during
the data phases of a transaction. These pins are inputs during slave operation and outputs dur-
ing bus mastering operation.
IDSEL 2 I ID select, active-high. This pin is used as a chip select during PCI configuration read and write
cycles.
AD[31:0] 92:99,4:11, I/O Multiplexed address and data lines.
23:30,33:40
FRAME# 14 I/O Cycle frame, active-low. The current PCI bus master drives this pin to indicate the beginning and
duration of a transaction.
IRDY# 15 I/O Initiator ready, active-low. The current PCI bus master drives this pin to indicate that as the initi-
ator it is ready to transmit or receive data (and complete the current data phase).
TRDY# 16 I/O Target ready, active-low. The current PCI bus master drives this pin to indicate that as the target
device it is ready to transmit or receive data (and complete the current data phase).
DEVSEL# 17 I/O Device select, active-low. The PCI bus target device drives this pin to indicate that it has
decoded the address of the current transaction as its own chip select range.
STOP# 18 I/O Stop transaction, active-low. The current PCI bus target drives this pin active to indicate a
request to the master to stop the current transaction.
LOCK# 19 I/O Lock.
PAR 20 I/O Parity, active-high. This pin indicates even parity across AD[31:0] and C/BE[3:0]# for both
address and data phases. The signal is delayed one PCI clock from either the address or data
phase for which parity is generated.
PME# 42 O Power management enable interrupt output to wake up the system.
CLKRUN# I/O Dual-purpose pin. CLKRUN# is an input for clock status and an output to start/speed-up clock.
43
ECS O ECS# is the EEPROM chip select. ECS is active during power-on reset; turned off after reset.
I/O Dual-purpose pin. GPIO0 is general purpose input/output 0. Selected by
GPIO0
Maestro2E_Base+68h[11:0].
45
I ISCLK is the serial shift clock for the DSP serial interface. Selected by setting PCI 52h[4] = 1 and
ISCLK
Maestro2E_Base+36h[15] = 1.
I/O Multi-purpose pin. GPIO1 is general purpose input/output 1. Selected Strap pin:
GPIO1
by Maestro2E_Base+68h[11:0]. 1 = TDMA mode for
46 O IDO is the serial data output for the DSP serial interface. Selected by 440LX chipset (default).
IDO 0 = PC/PCI mode for
setting PCI 52h[4] = 1 and Maestro2E_Base+36h[15] = 1.
440LX chipset.
GS0 O GS0 is PCI bus grant select 0. Selected by setting PCI 58h[0] = 1.
I/O Multi-purpose pin. GPIO2 is general purpose input/output 2. Selected by
GPIO2
Maestro2E_Base+68h[11:0].
47 I IDI is the serial data input for the DSP serial interface. Selected by setting PCI 52h[4] = 1 and
IDI
Maestro2E_Base+36h[15] = 1.
R0# I R0# is PCI bus request 0. Selected by setting PCI 58h[0] = 1.
I/O Multi-purpose pin. GPIO3 is general purpose input/output 3. Selected by
GPIO3
Maestro2E_Base+68h[11:0].
I ILR is the frame sync signal for the DSP serial interface. Selected by setting PCI 52h[4] = 1 and
ILR 48
Maestro2E_Base+36h[15] = 1.
O SPDIFO is the S/PDIF output. Selected by setting PCI 53h[0] = 1 and PCI 58h[1] = 0. Alterna-
SPDIFO
tively, the SPDIFO at pin 62 may be used. SPDIFO at pin 48 is the default.

ESS Technology, Inc. SAM0151-091198 7

 MAESTRO-2E DATA SHEET
PIN DESCRIPTION

Name Number I/O Definition

I/O Multi-purpose pin. GPIO4 is general purpose input/output 4. Selected Strap pin:
GPIO4
by Maestro2E_Base+68h[11:0]. 1 = Subsystem ID[0] = 0.
I VOLDN is a volume decrease input. Selected by setting PCI 52h[7:5] 0 = Subsystem ID[0] =1.
49
VOLDN to 1x0. Alternatively, the VOLUP/VOLDN pair at pins 73 and 74 may
be used.
GS1 O GS1 is PCI bus grant select 1. Selected by setting PCI 58h[0] = 1.
I/O Multi-purpose pin. GPIO5 is general purpose input/output 5. Selected by
GPIO5
Maestro2E_Base+68h[11:0].
50 I VOLUP is a volume increase input. Selected by setting PCI 52h[7:5] to 1x0. Alternatively, the
VOLUP
VOLUP/VOLDN pair at pins 73 and 74 may be used.
R1# I R1# is PCI bus request 1. Selected by setting PCI 58h[0] = 1.
I/O Dual-purpose pin. GPIO6 is general purpose input/output 6. Selected by
GPIO6
Maestro2E_Base+68h[11:0].
51
ISCLK I ISCLK (I2SCLK) is the I2S serial clock. Selected by setting Maestro2E_Base+36h[15] = 1.
(I2SCLK)
I/O Dual-purpose pin. GPIO7 is general purpose input/output 7. Selected by
GPIO7
Maestro2E_Base+68h[11:0].
52
ILR I ILR (I2SLR) is the I2S frame sync. Selected by setting Maestro2E_Base+36h[15] = 1.
(I2SLR)
I/O Dual-purpose pin. GPIO8 is general purpose input/output 8. Selected by
GPIO8
Maestro2E_Base+68h[11:0].
53
IDATA I IDATA (I2SDATA) is the I2S data input pin. Selected by setting Maestro2E_Base+36h[15] = 1.
(I2SDATA)
SDO2 55 I/O Serial data out.
SDI2 56 I Serial data in.
SDFS2 57 O Serial data frame sync. Strap pin in combination with strap pin 77. See the description for pin 77.
SDFS3 O Dual-purpose pin. SDFS3 is the serial data frame sync.
58 I DOCKED, when active-high, indicates that the unit is docked to an AC’97 CODEC with docking
DOCKED
station support. Internal 2.2k pull-down to digital ground.
SCLK2 59 I/O Serial data clock. Output pin when the multi-CODEC interface is used. Input pin when the AC-
link #2 interface is used.
I/O Dual-purpose pin. GPIO9 is general purpose input/output 9. Selected by
GPIO9
60 Maestro2E_Base+68h[11:0].
PCGNT# I PCGNT# is the PC/PCI grant input. Selected by setting PCI 50h[10:8] = 010.
I/O Dual-purpose pin. GPIO10 is general purpose input/output 10. Selected by
GPIO10
61 Maestro2E_Base+68h[11:0].
PCREQ# O PCREQ# is the PC/PCI request output. Selected by setting PCI 50h[10:8] = 010.
I/O Multi-purpose pin. GPIO11 is general purpose input/output 11. Selected by
GPIO11
Maestro2E_Base+68h[11:0].
SIRQ# 62 I/O SIRQ# is the serial interrupt request. Selected by setting PCI 40h[14] = 1.
O SPDIFO is the S/PDIF output. Selected by setting PCI 53h[0] = 1 and PCI 58h[1] = 1. Alterna-
SPDIFO
tively, the SPDIFO at pin 48 may be used. SPDIFO at pin 48 is the default.
OSCI 64 I 49.152 MHz crystal input. Refer to the Maestro-2 reference design for an update.
OSCO 65 O 49.152 MHz crystal output. Refer to the Maestro-2 reference design for an update.
GD[3:0] 70:67 I/O Game port data. Joystick timer.
GD4 71 I Game port data. Joystick switch.

8 SAM0151-091198 ESS Technology, Inc.

MAESTRO-2E DATA SHEET
PIN DESCRIPTION

Name Number I/O Definition

GD5 I Dual-purpose pin. GD5 is a game port data input pin.
72
EDOUT O EDOUT is EEPROM data output. EDOUT is active during power-on reset; turned off after reset.
GD6 I Dual-purpose pin. GD6 is a game port data input pin.
I VOLUP is a volume increase input. Selected by setting PCI 52h[7:5] = 1x1. Alternatively, the
VOLUP 73
VOLDN/VOLUP pair at pins 49 and 50 may be used.
EDIN I EDIN is EEPROM data input. EDIN is active during power-on reset; turned off after reset.
GD7 I Dual-purpose pin. GD7 is a game port data input pin.
I VOLDN is a volume decrease input. Selected by setting PCI 52h[7:5] = 1x1. Alternatively, the
VOLDN 74
VOLDN/VOLUP pair at pins 49 and 50 may be used.
ECLK O ECLK is the EEPROM clock output. ECLK is active during power-on reset; turned off after reset.
SCLK1 76 I Serial clock. In AC’97 configuration, this pin is an input which drives the timing for the AC’97
interface.
SDFS1 77 O Serial data frame sync. In AC’97 configurations, this strap pin is an output which indicates the
framing for the AC’97 link with pin 57.
Pin 57 Pin 77 Option
0 0 Reserved.
0 1 Reserved.
1 0 Multi-CODEC pinout at pins 59:55.
1 1 AC-Link#2 pinout at pins 57:55, and 59.

SDI1 78 I Serial audio data input.

SDO1 79 O Serial audio data out.
TxD O Dual-purpose pin. TxD is MIDI transmit data.
80 O XSC is the ES978 Expansion Audio Mixer serial clock. Selected by setting PCI 58h[2] = 1 while
XSC
the DOCKED pin is high.
RxD I Dual-purpose pin. RxD is MIDI receive data.
81 I/O XSD is the ES978 Expansion Audio Mixer serial data input/output. Selected by setting PCI
XSD
58h[2] = 1 while the DOCKED pin is high.
C24 83 O 24.576 MHz clock output. For CODEC clock source.
RST# 84 I Reset.
INT# 85 O Interrupt request, active-low. This pin is the level triggered interrupt pin dedicated to servicing
internal device interrupt sources.
PCICLK 87 I PCI bus clock. This clock times all PCI transactions. All PCI synchronous signals are generated
and sampled relative to the rising edge of this clock.
GNT# 89 I Bus master grant, active-low. The system arbiter drives this pin to indicate to the device that
access to the PCI bus has been granted.
REQ# 90 O Bus master request, active-low tri-state output. This pin indicates to the system arbiter that this
device is requesting access to the PCI bus. This pin must be tri-stated when RST# is active.
VCC 12,32,54, Pwr +3.3 volts.
66,86,100
GND 3,22,41,44, Pwr Ground.
63,75,88,91

ESS Technology, Inc. SAM0151-091198 9

 MAESTRO-2E DATA SHEET
STRAP SELECTED OPTION

STRAP SELECTED OPTION

Pin Name Pin Number Default State at Reset Condition Description
SDFS2 57 Pull-up See In AC’97 configurations, this strap pin is an output which
Description indicates the framing for the AC’97 link with pin 57.
Pin 57 Pin 77 Option
0 0 Reserved.
0 1 Reserved.
1 0 Multi-CODEC pinout at pins 59:55.
1 1 AC-Link#2 pinout at pins 57:55, and 59.

SDFS1 77 Pull-up See See description of pin 57.

Description
GPIO1 46 Pull-up Low PC/PCI system configuration is detected.
High No PC/PCI system configuration is detected.
TDMA mode for 440LX chipset.
GPIO4 49 Pull-up Low Bit 0 of PCI Configuration register 2Eh =1.
High Bit 0 of PCI Configuration register 2Eh =0.

MULTI-FUNCTION PIN ASSIGNMENT

Function Pin Names Pin Numbers Selection Settings
DSP Serial Interface ISCLK,IDO,IDI,ILR 48:45 PCI 52h[4] = 1 and Maestro2E_Base+36h[15]=1
EEPROM Interface ECS#,EDOUT, 43,74:72 Active during power-on reset. Turned off after reset.
EDIN,ECLK
ES978 Mixer Expansion Interface XSC,XSD 81:80 PCI 58h[2] = 1 and DOCKED pin high
General-Purpose Interface GPIO[11:0] 62:60,53:45 Maestro2E_Base+68h[11:0]
Hardware Volume Control VOLUP,VOLDN 50,49 PCI 52h[7:5] = 1x0
VOLUP,VOLDN 73,74 PCI 52h[7:5] = 1x1
I2S Interface ISCLK,ILR,IDATA 53:51 Maestro2E_Base+36h[15] = 1
Legacy Audio Interface PCGNT#,PCREQ# 61:60 PCI 50h [10:8] = 010
SIRQ# 62 PCI 40h[14] = 1
Multiple PCI Master Interface R[1:0]#,GS[1:0] 47,50,46,49 PCI 58h[0] = 1
Secondary AC’97 Interface SCLK2,SDFS2, 59, 57:55 Strap pin 57 high; strap pin 77 high
(AC’97 Extension 2.00) SDI2,SDO2
Serial CODEC Interface SCLK2,SDFS3, 59:55 Strap pin 57 high; strap pin 77 low
SDFS2,SDI2,SDO2
S/PDIF Output SPDIFO 48 (default) PCI 53h[0] = 1 and PCI 58[1] = 0
62 PCI 53h[0] = 1 and PCI 58h[1] = 1

10 SAM0151-091198 ESS Technology, Inc.

MAESTRO-2E DATA SHEET
FUNCTIONAL PIN GROUPING

FUNCTIONAL PIN GROUPING

Function Pins Pin Number
Function Pins Pin Number
I S Interface
2 ISCLK 51
ACPI Pin PME# 42 (I2SCLK) *
CODEC #1 Interface SCLK1 76 ILR 52
SDFS1 77 (I2SLR) *
SDI1 78 IDATA 53
SDO1 79 (I2SDATA) *

Clocks OSCI 64 Legacy Audio Interface PCGNT# * 60

OSCO 65 PCREQ# * 61

C24 83 SIRQ# * 62

Docking Station Interface Pin DOCKED * 58 MPU-401 Interface TxD * 80

DSP Serial Interface ISCLK * 45 RxD * 81

IDO * 46 Multiple PCI Master Interface R0# * 47

IDI * 47 R1# * 50

ILR * 48 GS0 * 46

EEPROM Interface Pins ECS * 43 GS1 * 49

ECLK * 74 PCI Bus Pins IDSEL 2

EDOUT * 72 AD[31:0] 92:99,4:11,

23:30,33:40
EDIN * 73
C/BE[3:0]# 1,13,21,31
ES978 Mixer Expansion Interface XSC * 80
Pins FRAME# 14
XSD * 81
IRDY# 15
Game Port Interface GD[3:0] 70:67
TRDY# 16
GD4 71
DEVSEL# 17
GD5 * 72
STOP# 18
GD6 * 73
LOCK# 19
GD7 * 74
PAR 20
General-Purpose I/O Pins GPIO0 * 45
CLKRUN# 43
GPIO1 * 46
RST# 84
GPIO2 * 47
INT# 85
GPIO3 * 48
PCICLK 87
GPIO4 * 49
GNT# 89
GPIO5 * 50
REQ# 90
GPIO6 * 51
Serial CODEC Interface / SDO2 55
GPIO7 * 52 Secondary AC’97 Interface SDI2 56
GPIO8 * 53
SDFS2 57
GPIO9 * 60
SDFS3 * 58
GPIO10 * 61
SCLK2 59
GPIO11 * 62
S/PDIF Output SPDIFO * 48, 62
Hardware Volume Control Pins VOLDN * 49,74
Power Pins VCC 100,86,66,
VOLUP * 50,73 54,32,12
GND 91,88,75,63,
44,41,22,3
* These pins share more than one function.

ESS Technology, Inc. SAM0151-091198 11


POWER MANAGEMENT
The Maestro-2E is a high-performance device with low
power consumption. Besides the low-power CMOS
technology used to process the Maestro-2E, various
features are designed into the device to provide benefits
from popular power-saving techniques. These features
and techniques are discussed in this section.
CLKRUN Protocol
The PCI CLKRUN feature is one of the primary methods
of power management on the PCI bus interface of the
Maestro-2E for the notebook computer. Since some
chipsets do not implement CLKRUN, this is not always
available to the system designer, and alternate power-
saving features are provided.
PCI Power Management Interface (PPMI)
The PCI Power Management Interface (PPMI)
specification establishes the infrastructure required to let
the operating system control the power of PCI functions.
This is done by defining a standard PCI interface and
operations to manage the power of PCI functions on the
bus. The PCI functions can be assigned one of five power
management states that result in varying levels of power
savings.
The five power-management states of PCI functions are:
• D0 – full power
• D1 and D2 – intermediate states
• D3 hot – off state; power supply is on
• D3 cold – off state; power supply is off
Table 1 Power-Management Registers
Register Name
Power-Management capabilities
Data PMCSR bridge support extensions
12 SAM0151-091198
MAESTRO-2E DATA SHEET
POWER MANAGEMENT
For the operating system to manage the device power
states on the PCI bus, the PCI function should support four
power-management operations:
– capabilities reporting
– power status reporting
– setting the power state
– system wake-up
The operating system identifies the capabilities of the PCI
function by traversing the new capabilities list. The
presence of new capabilities is indicated by setting bit [4]
in the PCI Status register and providing access through a
capabilities pointer to a capabilities list.
The capabilities pointer provides access to the first item in
the linked list of capabilities. For the Maestro-2E, the
capabilities pointer is mapped to an offset, C0h, indicated
in the PCI Configuration register at 34h. The first byte of
each capability register block is required to be a unique ID
of the capability. PCI power management has been
assigned an ID of 01h. The next byte is a pointer to the
next pointer item in the list of capabilities. There are no
more items in the list, so the next item pointer is set to zero.
The registers following the next item pointer are specific to
that function’s capability. The PPMI capability implements
the register block outlined in Table 1.
The Power-Management Capabilities register (PCI
Configuration register C2h in the Maestro-2E) is a static
read-only register that provides information on the
capabilities of the functions related to power-
management. The Power-Management Control/Status
register enables control of power-management states and
enables and monitors power-management events. The
Data register is an optional register that displays state-
dependent power measurements such as power
consumed or heat dissipation.
Offset
Next-Item pointer Capability ID 0
Power-Management control status (CSR) 4
ESS Technology, Inc.
MAESTRO-2E DATA SHEET
DISABLING MAESTRO-2E AUDIO

ACPI Transition Diagram

power-on reset D0
uninitia-
lized
PC
Ir
es
et

D0 pause
D2
active resume (200 µs, 100 ms)

timer e
resume (0 ms,100 ms)

so f

x
pires
t re
pause

se t
po D3cold
we
rd
ow
n d
ve
emo
r
C
VC
D1 D3hot

Figure 6 ACPI Transition Diagram

DISABLING MAESTRO-2E AUDIO

To disable Maestro-2E audio in both notebook and
motherboard implementations:
1. Set PCI 04h[2:0] = 000.
This disables Maestro-2E response to all inputs and
outputs and Bus Master cycles.
2. Set PCI 41h[7] = 1.
This disables Maestro-2E response to all legacy audio
functions.

ESS Technology, Inc. SAM0151-091198 13

 PRELIMINARY
ES1921
AC ‘97 Rev 2.1 Audio CODEC
Data Sheet

DESCRIPTION
The ES1921 CODEC is a general-purpose 18-bit stereo, full
duplex, audio codec that conforms to the analog component
specification of the Rev 2.1 AC'97 (Audio Codec 97)
Component Specification.
The ES1921 implements a high-performance accelerated PCI
audio solution when used with the ESS Maestro™ PCI Digital
Audio Controller. The ES1921 is equipped with a stereo 18-bit
DAC, a stereo 18-bit ADC, 6 line-level inputs (4 stereo and 2
mono), 3 outputs (2 stereo and 1 mono), and a Time Division
Multiplexed (TDM) serial AC-Link to a Maestro or other digital
controller.
The ES1921 may be used as a primary or secondary CODEC in
multiple codec configurations conforming to the AC'97 Rev. 2.1
specification.
The ES1921 audio CODEC can record and play back voice,
sound, and music at 48 kHz sample rate. The playback mixer has
4 stereo inputs (Line, CD, Video, Aux, and PCM digital audio)
and 2 mono inputs (Mic and Phone, plus PC beep). The record
multiplexer has 5 stereo inputs (Line, CD, Video, Aux, Mixer)
and 3 mono inputs (Mic, Phone, and Mono mix). The mixer has
3 outputs (Line, True Line Level, and Mono). Line out can be
used for stereo output to multimedia speakers while Mono out
can be used to output to a telephony subsystem or down-line
phone.
The ES1921 can be used on motherboards, add-on cards, or
PCMCIA cards. The ES1921 is available in an industry-
standard 48-pin Thin Quad Flat Pack (TQFP).
APPLICATIONS
• Multimedia PCs • Business Audio
• 3-D PC Games • Audio Conferencing
FEATURES
• Single, high-performance, mixed-signal, 18-bit stereo VLSI
chip
• Meets or exceeds Audio CODEC ’97 Rev. 2.1 performance
specifications
• Supports 2-CODEC architecture for configuration with one
ES1921 in notebook and one in docking station
• AC-Link digital serial interface (TDM format) to a Maestro or
other digital controller
Record and Playback Features
• Full-duplex stereo operation for simultaneous record and
playback
• 18-bit stereo ADC and DAC; 3rd 18-bit ADC for mic input
• 48 kHz playback and record sample rate
Inputs/Outputs
• 4 stereo inputs for line-in, CD, video, and auxiliary line-in
• 2 selectable mono inputs for microphone sharing a single mixer
input and 1 mono input for phone
• PC speaker input
• 2 stereo outputs for line-out (for example, multimedia speakers
and DVD Pure Audio)
Power
• Advanced Configuration and Power Interface (ACPI) support.
• EAPD - External Amplifier Power Down Control
• 3.3 V or 5.0 V digital and 5.0 V analog power supply (AVDD
>= DVDD)
Compatibility
• Meets Microsoft PC98 and PC99 1.0 specifications for
Baseline and Advanced Audio with FAQ updates
• Meets Intel’s Audio CODEC ’97 Rev 2.1 specifications

ES1921 Mono Out

L Mixer True Line Out
DAC
SYNC Line Out
R
PC Beep
BIT_CLK DAC
Analog Mixing Phone
Digital
RESET# and Line
Interface
Volume Control CD
SDATA_OUT L
Video
Register ADC
SDATA_IN Aux
Set R
ADC Mic1
+20 dB Mux Mic2

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 PRELIMINARY
ES1921 DATA SHEET
PINOUT

PINOUT

LINE_OUT_R
LINE_OUT_L
ANTI_POP

VREFOUT
AFILT2
AFILT1

AVDD1
AVSS1
CAP3
CAP2
CAP1

VREF
36 35 34 33 32 31 30 29 28 27 26 25
MONO_OUT 37 24 LINE_IN_R
AVDD2 38 23 LINE_IN_L
LNLVL_OUT_L 39 22 MIC2
NC 40 21 MIC1
LNLVL_OUT_R 41 20 CD_R
AVSS2 42 19 CD_GND
NC 43
ES1921 18 CD_L
NC 44 48-PIN TQFP 17 VIDEO_R
ID0 45 16 VIDEO_L
ID1 46 15 AUX_R
EAPD 47 14 AUX_L
NC 48 13 PHONE
1 2 3 4 5 6 7 8 9 10 11 12
XTL_IN

BIT_CLK
XTL_OUT

SDATA_IN

SYNC
SDATA_OUT
DVDD1

DVDD2

RESET#
PC_BEEP
DVSS1

DVSS2

Figure 1 ES1921 48-Pin Pinout

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ES1921 DATA SHEET
PIN DESCRIPTION

PIN DESCRIPTION
Name Number I/O Description
DVDD1 1 PWR Digital VDD
XTL_IN 2 I Oscillator input (24.576 MHz)
XTL_OUT 3 I Oscillator output
DVSS1 4 DGND Digital ground
SDATA_OUT 5 I AC ‘97 Serial data in
BIT_CLK 6 O Serial data clock (12.288 MHz)
DVSS2 7 DGND Digital ground
SDATA_IN 8 O AC ‘97 Serial data out
DVDD2 9 PWR Digital VDD
SYNC 10 I Fixed rate sample sync (48 kHz).
RESET # 11 I Hardware reset
PC_BEEP 12 I PC speaker out
PHONE 13 I Telephone speaker input
AUX_L 14 I Aux left channel input
AUX_R 15 I Aux right channel input
VIDEO_L 16 I Video left channel input
VIDEO_R 17 I Video right channel input
CD_L 18 I CD left channel input
CD_GND 19 I CD ground
CD_R 20 I CD right channel input
MIC1 21 I First microphone input
MIC2 22 I Second microphone input
LINE_IN_L 23 I Line-in left channel input
LINE_IN_R 24 I Line-in right channel input
AVDD1 25 PWR Analog VDD
AVSS1 26 AGND Analog ground
VREF 27 I DAC reference voltage filter capacitor
VREFOUT 28 O Mic reference voltage output (2.5 V, 1.25 mA)
AFILT1 29 O Anti-Aliasing Filter Cap - ADC channel
AFILT2 30 O Anti-Aliasing Filter Cap - ADC channel
CAP1 31 O Analog output hold-off delay
CAP2 32 O ADC Reference Capacitor
CAP3 33 O Anti-Pop Power Sustain Delay
ANTI_POP 34 O Anti-Pop Output Ground Shunt Control
LINE_OUT_L 35 O Line Out Left Channel
LINE_OUT_R 36 O Line Out Right Channel
MONO_OUT 37 O Mono out
AVDD2 38 PWR Analog VDD
LNLVL_OUT_L 39 O True Line Level Output Left Channel
NC 40 NC No connect
LNLVL_OUT_R 41 O True Line Level Output Right Channel
AVSS2 42 AGND Analog ground
NC 43, 44, 48 NC No connect
ID0 45 I Multi-CODEC ID select - bit 0
ID1 46 I Multi-CODEC ID select - bit 1

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 PRELIMINARY
ES1921 DATA SHEET
FUNCTIONAL DESCRIPTION

Name Number I/O Description

EAPD 47 O External Amplifier Power Down

FUNCTIONAL DESCRIPTION
This section shows the overall structure of the ES1921 and The major subunits of the ES1921 are shown in Figure 2 and
discusses its major functional subunits. described briefly in the following paragraphs.

DVSS DVDD

AVDD
CD
LINE_IN
RECORD AVSS
VIDEO SOURCE
AUX
MIC1
PREAMP/MIC BOOST PLAYBACK
MIC2
PHONE MIXER

PC_BEEP ID[1:0]
PCM-out DACs
RESET# Left 18-BIT
BIT_CLK DACDAC
STEREO
SYNC
SDATA_IN RIght 18-BIT
MONO_OUT
SDATA_OUT STEREO
DACDAC
MONO
18-BIT Left VOL
AFILT[1:0] FILTER CTRL
ADC
AC-LINK
18-BIT Right
FILTER
ADC
LNLVL
PCM-in ADCs MASTER
VOL
CTRL

VREF
VREFOUT LINE_OUT
REF GEN POWER MGMT
MASTER
VOL
CTRL

XTL_IN XTL_OUT EAPD ANTI_POP

Figure 2 ES1921 Block Diagram

A simplified ES1921 block diagram is given in Figure 2. The ADCs take any mix of mono or stereo sources and convert it to
ES1921 performs fixed 48K sample rate D-A and A-D a stereo PCM-in signal. All ADCs and DACs operate at 18-bit
conversion, mixing, and analog processing. Its digital interface resolution.
communicates with the AC'97 digital controller, such as an ESS
Maestro™ PCI Digital Audio controller, via the five-wire AC-
Link. Two fixed 48Ks/s DACs support two stereo PCM-out
channels. The digital mix of all sources, including the internal
synthesizer and any other digital sources, is performed in the
digital controller. The Mixer block mixes the PCM_OUT with
any analog sources, then outputs to LINE_OUT and
LNLVL_OUT. The MONO_OUT delivers either mic only or a
mono mix of sources from the mixer. The two fixed 48Ks/s

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ES1921 DATA SHEET
FUNCTIONAL DESCRIPTION

Digital Subsystems • 18-Bit stereo ADC – for audio record. Audio is returned to the
• AC-Link – a four line serial link between the ES1921 and a host via the AC-Link and the digital controller.
Maestro or other digital controller. The fifth line, RESET#, is • Record source and input volume control – input source and
linked directly to the host or to the Maestro. This link is the volume control for recording. The Mic source can be mixed
control interface for the ES1921. It also carries audio data post input volume with its own independent input volume
between the ES1921 and its digital controller. control. The recording source can be selected from one of eight
choices:
Analog Subsystems – Line In
• Playback Mixer – eight input stereo mixer. All inputs can be – CD Audio In
muted. Each of the following inputs has a 5-bit volume control: – Auxiliary In
– PCM Out (digital audio from the Maestro digital control- – Video Audio In
ler)
– Stereo mix
– Line In
– Mono mix
– CD audio In
– Mic In
– Video Audio In
– Phone
– Auxiliary In
• Output volume and mute – The output master volume
– Phone In
supports 5 bits per channel plus mute. There are separate
– Mic1 or Mic2 Mono In volume controls for mono out and stereo outs.
This input has a 4-bit volume control: • Reference generator – analog reference voltage generator.
– PC Beep Throughput • Pre-amp – 20 dB microphone pre-amplifier with bypass.
• 18-Bit stereo DAC – for audio playback of digital audio from
the Maestro digital controller.

Mixer • 2-channel input w/mono output reference (mic + stereo mix)

The ES1921 mixer is designed to the AC'97 specification to
manage the playback and record of all digital and analog audio
sources in the PC environment. These include:
• System Audio: digital PCM input and output for business,
games and multimedia
• CD/DVD: analog CD/DVD-ROM Redbook audio with
internal connections to Codec mixer
• Mono microphone: choice of desktop mic, with programmable
boost and gain
• Speakerphone: use of system mic and speakers for telephone,
DSVD, and video conferencing
• Video: TV tuner or video capture card with internal connections
to Codec mixer
• AUX/synth: analog FM or wavetable synthesizer, or other
internal source
Note: any unused input pins should have a capacitor (1 uF
suggested) to ground.
Mixer Output
The mixer generates two distinct outputs:
• a stereo mix of all sources for output to the LINE_OUT
• a stereo mix of all sources for output to the LNLVL_OUT
• a mono, mic only or mix of all sources for MONO_OUT
NOTE: Mono output of stereo mix is attenuated by -6 dB .
PC Beep Implementation
PC Beep is active on power up and defaults to an unmuted state.
The user should mute this input before using any other mixer
input because the PC Beep input can contribute noise to the
lineout during normal operation.

Mixer Input
The mixer provides recording and playback of any audio
sources or output mix of all sources. The ES1921 supports the
following input sources:
• any mono or stereo source
• mono or stereo mix of all sources

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ES1921 DATA SHEET
MIXER SCHEMATIC BLOCK DIAGRAM

MIXER SCHEMATIC BLOCK DIAGRAM

DAC
stereo line
PCM out
digital audio mono line

PC BEEP

PHONE Playback
Mixer
Bypass
MIC1
LNLVLout
MIC2 Mic Preamp Line Level
Select Volume
LINE IN Line out
-6 dB Master
Volume
CD

VIDEO Σ Mono out

Mono
AUX Mono Volume
Select
Output
Volume
and
Mute -6 dB

ADC

Record PCM in
Source digital audio
Record
Volume

Table 1 Mixer Functional Connections

SOURCE FUNCTION CONNECTION
PC_Beep PC beep pass thru from PC beeper output
PHONE speakerphone or DLP in from telephony subsystem
MIC1 desktop microphone from mic jack
MIC2 second microphone from second mic jack
LINE_IN external audio source from line-in jack
CD audio from CD-ROM cable from CD-ROM
VIDEO audio from TV tuner or video camera cable from TV or VidCap card
AUX upgrade synth or other external source internal connector
PCM out digital audio output from AC'97 digital controller AC-Link
LINE_OUT stereo mix of all sources To output jack
LNLVL_OUT Additional stereo mix of all sources To output jack
MONO_OUT mic or mix for speakerphone or DLP out to telephony subsystem
PCM in digital audio input to AC'97 digital controller AC-Link

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ES1921 DATA SHEET
TYPICAL APPLICATION (PRIMARY CODEC CONFIGURATION)

TYPICAL APPLICATION (PRIMARY CODEC CONFIGURATION)

ES1921
ID0 EAPD

ID1 ANTI_POP

AUX_L Aux In Left

AVDD1 AUX_R Aux In Right

5.0 V ± 5% .1 uF VIDEO_L Video In Left

1 uF VIDEO_R Video In Right
AVDD2
LINE_IN_L Line In Left
.1 uF
LINE_IN_R Line In Right
DVDD1 CD_L
3.3 V ± 5% .1 uF
CD In Left
CD_R CD In Right
or 5.0 V ± 5%
10 uF DVDD2 CDGND CD Ground
.1 uF PHONE Phone In

C24 MIC1 Mic1 In

XTL_IN
MIC2 Mic2 In
XTL_OUT
SDFS1 PC_BEEP PC Beep In
SYNC
SCLK1 AFILT1
BIT_CLK
560 to 1000 pF
SDO1
SDATA_OUT AFILT2
SDI1 560 to 1000 pF
SDATA_IN
GPO0
RESET#
AVSS1
Maestro
Digital Controller
AVSS2
VREF
10 µF 0.1 µF
DVSS1

DVSS2
Optional
CAP1
10 µF 10 µF VREFOUT
0.1
LNLV_L True Level
LNLV_R Line Out
CAP2
10 µF 0.1 µF
LINE_OUT_L

Optional
LINE_OUT_R
To Stereo
CAP3
22 µF Amplifier

MONO_OUT

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ES1921 DATA SHEET
ANALOG DESIGN CONSIDERATIONS

ANALOG DESIGN CONSIDERATIONS

This section describes design considerations related to inputs Power Connection
and outputs of analog signals and related pins on the chip.
The recommended power connection is shown below. Analog/
Digital power sequencing order is not critical and the chip
Reference Generator
design avoids latch-up.
Reference generator pins VREF , VREF Out, and CAP2 are
shown below.

ES1921
ES1921
10 µF
VREF
DVDD
0.1 µF 3.3 V or 5.0 V

VREF OUT

CAP2 10 µF AVDD
5.0 V
0.1 µF

Figure 3 Reference Generator Pin Diagram

Figure 5 Recommended Power Connection

Anti-Aliasing Filter
The filter pins AFILT1 and AFILT2 are shown in Figure 4.

ES1921

560 to 1000 pF
AFILT1

560 to 1000 pF
AFILT2

Figure 4 Anti-Aliasing Filter Pin Diagram

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ES1921 DATA SHEET
AC-LINK CLOCK AND RESET
AC-LINK CLOCK AND RESET
Figure 6 shows the AC-Link serial interface and the clocking
link between the ES1921 and its Maestro digital controller. All
digital audio streams and command/status information are
communicated over the AC-Link. See “Digital Interface” on
page 13 for details. AC-Link is described in the Intel Audio
Codec ‘97 Specification, which is available for download from
Intel at its web site:
http://developer.intel.com/pc-supp/platform/ac97
XTAL_IN
RESET#
Maestro SYNC
Digital BIT_CLK
ES1921
Controller
SDATA_OUT
SDATA_IN
Figure 6 ES1921's AC-Link to the Maestro Digital Controller
Clocking
The beginning of all audio frames transferred over the AC-Link
is synchronized to the rising edge of the SYNC signal driven by
the Maestro or other digital controller. Data is transmitted
through the AC-Link on every rising edge of BIT_CLK, and
subsequently sampled by the receiving side on each
immediately following falling edge of BIT_CLK.
There are three different clock inputs available to the ES1921.
The potential inputs are a Maestro digital controller, an external
crystal, and a master ES1921.
Maestro Digital Controller as Source
The ES1921 can derive its clock internally from the Maestro
digital controller through the XTAL_IN pin. See Figure 6. This
eliminates the need for an extra component. Synchronization
with the Maestro digital controller is achieved through the
BIT_CLK pin at 12.288 MHz (half of crystal frequency).
External Crystal
The clocking for the ES1921 can be derived from a 24.576 MHz
external crystal connected to the XTAL_IN and XTAL_OUT
pins. See Figure 7.
Master CODEC as Source
In cases where the ES1921 is a slave CODEC and can’t be
driven by the Maestro digital controller, its internal clocking is
derived by doubling the BIT_CLK input. The BIT_CLK input
received from master CODEC synchronizes the AC-link and
ESS Technology, Inc.
determines the clocking for the slave CODEC. If there is no
BIT_CLK input, the slave CODEC stays dead. For discussion of
this, see “Master-Slave Operation” below.
XTAL_IN
ES1921
XTAL_OUT
Figure 7 ES1921's clocking from an external crystal
Reset
There are 3 types of resets as detailed under “Timing
Characteristics”.
• a “cold” reset where all ES1921 logic including registers
is initialized to its default state
• a “warm” reset where the contents of the ES1921 register
set are left unaltered
• a “register” reset which only initializes the ES1921
registers to their default states
After signaling a reset to the ES1921, the AC'97 digital
controller should not attempt to play or capture audio data until
it has sampled a “Codec Ready” indication (bit 15 Slot 0) via
register 26h from the ES1921.
For proper reset operation SDATA_OUT should be “0” during
“cold” reset. See “Testability” section for more information.
Master-Slave Operation
Certain applications require multiple CODECs supporting a
single digital controller. For example, a notebook computer and
its docking station is such an application. In this example, a
digital controller and CODEC reside in the notebook while an
additional CODEC is in the docking station. The docking station
CODEC provides access to the audio resources available to the
docking station. These two CODECs are in a master-slave
relationship.
The master CODEC generates BIT_CLK for both the Maestro
digital controller and the slave CODEC. This ensures that all
three chips are in sync. In addition, internal chip clocking for the
slave CODEC is derived by doubling the BIT_CLK input from
the master CODEC.
The master and slave CODECs are determined by the status of
the ID pins. If either of the two ID pins is tied low, the CODEC
is a slave.
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ES1921 DATA SHEET
AC-LINK CLOCK AND RESET

Table 2 CODEC Master-Slave Relationship (External Pins) Table 3 Maestro-2E/ES1921 Pin Assignments
ID0 ID1 CODEC Relationship Master
Maestro-2E
DVDD or Floating DVDD or Floating Master Interface ES1921
Pin Name Pin Name
GND DVDD or Floating GPO0 RESET#
SCLK1 BIT_CLK
DVDD or Floating GND Slave Master SDFS1 SYNC
CODEC SDI1 SDATA_IN
GND GND SDO1 SDATA_OUT
C24 XTAL_IN
The Maestro-2E digital controller provides for two CODEC
Maestro-2E Slave ES1921
interfaces. For an example, see Figure 8 below. Interface
Pin Name Pin Name
GPO3 RESET#
SDI2 SDATA_IN
SDO2 SDATA_OUT
Slave
CODEC

SDFS2 SYNC
SCLK2 BIT_CLK

Notebook ES1921 (Master)

C24
SDFS1 SYNC XTAL_IN
SCLK1 BIT_CLK
SDO1 SDATA_OUT
ID0
SDI1 SDATA_IN
GPO0 RESET# ID1

Maestro-2E

SDFS2 SYNC XTAL_IN

SCCK2 BIT_CLK
SDO2 SDATA_OUT ID0
SDI2 SDATA_IN
GPO3 RESET# ID1

Docking Station ES1921 (Slave)

Maestro-2E and Dual ES1921s for Notebook Plus Docking Station Configuration
Figure 8 Example of Dual CODEC Design

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