Professional Documents
Culture Documents
% Deedy CV/Resume
% XeLaTeX Template
% Version 1.0 (5/5/2014)
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% This template has been downloaded from:
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% Original author:
% Debarghya Das (http://www.debarghyadas.com)
% With extensive modifications by:
% Vel (vel@latextemplates.com)
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% License:
% CC BY-NC-SA 3.0 (http://creativecommons.org/licenses/by-nc-sa/3.0/)
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% Important notes:
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\begin{document}
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% TITLE SECTION
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% Education
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\section{Education}
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\section{Coursework}
\subsection{Graduate}
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% Skills
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\section{Skills}
\subsection{Programming}
Verilog \\
SystemVerilog \\
C basics \\
TCL (CLI)
\subsection{TOOL}
Vim \\
Eldo(Mentor Graphics) \\
LT- spice \\
Xillinx \\
Questa Sim
\section{ACHIEVEMENTS}
IEEE Conference resarch paper on Implementation of Probability Using FIR filter.
(2014) \\
IEEE resarch paper on Performance Optimization of Digital CMOS logic circuits using
LE theory and APSO.(2019) \\
GATE Percentile 98.67(2016) \\
GATE Percentile 98.53(2018)
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% Experience
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\section{Experience}
\runsubsection{TRUECHIP SOLUTIONS}
\descript{| Training}
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\section{PROJECT}
\runsubsection{DESIGN AND VERIFICATION OF 8b9b ENCODER}
\location{May 2019 – July 2019 | Noida, UP}
\begin{tightitemize}
\item Encoding 8bit into 9bit and writing DUT using SystemVerilog.
\item A verification environment is created using UVM methodology to verify the
correct functionality of DUT.
\end{tightitemize}
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\section{Research}
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% Awards
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\section{POSITION OF RESPONSIBILITY}
\runsubsection{NSIT- NEW DELHI}
\descript{| TEACHING ASSISTANTSHIP}
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% Societies
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