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TL431LI-Q1
TL432LI-Q1
SNVSBA4A – MAY 2019 – REVISED NOVEMBER 2019
Vref
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL431LI-Q1
TL432LI-Q1
SNVSBA4A – MAY 2019 – REVISED NOVEMBER 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 9.4 Device Functional Modes........................................ 12
2 Applications ........................................................... 1 10 Applications and Implementation...................... 13
3 Description ............................................................. 1 10.1 Application Information.......................................... 13
4 Revision History..................................................... 2 10.2 Typical Applications .............................................. 13
10.3 System Examples ................................................. 22
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 3 11 Power Supply Recommendations ..................... 25
7 Specifications......................................................... 4 12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
7.1 Absolute Maximum Ratings ...................................... 4
12.2 Layout Example .................................................... 25
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4 13 Device and Documentation Support ................. 26
7.4 Thermal Information .................................................. 4 13.1 Device Support...................................................... 26
7.5 Electrical Characteristics........................................... 5 13.2 Documentation Support ........................................ 26
7.6 Typical Characteristics .............................................. 6 13.3 Related Links ........................................................ 26
13.4 Receiving Notification of Documentation Updates 26
8 Parameter Measurement Information .................. 9
13.5 Support Resources ............................................... 26
8.1 Temperature Coefficient............................................ 9
13.6 Trademarks ........................................................... 27
8.2 Dynamic Impedance ............................................... 10
13.7 Electrostatic Discharge Caution ............................ 27
9 Detailed Description ............................................ 11
13.8 Glossary ................................................................ 27
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 11 14 Mechanical, Packaging, and Orderable
Information ........................................................... 27
9.3 Feature Description................................................. 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
CATHODE 1
REF 1
3 ANODE
3 ANODE
REF 2
CATHODE 2
Pin Functions
PIN NUMBER
NAME TL431LI-Q1 TL432LI-Q1 TYPE DESCRIPTION
DBZ DBZ
ANODE 3 3 O Common pin, normally connected to ground
CATHODE 1 2 I/O Shunt current/Voltage input
REF 2 1 I Threshold relative to common anode
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VKA Cathode Voltage (2) 37 V
IKA Continuos Cathode Current Range –10 18 mA
II(ref) Reference Input Current –5 10 mA
TJ Operating Junction Temperature Range –40 150 C
Tstg Storage Temperature Range –65 150 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ANODE, unless otherwise noted.
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification
(1) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ can affect reliability. Please see the Semiconductor and IC
Package Thermal Metrics Application Report for more information.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report.
(1) The deviation parameters VI(dev) and II(dev) are defined as the differences between the maximum and minimum values obtained over the
rated temperature range. For more details on VI(dev) and how it relates to the average temperature coefficient, see the Temperature
Coefficient section.
(2) The dynamic impedance is defined by |ZKA| = ΔVKA/ΔIKA. For more details on |ZKA| and how it relates to VKA, see the Temperature
Coefficient section.
2520 0.5
Vka = Vref IKA = 1 mA
2515 IKA = 1 mA
Vref - Reference Voltage - mV
2505
0.3
2500
2495
0.2
2490
2485 0.1
2480
2475 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TA - Free-Air Temperature - °C Book
TA - Free-Air Temperature - °C
Figure 1. Reference Voltage versus Free-Air Temperature Figure 2. Reference Current versus Free-Air Temperature
15 0.064
VKA = Vref VKA = 36 V
0.048
9
0.04
6 0.032
0.024
3
0.016
0 0.008
-3 0
0 0.5 1 1.5 2 2.5 3 -50 -25 0 25 50 75 100 125 150
VKA - Cathode Voltage -V TA - Free-Air Temperature - °C
D003
Figure 4. Off-State Cathode Current
Figure 3. Cathode Current versus Cathode Voltage
versus Free-Air Temperature
-0.35 75 200
AV - Small-Signal Voltage Amplification - dB
VKA = 3 V to 36 V Gain
-0.4 Phase
-0.45 60 160
'Vref / 'VKA = mV/V
-0.5
Phase - Degrees
45 120
-0.55
-0.6
30 80
-0.65
-0.7
15 40
-0.75
-0.8 0 0
-50 -25 0 25 50 75 100 125 150 100 1k 10k 100k 1M 10M
Temperature (°C) D006 f - Frequency - Hz Gain
Figure 5. Ratio of Delta Reference Voltage to Delta Cathode Figure 6. Small-Signal Voltage Amplification
Voltage versus Free-Air Temperature versus Frequency
GND 0.1
1k 10k 100k 1M
f - Frequency - Hz
Figure 7. Test Circuit for Voltage Amplification Figure 8. Reference Impedance versus Frequency
1 kΩ 6
TA = 25qC
Output Input
5
50 Ω 3 Output
−
2
+
GND 1
0
-1 0 1 2 3 4 5 6 7
t - Time - Ps puls
Figure 9. Test Circuit for Reference Impedance Figure 10. Pulse Response
220 Ω 15
A VKA = Vref
Output B VKA = 5 V
12 C VKA = 10 V
IKA - Cathode Current - mA
f = 100 kHz
6
GND
3
0
0.001 0.01 0.1 1 10
CL - Load Capacitance - µF Copy
TL43
The areas under the curves represent conditions that may cause the
device to oscillate. For curves B and C, R2 and V+ are adjusted to
establish the initial VKA and IKA conditions, with CL = 0. VBATT and CL
then are adjusted to determine the ranges of stability.
Figure 11. Test Circuit for Pulse Response
Figure 12. Stability Boundary Conditions for All TL431LI-Q1,
TL432LI-Q1 Devices
IKA
+
CL VBATT
−
IKA
R1 = 10 kΩ 150 Ω
CL
+
R2 VBATT
−
Vref
Input VKA
IKA
R1 Iref
R2 Vref æ R1 ö
VKA = Vref ç 1 + ÷ + Iref × R1
è R2 ø
Input VKA
Ioff
αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the
lower temperature. The full-range temperature coefficient is an average and therefore any subsection of the rated
operating temperature range can yield a value that is greater or less than the average. For more details on
temperature coefficient, refer to the Voltage Reference Selection Basics White Paper.
Itest
P/
IKA
IKA(min)
0 VKA (V)
Ps
Figure 17. Dynamic Impedance
9 Detailed Description
9.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications, ranging from power
to signal path. This is due to its key components containing an accurate voltage reference and op amp, which
are very fundamental analog building blocks. TL43xLI-Q1 is used in conjunction with its key components to
behave as a single voltage reference, error amplifier, voltage clamp or comparator with integrated reference.
TL43xLI-Q1 can be operated and adjusted to cathode voltages from 2.495 V to 36 V, making this part optimal for
a wide range of end equipments in industrial, auto, telecom and computing. In order for this device to behave as
a shunt regulator or error amplifier, >0.6mA (Imin(max)) must be supplied in to the cathode pin. Under this
condition, feedback can be applied from the Cathode and Ref pins to create a replica of the internal reference
voltage.
Various reference voltage options can be purchased with initial tolerances (at 25°C) of 0.5% (denoted by B), and
1% (denoted by A). TL431LI-Q1 and TL432LI-Q1 are both functionally the same, but have different pinout
options.
CATHODE
REF +
_
Vref
ANODE
CATHODE
REF
ANODE
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
Rsup
Vout
CATHODE
R1
VL
RIN
VIN REF
+
R2
2.5V
ANODE
10.2.3.1.1 Overdrive
Slow or inaccurate responses can also occur when the reference pin is not provided enough overdrive voltage.
This is the amount of voltage that is higher than the internal virtual reference. The internal virtual reference
voltage is within the range of 2.495 V ±(0.5% or 1.0%), depending on which version is being used. The more
overdrive voltage provided, the faster the TL43xLI-Q1 responds.
For applications where TL43xLI-Q1 is being used as a comparator, it is best to set the trip point to greater than
the positive expected error (that is +1.0% for the A version). For fast response, setting the trip point to >10% of
the internal VREF suffices.
For minimal voltage drop or difference from Vin to the ref pin, TI recommends to use an input resistor <10 kΩ to
provide Iref.
3
2.5
2
1.5
1
Vin
0.5 Vka(Rsup=10k:)
0 Vka(Rsup=1k:)
-0.5
-0.001 -0.0006 -0.0002 0.0002 0.0006 0.001
Time (s) D001
Figure 21. Output Response With Various Cathode Currents
VCC VCC
R1 = I
OUT
IKA
hFE
VREF
IOUT =
RS
VCC
IOUT
R1
TL431LI-Q1
RS
GND
10.2.6.2.3 Stability
Though TL43xLI-Q1 is stable with no capacitive load, the device that receives the output voltage of the shunt
regulator can presents a capacitive load that is within the TL43xLI-Q1 region of stability, shown in Figure 12.
Also, designers can use capacitive loads to improve the transient response or for power supply decoupling.
When using additional capacitance between Cathode and Anode, refer to Figure 12. Also, the Understanding
Stability Boundary Conditions Charts in TL431, TL432 Data Sheet Application Note provides a deeper
understanding of this devices stability characteristics and aids the user in making the right choices when
choosing a load capacitor.
12
9
6
3
0
-3
-6
-5E-6 -3E-6 -1E-6 1E-6 3E-6 5E-6
Time (s) D001
Figure 24. TL43xLI-Q1 Start-Up Response
VIN AC VOUT
VDD
VPC VSC
VDD HV
UCC28740 UCC24636
PWM Controller SR Controller
VS
DRV
DRV TBLK
FB CS
GND TL431LI-Q1
Rs
Error|Iref R1 = 40.2 NŸ
IREF
TL431LI-Q1
Error|Vref R2 = 8.06 NŸ
2N222
30 Ω
0.01 µF 4.7 kΩ
TL431LI-Q1 VO
R1
R2 æ R1 ö
0.1% VO = ç 1 +
0.1% ÷ Vref
è R2 ø
VI(BATT)
IN
OUT
uA7805 VO
Common R1
(
VO = 1 + R1 Vref (
R2
TL431LI-Q1 Minimum V V + 5V
O = ref
R2
VI(BATT) VO
R1 (
VO = 1 + R1 Vref (
R2
R2 TL431LI-Q1
VI(BATT) VO
R1
TL431LI-Q1
C
(see Note A)
R2
Refer to the stability boundary conditions in Figure 12 to determine allowable values for C.
IN OUT
VI(BATT) LM317 VO ≈5 V, 1.5 A
8.2 kΩ Adjust
243 Ω
0.1%
TL431LI-Q1
243 Ω
0.1%
VI(BATT) VO ≈5 V
Rb
(see Note A) 27.4 kΩ
0.1%
TL431LI-Q1
27.4 kΩ
0.1%
12 V
VCC
6.8 kΩ
5V 10 kΩ
−
10 kΩ
+
0.1% TL598
X
TL431LI-Q1 Not
10 kΩ Used
0.1%
Feedback
R3
(see Note A)
VI(BATT)
R4
R1A R1B
(see Note A)
Low Limit = 1 + R1B V ref
R2B
TL431LI-Q1
High Limit = 1 + R1A V ref
R2A
LED on When Low Limit < VI(BATT) < High Limit
R2A R2B
Select R3 and R4 to provide the desired LED intensity and cathode current ≥0.6 mA to the TL431LI-Q1 at the
available VI(BATT).
650
12 V
R 2 k
TL431LI-Q1
On C 12 V
Off Delay = R × C × ln
12 V – Vref
RCL IO
0.1% V ref
VI(BATT) Iout = + IKA
R CL
R1 V I(BATT)
TL431LI-Q1 R1 = I
O
h FE + IKA
VI(BATT)
IO
Vref
IO =
RS
TL431LI-Q1
RS
0.1%
12 Layout
CL
GND
TL431LI X X XXX X XX
13.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TL431LIAEDBZRQ1 ACTIVE SOT-23 DBZ 3 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 150 23CP
TL431LIAQDBZRQ1 ACTIVE SOT-23 DBZ 3 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 22TP
TL431LIBEDBZRQ1 ACTIVE SOT-23 DBZ 3 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 150 23DP
TL431LIBQDBZRQ1 ACTIVE SOT-23 DBZ 3 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 22UP
TL432LIAEDBZRQ1 ACTIVE SOT-23 DBZ 3 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 150 23EP
TL432LIAQDBZRQ1 ACTIVE SOT-23 DBZ 3 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 22VP
TL432LIBEDBZRQ1 ACTIVE SOT-23 DBZ 3 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 150 23FP
TL432LIBQDBZRQ1 ACTIVE SOT-23 DBZ 3 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 22WP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2020
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2020
Pack Materials-Page 2
PACKAGE OUTLINE
DBZ0003A SCALE 4.000
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
2.64 C
2.10
1.12 MAX
1.4
B A
1.2 0.1 C
PIN 1
INDEX AREA
0.95 (0.125)
3.04
1.9 2.80
3
(0.15)
NOTE 4
2
0.5
3X
0.3
0.10
0.2 C A B (0.95) TYP
0.01
0.25
GAGE PLANE 0.20
TYP
0.08
0.6
TYP SEATING PLANE
0 -8 TYP 0.2
4214838/D 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
4. Support pin may differ or may not be present.
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EXAMPLE BOARD LAYOUT
DBZ0003A SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
(R0.05) TYP
(2.1)
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
4214838/D 03/2023
NOTES: (continued)
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EXAMPLE STENCIL DESIGN
DBZ0003A SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
(R0.05) TYP
(2.1)
4214838/D 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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