Digital LDO Modelingfor Early Design Space
Exploration
Stefan Leitner, Paul West, Chao Lu and Haibo Wang
Dept. of Electrical and Computer Engineering, Southern Illinois University Carbondale, Illinois USA 62901
Abstract-Digital low dropout (LDO) voltage regulators have
been widely used in the latest low-power circuits that involve jine­
grain power management. Due to the mixture of discrete- and
continuous-time operation as well as the nonlinear comparator gain,
it is difficult to derive the closed-loop transfer function for a digital
LDO The use of its open-loop transfer function is also limited due to
the non-constant feedback factor. Thus, it is not easy to predict
digital LDO performance in the early design stage, which limits
designer's capability to effectively explore the design space. This
paper presents closed-form expressions for estimating critical
performance parameters of digital LDO circuits, such as settling time
and peak control error. The accuracy of the predictions is validated
by comparing with circuit simulation results. The derived formulas
can be used by designers or integrated into design automation tools.
Keywords-Digital Low dropout regulator; power management;
voltage regulator; low-power design
L INTRODUCTION
Digital low dropout (LDO) voltage regulators have been
widely used in latest low-power circuits that involve fine-grain
power management [1-2], Traditionally, LDO circuits are
implemented in analog domain using a high-gain amplifier to
sense the difference, denoted by Vern between the LDO output
and the reference voltage level. Subsequently, the amplifier
output is used to control the gate voltage of the power device,
which bridges the input power supply and the LDO output.
These components form a feedback loop to keep the LDO
output at the reference level. High amplifier gain is required to
reduce Verr in steady state, With the scaling down of power
supply, it becomes increasingly challenging to design power­
efficient high-gain amplifiers, This instigates the recent
development of digital LDO circuits [3-8],
The hallmark of digital LDOs is to replace the high-gain
amplifier with other circuits, such as comparators [3], voltage
controlled oscillators [4], etc., for detecting Verr . Among these
approaches, the comparator-based design has attracted more
interest from the design community, partially due to its
relatively simple structure. The second common feature of
digital LDOs is that an array of small power devices is used,
Thus, digital codes can be utilized to control the equivalent on­
resistance of the power device array. This represents another
significant deviation from analog LDOs, which use a large
single power device and its on-resistance is controlled by the
device gate voltage, Figure 1 shows a simplified digital LDO
circuit to illustrate its operation [3], The operation of the
comparator and digital control circuit is synchronized by a
clock The output code of the digital circuit governs how many
PMOS power devices are conducting. To minimize the impact
of switching glitches, thermometer coding is typically used at
978-1-5090-1367-8/16/$31.00 ©2016 IEEE
the output of the control circuit. If the comparator indicates that
Vout < Vret, the control logic increases the number of
transistors that are conducting; otherwise, it reduces the
number of conducting transistors. By this mechanism, the
digital LDO keeps the output voltage at the reference level.
Digital
Control
Logic
CIK
Vout
Figure 1 A simplified digital LOO circuit
The comparator is much simpler and potentially consumes
significantly less power compared to the error amplifier used in
analog LDOs. However, it also provides less information for
controlling purposes. In analog LDO circuits, the error
amplifier output is proportional to Verr . When Verr is large, the
error amplifier output can dramatically change the gate voltage
of the power device. In digital LDO circuits, the comparator
output, 1 or 0, only tells the relation between Vout and Vret, but
not the magnitude of Verr . Therefore, the above simple LDO
circuit cannot respond quickly even if there is a large
difference between the output and reference level. To address
this problem, several transient response enhancement
techniques are presented in literature [1,2,4-8]. For example,
additional comparators can be added to detect if Verr exceeds
pre-selected thresholds. If so, the digital circuit will update the
control code with increased step sizes. Also, a fast clock can be
used to improve digital LDO output transition speed.
The use of comparators also complicates the modeling of
digital LDO circuits. As mentioned above, the comparator
output is not proportional to Verr . Thus, the feedback factor of
the control loop in digital LDOs is not constant, making it
difficult, if not impossible, to derive the closed-loop transfer
function. Although the open-loop transfer function of a digital
LDO circuit can be easily derived, its effectiveness on
predicting system stability, settling time, peak voltage
deviation, etc., is limited. This is because previous estimation
equations based on the system open-loop transfer functions are
developed with the assumption of a constant feedback factor,
which is not true in comparator-based digital LDO circuits.
The lack of analytical digital LDO system models significantly
limits the designers' capability to estimate digital LDO
7
performance at the early design stage and poses a stiff
challenge on design space exploration. Since the optimization
problem depends on a number of variables, locating an ideal
set of parameters is limited to time consuming simulations.
T�i� paper presents closed-form expressions for estimating
cntlcal performance parameters of digital LDO circuits, such
as settling time and peak control error. This allows an
immediate assessment of the trend of any parameter change
and enables simple evaluation of approximate design
parameters. The accuracy of the predictions is validated by the
comparison with circuit simulation results. The derived
formulas can be directly used by designers or integrated into
design automation tools.
The rest of the paper is organized as follows. Section 2
reviews previous efforts on analyzing and modeling digital
LDOs from a system perspective. The developed estimation
methods are presented in Section 3. The comparison between
estimations and circuit simulation results are discussed in
Section 4 and the paper is concluded in Section 5.
11. RELATED WORK
The control logic of a digital LDO operates in discrete-time
manner, which can be modeled by z-domain expressions.
Meanwhile, the circuit at the LDO output node is a continuous­
time circuit that can be conveniently described by an s-domain
function. Due to the lack of methods to directly analyze hybrid
transfer functions that contain both z-domain and Laplace
�ariables, digital LDO models presented in literature [5,6]
mvolve transforming a portion of the circuit model from one
domain to the other. Figure 2 shows the system-level model of
the digital LDOs, in which the digital control logic is
implemented by bi-directional shift registers [6]. Note that the
number of zeros in the shift register output is effectively the
accumulation of the comparator output over time (-1 or 1 is
accumulated depending on the comparator output). Thus, the
digital control logic can be modeled by a digital integrator,
followed by a zero-order hold block. At the output node, output
resistance R and load capacitance C form a first-order linear
system with the transfer function �, where
1+-­
Wout
at the output node of the circuit and Wout =
R·C
__
1 .
1 -Ts
V , ef -e
s
Figure 2 System-level model of digital LOO
By translating the s-domain expressions into z-domain
functions, the z-domain open-loop transfer function of the
digital LDO can be derived as [6]:
C · C
D A
TF(z ) = w
(z - 1) ( z - e- fC�t )
where CDis the gain of the digital control circuit and [elk is the
clock frequency of the circuit. It shows the open-loop transfer
function has two poles: one is located at the unit cycle and the
Wout
other is at e- t elk. The expression of the second pole reveals
some insights into the digital LDO operation. For example, if
the load current decreases, R becomes larger and Wout
becomes smaller. As a result, the second pole approaches the
unit cycle and the digital LDO more likely experiences reduced
damping factor and increased settling time [6]. Because of the
comparator, the feedback factor in digital LDOs does not
remain constant during circuit operation. Thus, the previously
established procedures to estimate settling time and peak
control error from pole locations for feedback systems with
constant feedback factors cannot be used for digital LDOs. Due
to the same reason, the usefulness of the root locus method is
also limited for digital LDO circuits.
For the system-level model shown in Figure 2, if we
replace Z-1 by e-S/felk and also consider the zero caused by
the equivalent series resistance (ESR) RESR of the load
capacitor, the open-loop transfer function can be written in s­
domain as:
s s
e-felk 1 +w­
TF(s) = C . s
__ . __
1 +...£
z
(2)
w
p
1 1
where Wz = __ W = (R+R - """ Wout , and C IS
· the
RESE.C ' P )
ESE C
combined gain contributed by the digital control logic and the
analog circuit at the LDO output node. This is similar to the
transfer function used in digital LDO stability discussion in [5].
If the clock frequency is much higher than the natural
5
frequency of the LDO system, the effect of term e-t elk can be
ignored. Then, the system has a pole at the origin and another
at -wp• The LDO stability in two circuit configurations is
discussed in [5] with the help of the s-domain transfer function.
In the first case, the load capacitance is small such that W is
much higher than the unit gain frequency of the open-l�op
transfer function. Then, the stability of the digital LDO is
guaranteed. In the second case, the load capacitance is very
large and wp is smaller than the unit gain frequency. In this
C is the gain
A scenario, the digital LDO needs to be compensated by the ESR
induced zero to achieve stable operation. The s-domain model
faces the same challenge as the z-domain model, which is that
the feedback factor is not constant during circuit operation.
Thus, it is difficult to use the pole position or phase margin of
s
1+ ­ the s-domain open-loop transfer function to estimate the
())out
settling time and peak deviation from the reference voltage.
In summary, the open-loop transfer functions help identify
Output factors that affect digital LDO stability and its transient
responses. However, they cannot be used to estimate critical
performance parameters due to the non-constant feedback
factors in digital LDOs. The lack of such capability hinders
designers' efforts to effectively perform early design space
exploration. This motivates the work to be discussed in the
next section.
Ill. DIGITAL LDO PERFORMANCE ESTTMA TION
(1) The following discussion analyzes the LDO response to
load changes by modeling the system behavior with a
continuous time model. In the derivations, IpMOS denotes the
current conducted by a single power device and l1iload
8
represents the load current change. The other notations, [elk, R
lliload
and C are introduced in the previous section. R can be Iload (S)= (7)
estimated by ron sw/n, where n is the number of conducting S
-­

power device and ron sw is the on-resistance of a single power
device. Alternatively, R can be calculated by the ratio of
voltage drop llVss over the load current iLss.
VDD
Figure 3 Circuit level (left) and small signal model (right) of the LDO output
node
A schematic of the analog output node of the LDO is
depicted on the left of Figure 3. Current is supplied to the
node by a number of PMOS transistors in parallel. The load is
comprised by a current source and a parallel capacitor. In the
Substituting the above relations into (4) yields:
( IPMOS. [elk - S· lliload). R
Vout,(s)= (8)
S2. (1+s ·R . C)
The impulse response of (8) is the response of the LDO output
node when the load current increases instantaneously by
lliload. This is because the system input itself has already been
incorporated into the transfer function and the Laplace
transform of the impulse function is 1. Note that this model
holds true until the output voltage crosses the 0 level (the ideal
steady state level) the fIrst time after the initial transition at
t=O. This is because the comparator output changes after the
output voltage crosses the 0 level. Since the model needs to be
modifIed slightly each time the comparator changes its output
value, we partition the LDO output response into different
regions, which are partitioned by the time instants that the
LDO output crosses 0 as illustrated in Figure 4. In Equation
(8) and the following expressions, numbers in footnotes are
used to indicate the regions that are being considered.
v

/T"" k
small signal model on the right of Figure 3, the PMOS power
devices are modeled by a current source and a parallel resistor.
iin(t) is the sum of PMOS device currents and R is the
equivalent on resistance of the conducting devices at a VPEAKI \\ tpeab tpeak2
I
/
particular steady state condition. Performing small signal (
I
analysis at the analog node, we have: tl I t
. vout (t) d(vout (t))
lm (t) - lload (t)+C. (3) tpeakl
. _ .
_

R dt
with iload (t) denoting the load current. Performing Laplace Figure 4 Notation of waveform quantities used in the derivations
transform on (3) and solving for Vout (s) yield:
Performing partial fraction expansion simplifIes (8) to:
Vout (S)=
( lin(S) - hoad (S))·R (4) X Y Z
l+s. R. C Vout,(S)=�+ 2+ (9)
S 1+S. R . C
In order to obtain the LDO response (closed loop response) to
a load change, Vout (s) is obtained by the sum of the system Comparing the coeffIcients for unknown constants Xl, YI and
responses to changes in lin(s) and Iload (s), thus their Zl gives respectively:
difference lin(S) - Iload (S) is treated as the system input. X = - lli1oad · R - IpMOS. [elk · R2. C
The following discussion estimates the system behavior for Y=IpMOS. [elk·R (10)
a step increase of iload by lliload. The response to a decrease
of load current by the same magnitude can be obtained by Z=lli10ad . R2. C+IpMOS. [elk · R3. C2
multiplying vout (t) by -1. When iload increases, vout
decreases, and the feedback loop with comparator and shift Performing inverse Laplace transform gives the LDO output
register (integrator) responds by increasing the number of voltage in time domain:
conducting PMOS devices at a rate that is equal to [elk . In the Z t
continuous time model, iin (t) can be approximated by a ramp Vout,(t)=X+Y · t+ e-R-e (11)
R. C
input with slope:
dCiin(t)) = iPMOS· {elk· R - (lliload· R + iPMOS· {elk· R2• C)· (1- e-Rte)
=IpMOS. [elk (S)
dt The maximum deviation from the reference voltage occurs
Thus lin(s) and Iload (s) can be modeled respectively by: when vout,(t) reaches its minimum:

- IpMOS. [elk d(voutl (t)) X _t peakl

Im (S)= (6) --'-'--=---- =Y+-- e R-e =0 (12)
S2 dt R ·C
- -

9
The time between the load step and the peak voltage deviation Similarly, the peak values for the first few oscillations can be
is denoted by t peak l and is expressed as: calculated. It indicates that their magnitudes follow an
exponentially decaying function of the form:
-X t
t peak l = R · C 'in ( y ' R , c ) (13)
Venvelope (t) = M·e-ao (22)

where M and a can be found using the location and

= R · C ·in (IPMOS [elk' R . C +l:1iload
.

IpMOS . [elk' R . C
) magnitudes of the fust two extreme values of the system
response as follows (Note that the negative of VPEAK , is
The maximum deviation from the desired output voltage is included in (23) since Vpeak , is negative due to the load
therefore Vout,(t peak ,): increase):

VPEAK , = - R 'l:1iload -VPEAK , = M. e-a·tpeak, (23)

(14)
1
PMOS t.elk. . R2. C . in
(/PMOS' [elk' R C +l:1iload) . VPEAKz - 'C
- M·e-a tree, Hpeakz) (24)
+
IPMOS t.elk R. C . .
This however requires solving equations numerically, since it
Denote the time that VOUt,(t) = 0 as recovery time t ree , as is not possible to solve t ree , explicitly. Thus, no closed form
shown in Figure 4. After t ree" the control error becomes formula can be derived using this strategy.
positive, since vout becomes larger than the reference voltage. To overcome this problem, an imaginary system response
Comparator and shift register respond with a decrease of iin' for t < 0 (before the actual load change occurs) can be
The input to the differential equation (DEQ) for the next constructed, which is illustrated by the dash line in Figure 4.
region (Region 2) is therefore -iin(t) with an equivalent So the question is, how would the waveform for t < 0 have to
offset 61, which corresponds to the integral value of the input look like in order to result in the system response vout (t) for
current minus the load current during Region 1 (from t = 0 to t � 0 that is calculated above? The imaginary system
t = t ree') . The governing equations with unknown 61 are: response for -t = t/ is governed by equations:
dv/ (t/) v/ (t/)
v
outz (s) -
_
(61 (s ) - lin(S))' R
1 + S . R. C
(15) C. --- = 6/ -
do
IpMOS [elk' t/ + --
.
R
t V/CO) = 0
voutz (t) = -y. t - X* . 1- e-R c ( ) (16)
dv/CO) d(voutl ( 0))
(25)

= -lpMos' {elk' R· t + (61' R + IpMos' {elk' R2• C)· (1- e-R c� ) dt/ dt
where (15) and (16) describe the output voltage for Region 2 with v/Ct/) as the imaginary LDO response for t < 0 .
in frequency- and time domain respectively. Solving them in a Equation (25) is almost equivalent to Equation (1) for a
similar way as (8) and (11). 61 can be found by equating the negative load step, thus iinCt/) is negative and 6/ is unknown.
derivatives of VOUt,( t ree ,) and Voutz ( 0): The only difference lies in the term containing R whose sign
VoutCt)
x _� has to be swapped. Unlike in the t - domain, where
X* 61 R
Y+ -y -y + C + IpMos' {elk' R t
acts towards lowering the maximum control error, v/C /)
e R· e -
R. C R. C
= =

(17) R
supports deviations from Vret in the t/ - domain. Therefore,
Solving for 61 yields: the system has a negative damping coefficient for t < O . The
tree, initial condition assures a smooth transition between the
= 2·y. C + Re-� - IpMOS' [elk' R ·C
X
61 (18) solutions at -t = t/ = O . This leads to:

= IpMOS' [elk' R · C· ( 1- e-�) -l:1iloade-�

tree1 tree1 d(vout1 ( 0)) l:1iload (26)
dt C
Since 61 is the difference of integrated input current and load
current, it must also hold that: Then DEQ (27) and its Laplace transform (28) are obtained
for the imaginary system:
(19)

Subsequently, t peakz and VPEAKz can be solved similar to (13)

dv/Ct/)
�=C
(l:1lload
1 .
.
V/Ct/)
- IpMOS [elk' t/ + --) (27)
R
and (14): (S ·l:1iload - IpMOS [elk) . R
.
Vout (S) -
. IPMOS [elk' R. C + 61)
(28)
C in (
2
_

. / S . (S . R. C - 1)
t peakz - R .
IPMOS t.elk R. C (20)
_

. . Similarly as earlier derivations, perfonning partial fraction

VPEAKz R . 61 - IpMOS. {elk' R2. C. In

/PMOS. {elk' R. C + 61 ( )
expansion and inverse Laplace transform yields:
IPMOS. }elk'
F R. C
=

(21)

10
 Xl Yl Zl IV. COMPARISON WITH SIMULATION RESULTS
Vout/ S) = -S + s2 + s· (29)
R
.
C -1 To verify the accuracy of the derived estimation equations,
Xl = -t:.iload·R + ipMOS [elk' R2 . C • a digital LDO circuit is designed using a 0.13f..l CMOS
technology. The LDO circuit follows the structure shown in
}[ = iPMOS •
[elk' R (30) Figure 1. It operates with a 0.5 V power supply and its output
Zl = t:.iload. R2 . C - ipMOS •
[elk' R3 . C2
voltage is 0.45 V with a maximum output current of 200 f..lA.
The digital control is implemented by a 256-bit bi-directional
Zl ..EL shift register [3] and the same number of PMOS transistors are
Voutl (t) = Xl +}[ . t l + eRoC (31)
R. C used in the array of the power devices. The size of each power
= iPMOS' {elk' R tl . - (t:.iload . R - iPMOS . {elk' R2 . C) . (1 - e:.1c) device is 0.4f..l/0.12f..l. The clock frequency as well as the
output load capacitance are varied in simulation to create
The imaginary peak occurs at time t peak l and has a magnitude different design configurations used in the study. Figure 5
OfVpeakl given by:
shows a simulated LDO output voltage (top panel) and its load
current (bottom panel). At t = 2 ms, the load current changes
t peakl = R. C . in (}[ Xl C ). R.
(32)
from 75 f..lA to 150 f..lA, and it switches back at t = 4 ms.
These current changes cause the LDO output to deviate from

= R. C . in ( -t:.iload IpMos
. R
•
[elk' R2 .
+ IpMOS [elk' R2 . C •
C

)
its ideal level momentarily. The maximum voltage error and
the output settling time are measured from simulation and
compared with results from the estimation equations. Since
VpeakI = }[. t + Xl. ( 1 -e
tP:o�k I

) ) (33)
the LDO output settling behavior is of interest in this paper,
only the regions that the LDO output manifests transient

- IPMOS .
_
{elk. R2. C . In ( _
A
LlLl
°
oad
IpMos . {elk' R2. C
•
R + IPMOS . jFelk. R2. C -R
.

/).!load
0
responses, e.g. the region encapsulated by a rectangle in
Figure 5, are depicted in the following plots.
Then the parameters for the envelope of the LDO response can
be found as follows:

Vpeak I = M ·
eaotpeakI (34)

-v
peak1 = M ·
e-aotpeak, (35)

(36)
"'(IIIS)

M = Vpeak I ' e-aotpeakI (37) Figure 5 Transient response of LDO circuit used in testing

Denote the LDO output settling error as

-
VERR BAND, the As mentioned earlier, the analysis approximates the
settling time is defmed and determined as follows: resistance at the LDO output node by a constant value R.

Venvelope (t settlmg ) - 0
-M . e-aotsettling - V - ERR_BAND (38)
Studies are first conducted to find out what is a good
approximation of the R value that can be used in the

in_(....;VE:.;.R;.;;R""M B:.;.A;;.;N ..:;.D.;...) estimation equations. There are three candidates that can be

t settling = _
(39) conveniently obtained. Two of them are the steady state LDO
a
output resistance before and after the load current change,
which can be estimated by the ratio of the voltage drop over
with all parameters given explicitly in (10), (13), (14), (30), the load current. The third option is to use the average of these
(32), (33), (36) and (37). two resistance values. Figure 6 compares the simulated results
Since the expression for the settling time is derived by with estimation outcomes. The solid line without symbols
constructing an imaginary peak at t < 0, it relies on the fact depicts the simulation results. Note that the ideal output
that such a peak actually exists. Under certain conditions the voltage level 0.45 V is treated as 0 in the plot since it is the
mathematical model describes the LDO output going off to steady state value. The other lines with legends represent the
infinity at t < O. The necessary and sufficient condition for settling envelope curves described by Equation 22. It shows
the existence of the desired imaginary peak is t:.iload < IpMos •
that using the average resistance in estimation leads to the
most accurate results (the curve with triangle legends) and
[elk . R . C. Another limitation is the resistance at the LDO
output node, which is considered to be a constant, leading to hence this approach is taken in the following study.
elevated estimation errors when the load changes are of large Circuit simulations are conducted for a number of design
magnitude or if the steady state load before the load change is configurations created by varying the clock frequency and
small. output capacitance. In simulation, the LDO load current
experiences a 75 f..lA to 150 f..lA transition. The maximum

11
voltage error and the output settling time measured from partition is valid. Such partition helps designers in the selection
simulation and estimated from equations are compared in of the clock frequency and output capacitance combinations
Table 1. The settling error requirement is set to 4 mV in that best suit their design situations.
determining the settling times. It shows the estimation
expressions achieve reasonably accuracy. Their accuracy can Compliance Region
be potentially improved by using more sophisticated methods 2.5
to select the R value used in estimation, which will be 6.7mV
investigated in our future work.
o 4.2mV
0.015
--B--- Calculated
with High Current
� Calculated with Average Current
0.01 � Calculated with Low Current G x
1
8.8mV
--Simulated
0.5

Capacitance(nF)

� Figure 7 Design space partition for satisfying maximum voltage deviation

o .0 005 requirement

V. CONCLUSION
-0.01
This work derives closed-form expressions for estimating
5
digital LDO settling time and the maximum voltage deviation
-OOI 0�-:0:":.5:----'--c-'1.::-
5 --=----=-
27.5 --=-----=3:': .5---':--4'"'.5:----:5 after a load change. The accuracy of the estimation results is
time(sec)
validated by comparing with circuit simulation results. It also
Figure 6 Comparison between simulated and calculated results with different
calculated R values shows how the derived equations can be used to help
designers effectively explore the design space in early design
Table I' Comparison of simulation and estimation results stages.
Clock Freq. (MHz) I 2.5 5 7.5
Output Cap. (nF) 200 100 45 30 VI. REFERENCES
Volt. peak Estimation 10 8.2 8.8 8.8
deviation Simulation 9.8 10 8.6 11.1 [I] S. T. Kim, Y.-C. Shih, et. aI., "Enabling wide autonomous DVFS in a
(mV) Error 2% 18% 2% 21% 22nm graphics execution core using a digitally controlled hybrid
Estimation 191.4 75.2 37.7 25.2 LDO/switched-capacitor VR with fast droop mitigation," in International
Settling time
Simulation 167.8 80.4 39.8 26.8 Solid-State Circuits Conference (ISSCC), San Francisco,CA,Feb 2015.
(/1s)
Error 14% 6% 5% 6%
[2] K. Luria, J. Shor, M. Zelikson and A. Lyakhov, "Dual-use low-drop-out
regulator/power gate with linear and on-off conduction modes for
The estimation equations can help designers effectively
microprocessor on-die supply voJtages in 14nm," in International Solid­
explore the design space in early design stage. It can be easily State Circuits Conference - (ISSCC), San Francisco,CA,2015.
verified whether an LDO with selected design parameters can [3] Y. Okama, K. Ishida, Y. Ryu, X. Zhang, P.-H. Chen, K. Watanabe, M.
satisfy certain transient behavior requirements. Similarly, Takamiya and T. Sakurai, "0.5-V Input Digital LOO with 98.7% Current
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aforementioned digital LDO circuit is required to keep the
maximum voltage error below 5 mV when its load current
switches between 50 f..lA and 100 f..lA levels. Also, assume the
designer has the freedom to vary the clock frequency and
output capacitance to satisfy the above design requirement.
Thus, the design space can be illustrated by a 2-D plot as
shown in Figure 7. The estimation equation can be used to
generate a curve that partitions the design space into
compliance region and noncompliance region as shown in the
figure. The compliance region is the design space that meets
the design requirement. To verify the design space partition,
four design configurations are simulated. Two of them,
represented by circle symbols, are located on the boundary
between the two regions; the other two, represented by
symbols D and x, are located inside and outside of the
compliance region, respectively. The maximum voltage errors
obtained from circuit simulation are listed beside the symbols.
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