15.5 (8005) IEEE Asian Solid-State Circuits Conference November 5-7, 2018/Taman, Taiwan A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI Guénolé Lallement"t, dy Abouzeid", Thierry Di Gilio*, Philippe Roche* and Jean-Luc Autran’ *$TMicroclectronics, 850 Rue Jean Monnet, F-38926 Crolles Cedex, France, NIM2NP, Aix-Marseille University and CNRS, UMR7334, Marseille, France. Email: guenole lallement@st.com Abstract—The design of Ultra-Low Power clock reference systems with highly energy-eflicient operations is a key concept ‘to achieve autonomous Internet-of-Things applications. In this work, a System-on-Chip is presented, embedding an area-efficient tltra-low voltage clock reference generator built on a digitally ‘controlled leakage-based Ring Oscillator. Through a relocking scheme using 2 2° Hz external quartz reference, an associated digital compensation circuit ensures a stable output frequency ‘of 32.768 kilz over inherent Process, Voltage and Temperature variations. The whole design has been fabricated in 28 nm FD- SOI technology and operates at a fixed supply voltage Ve of 0.5V. By combining Ultra-Low Power techniques, a 15nW power consumption is achieved for the Oscillator and 125 nW {or the digital compensation. The circuit area of the proposed clock source is 56.2h1m x 29.1ym. A 90 ppnvV voltage accuracy has been measured over 10 packaged dies for Vas = 8%. A temperature accuracy of 1.9 ppnv'C is also reported from 0°C to 50°C. Lastly the long-term frequency stability is characterized by an Allan deviation floor of 0.1 ppm. I. INTRopucTION With billions of devices expected in the next decade, the Internet-of-Things (IoT) ecosystem will require a wide variety ‘of low cost, battery-operated and inter-connected applications From implantable biomedical sensors to industrial machine diagnosis devices or personnal IoT applications [1], a clock source is always required as a substantial building block of digital Systems-on-Chip (SoCs). Actually, a low frequency clock from a few Hz to 10's of KHlz is used as a Real Time Clock (RTC) or applied as an input reference for further embedded clock mulipliess (eg. PLLs). More aggressive power reduction strategies are using this reference to clock digital circuits during sleep modes. In the specific context of Ulua-Low Power (ULP) applications the proposed clocking solution must also ensures insensitivity to PVT variations as ‘well as inherent low power consumption, Tn this work a leakage-based approach has been developed combined with a fully digital controller. The system bas been implemented in 28nm Fully Depleted Silicon-On-Insulator FD-SOD) technology with an operating supply voltage of ‘The ULP leakage-based Ring Oscillator (LRO) is coupled with a digital compensation block encapsulated in a Control Logic Unit (CLU) to offer an accurate and stable 32.768kHe output frequency with 90 ppnvV voltage, 1.9 ppmi°C temperature accuracy, and 0.1 ppm long-term fre quency stability. A 2°? Hz external reference is used for LRO 976-1-5386-6419-118/831.00 ©2018 IEEE 197 calibration, yet periodically deactivated to offer energy savings in comparison to a XTAL approach, In Section Tl, the implementation challenges and chosen, system architecture are presented. Thereafter, Section HI focus onto the clock generation using a programmable leakage-based oscillator, whereas Section IV gives an overview of the digital compensation developed. Lastly, the silicon measurements and results are given in Section V. TL, SYSTEM ARCHITECTURE In the context of loT-oriented systems with ~100 !W power budget [2], the timer power must be drastically reduced, Indeed, as the time reference remains ON for the entire lifetime utilization of the SoC, the regular power consumption of the device may easily dominate the energy budget. [As shown in Fig. 1 a complete system has been imple- mented, The whole design is composed of three building blocks: + A Full-Custom leakage-based Ring-Oseillator (LRO) pro- ducing an output clock CLK zRo, and digitally con- trolled using 10 control bits and an enable signal; + A Control Logie Unit (CLU) embedding a digital com- ‘pensation circuit to calibrate the LRO with the help of an extemal known reference CLK nse: + A SPI conuoller and configuration interface to easily communicate with the IP and guarantee a proper con- figuration of the device tenable of ak nO opie | ral Sgnae Fig. 1: Overview of the clock generator architecture.15.5 005) H " Fig. 2: Leakage-based Ri IIL, CLOCK GENERATION USING A LEAKAGE-BASED RING OSCILLATOR, A.5 stages current controlled Ring Oscillator architecture has been designed (see Fig. 2a). This topology offers a very low power consumption as explained in [3]. nMOS devices are ‘used to drive a curtent source [ieq4 to load an output capacitor Gr. Thus, the output frequency is directly given by the current Treat G.Ven four with Vw the threshold voltage of the nMOS transistors. ‘A matching circuit is attached to the last transistor of the ring. It helps to maintain the dynamic swing of the signal between Vig and gd to drive the following stage composed of standard cells. Lastly, an AND gate is added into the feedback loop of the RO to act as an enable whereas a final output buffer ensutes the correct driving of the output stages. The full system is operating at a fixed Vag = 0.5V. Digitally controlled leakage-based current sources have ‘been implemented as shown in Fig. 2b. A set of three different aurays of wansistors is used (o generate the output current at. By selecting X number of Low-Voltage Threshold (LV” PMOs and Y number of Regular-Voltage Threshold (RVT) pMOS, a given amount of current is produced, leading to a modulation of the LRO output frequency. The array based on LVT pMOS helps to produce coarse steps whereas RVT pMOS are used for fine steps. Besides, the Init array is added to guarantee oscillations when no other sources are activated and the RO enabled. The current sources in Fig. 2b are replicated 5 times to compose the 5 RO stages. To ensure high linearity when adding one more digitally controlled leakage source, a thermometer approach is chosen, ‘Thus, a conversion stage converts the binary veetor CTRL to 1 thermometer code SEL dispatched to the leakage sources. To compensate the PVTs variations, the LRO must offer adequate current to always ensure cortect operation at the 82,763kHe target frequency. Simulations were performed around five comer cases; FastFast (FF), FastSlow (FS), Slow- Fast (SE), SlowSlow (SS) and Typical (TT), from 0°C to 50°C, and 0.46 V to 0.54 V voltage ranges. IEEE Asian Solid-State Circuits Conference November 5-7, 2018/Tainan, Taiwan () Schema of he dgtally cone leshage sources ing Oscillator Architecture IV, DIGITAL RELOCKING SCHEME In onder to guarantee absolute frequency stability of the across PVT variations calibration methods are required. Hence, ‘wo approaches could be developed; reducing the sensitivity twough analog circuit techniques or compensating the vari- ations using an external digital feedback loop. In advance technology nodes, high noise immunity can be achieved using simple (.e. negligible power) digital logic, whereas decreasing the sensitivity of the RO implies a more complex analog par. A digital approach using a 2? MHz XTAL reference has therefore been chosen, {As circuits using Successive Approximation Registers tend to have high jitter sensitivity [4], a Proportional-Integral (PD) corrector solution has been selected. It ensures a fast setting time of the compensation loop, a good accuracy and a simple implementation. Fig. 3 describes the Control Logie Unit implementation. As a fist step, a synchronization and counting stage produces the digital word Zzno/aer = Sse Suno- This frequency ratio is then fed to the compensation stage where it is compared With Ztorgee = 22/2! = 128 to produce the error signal & Subsequently, ¢ is used into the PI stage presenting a programmable integral gain K; (< 0) to generate the binary control signal CTRL. However, to maximize the accuracy of the system two modules have been added Sinton and Counting Stage conversion tage eno] coon rome) 25) imse| ame FZ le aor) ay ot —t $ cal = al nom anal Fae Fig, 3: Control Logic Unit. 19815.5 (8005) Fust, a low saturation module avoids oscillations due to the discrete error. On the one side, when a large frequency error is detected a large gain ensures fast convergence. On the other side, when « > 0, a smaller feedback gain is required to set the tuning word and target the correct output frequency. By detecting this low saturation a second error signal ¢’ is produced to automatically tune the effective gain of the corrector and achieve accuracy with high jiter tolerance, Secondly, an anti-windup stage avoids overshooting and continuous increasing of the accumulated error. Indeed, if ¢ remains positive (fesp. negative) for a certain period of time, the control signal saturates at a min, value (tesp. a max value) due to the limited number of leakage sources available. Yet, if the error stays positive (or negative) after saturation, the integrator continues to accumulate an error that «will be difficult to compensate in a reasonable amount of time. This can lead to a significant error on the output or system instability, Therefore, a loop is added that uses a third error signal e” defined as the difference between the PI output and the effective output CTRL. Finally, a conversion stage converts the binary code into a thermometer code to address the LVT and RVT array (see Section I) ‘The CLU is using CLK ger as the clocking element. As the ertor is updated every period of CLK‘, no. this solution helps relax the design timing constraints by allowing the K, ‘multiplication to be done over multiple CLK ger periods. ‘Moreover, when the relocking is done, disabling the reference lock leads to removing the dynamic power of the digital block and the XTAL power. V. SILICON MEASUREMENTS ‘The full system has been integrated into an ULP SoC [2] and fabricated in 28nm FD-SOI technology, The oscillator provides a 32.768kHz reference for a frequency multiplier ‘or enables direct clocking of the Always-On domain of an ARM-based microprocessor dusing deepsleep operations. In Fig. 4, an overview of the LRO layout is given as well as a micrograph of the testchip. The CLU and SPI module have bbeen integrated directly into the Always-On logic. Fig. 4: Testchip micrograph and view of LRO layout. LRO area is 1635 pan?) Thereupon, 42 dice were packaged and measured using a custom development board and Kintex®-7 FPGA from 199 IEEE Asian Solid-State Circuits Conference November 5-7, 2018/Taman, Taiwan Xilinx. The power consumption of the LRO is 15nW and 125uW for the CLU, both measured at 0.5 V/25 °C with an output frequency of 32.768 kHz and a reference at 22? Hz. A. LRO Free Oscillations and Sister ‘The output frequency of the oscillator according to the input, control code has been measured for 42 dice and reported in Fig. 5. The grey area represents the whole set of measured values. For each sample the target frequency can be reached showing proper process compensation capabilities. Moreover, the measured mean frequency is compared (o the simulated value in TT, showing matching between CAD models and silicon results. From these results, 10 dice were randomly selected for further analysis. saat Frequency] 2ou0! Input code crm. Fig. 5: Comparison of simulated and measured LRO frequency ranges according to the input code for 42 dice at 0.5 V/25°C, B. Digital Compensation Evaluation A measurement of a typical locking cycle is shown in Fig. 6 with the correction word CTRL and the error ¢ in blue and red respectively, Starting from the fastest configuration (all sources activated), the system is able to lock in 0.342ms showing a fast settling time. — Binaryinpt code eeegerses Time ns) Fig. 6: Evaluation of the locking scheme during a typical initial calibration at 0.5 V/25 °C. ‘The CLU compensation capabilities across voltage and temperature were measured for 10 dice when the system has locked. At the nominal operating point 0.5 V, a median output frequency of 32768.3687 Hz is calculated leading to15.5 005) a relative variation of 11 ppm. Across the [0.46 V-0.54V) voltage range (ie. Vaz = 8%), an average median frequency of 32768.2870Hz is measured leading t0 a ~90 ppavV voltage stability (Fig. 7). From 0°C to 50°C, an average median frequency of 32771.06701Hz is obtained leading a ‘~L9 ppny°C temperature stability g 5 ouartte Supply ota VV Fig. 7: Measured output frequency when relocked versus supply voltage for 10 dice at 25°C. Long-term stability is often described using the two-sample deviation 0, (7), also called Allan deviation. Timer long-term stability is mandatory when used for SoC's sleep modes. In Fig. 8, the Allan deviation is calculated for averaging periods + up to 100s withthe max and min confidence interval. For intervals up to 20s, 6,(7) is limited by white noise. Then, the Allan deviation is bounded by I/f noise, which is reduced in advanced FD-SOI nodes [9]. This helps to achieve a 0.4 ppm Allan deviation flor after 30 The system performances are compared in Table T with the latest Stale of the Art CMOS-based oscillators operating around 32.768 kis VI. CoxeLusions ‘This research presents a fully-integrated Ultra-Low Power oscillator and an associated compensation unit in 28mm FD- SOI both operating at 0.5 V. It offers high power efficiency combined with very low voltage and temperature variations. In the end, by demonstrating an efficient low-cost clock, this work offers a versatile time reference and clock source for standard digital systems. IEEE Asian Solid-State Circuits Conference November 5-7, 2018/Tainan, Taiwan ‘averaging period) Fig. 8: Measured Allan deviation with min and max confidence intervals at 0.5 V/25 °C. REFERENCES [1] J.A. Stankovic, “Research directions forthe internet of things IEEE Internet of Things Journal, pp. 3-9, 2014 [2] G.Lallement etal, “A 27 pMfeycle 16 Mil, 0.7 KW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SO1," JEEE Fournal of Solid State Circuits, pp. 1-13, 2018 [3] B. Rezavi, Design of Analog CMOS Integrated Circuits MeGra-Hill Education, 2001 [4) M. Scholl a, “A. 80 nW , 32 kite Charge-Pump based Ultra Low Power Oscillator with Temperature Compensation,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 343 346, 2016 [5] D. Kamakshi et al, “A 36 nW, 7 ppmy°Con-Chip Clock Souree Platform for Near-Human-Body’ Temperature Applica- tions," Journal of Low Power Electronies and Applications (IL PEA}, 2016, D. Gritith et al, “A 190nW 33kHr RC oscillator with 40.21% {emperature stability and 4ppm long-term stability.” IEEE Inter national Solid-State Circuits Conference (ISSC), pp. 300-301, 2014, (7) K. Toubaki et al, “A 3255-kHz, 472-n0V, 120ppm"C, fully on- chip, vatiation tolerant CMOS telaxation oscillator for a teal lume clock application,” IEEE European Solid-State Chcuite Conference (ESSCIRC), pp. 315-318, 2013. [8] K-I. Hsiao, “A 324 ppm/'C. 3.2-1.6V Sel-chopped Relaxation Oscillator with Adaptive Supply Generation,” IEEE Symposium ‘on VEST Circuits (VESD), pp. 14-15, 2012. (9) E.G. Ioannidis etal, “Low frequency noise variability in high- Kimetal gate stack 28nm bulk and FD-SOT CMOS transistors, International Electron Devices Meeting, IEDM, pp. 449-432, 2011 6 TABLE I: SUMMARY OF THE ACHIEVED PERFORMANCES AND STATE OF THE ART COMPARISON Feue [| Thiswork [| MPENIS(S) | ESSCRCIG() | SCH (6 | ESSCROG | Vista I) Technology [| 28nm FDSOI || 130m CMOS | 130nm CMOS | G5mm CMOS | 180mm CMOS | oan CMOS Archiectre |} Ring Osctator |] Ring Oscitator | Charge-Pump | RC Oscillator | Relax. Oscaor | Relax. OscTator (Ose Area fmm?) 0.001635 0269 one ois ‘10s nose Frequency IRF 32.768 150 2 2 5255 2768 TSnW (Ore) || 20aW (xe) | sOmW Ove) ¢ uw owes] rasa aoiiay [| :258'cvcan | 2oon nde | Be | za aan Voltage 90 10000 5 T1000 a0 sendy || 104s 02a v [| 00s Be xa fins Hany | wotiy | ae 3tiy “Tempersture 720. 3a suntinmra _w save 20 tio too | p20 ce | 40 “itoy ee | p20 “tone eine tor Loos | Se