Architecture for Carbon Nanotube

Based Memory (NRAM)

Bill Gervasi
Principal Systems Architect

18 August 2018
Agenda 2

• Carbon nanotube basics

• Making & breaking connections
• Resistive measurements
• Write endurance, Timing, & Temperature
• When DRAM fades away
• The universe of Storage Class Memories
• NRAM: Memory Class Storage
• Standard modules using NRAM
• Industry readiness for persistent memory
 Disclaimer 3

• Nantero is a technology development and intellectual property licensing

company
• This presentation covers the technology we develop and license
• Details shown apply to a specific reference design
• Specific product details and introduction dates relate to availability of the
technology
• Customers & partners control actual product details and dates
• We’d be thrilled to license to YOU, too 
CNT Nonvolatile Memory 4

ELECTRODE

ELECTRODE

Van der Waals effect keeps CNTs apart or together

Data retention >300 years @ 300֯ C (more likely >1000 years)

Stochastic array of many nanotubes per each cell

No Dielectric  No Known Failure Mechanism 5

TOP METAL
CNTs switch in a void

No dielectric

Wear-out has not been observed

 Unlimited write endurance expected

BOTTOM ELECTRODE
 Resistance Measurements, 0 and 1 6

20

15
Count

One representative
10 15 x 15 nm
cell shown

5
ON
OFF
0
100k 1M 10M 100M 1G
Resistance (Ohm)
Voltage

Greater than 10X difference between ‘0’ and ‘1’…

No calibration required across the wafer
Smooth SET curve: MLC has been tested as well
Pulse Width Timing, Reset  0, Set  1 7

Cumulative sampling

Consistent operation from 40 ns down to 5 ns read/write per cell

And very repeatable

No Apparent Temperature Sensitivity 8

Similar set & reset curves at any temperature

CNT operation and retention seen at 300֯C, > 300 years
Limited by underlying silicon circuit reliability
NRAM Capacity Scaling 9

……………..
……………..
……………..

Die stacking using

Add layers Example: standard TSV
of CNTs
4Gb/layer
w/ 28nm logic
Logic/Memory
process
Substrate

Process scaling is a
function of #CNTs
Multi-level cell per bit…
as a function Process agnostic… well understood
of pulse Can be built on top < 5nm
of memory or logic
processes
Note: Reference design detail; may vary by customer
DDR NRAM Scalability 512 Gb
7 nm
10
8 layers CNT
Add layers
~100 mm2
256 Gb
7 nm
128 Gb 4 layers CNT
14 nm
8 layers CNT DDR5
New process
Design Add layers
Ready 64 Gb
14 nm
4 layers CNT DDR4
16 Gb New process
28 nm logic
4 layers CNT
Add layers
16-die stacks
8 Gb
28 nm logic 8-die stacks
2 layers CNT Note: Reference design detail; may vary by customer
NRAM is a “Memory Class Storage” 11

Storage
Hard Disk
Class Memory
SSD
Memory Class
NVMe
Flash Storage
3D NOR
Phase
> DRAM performance
Change
3D Xpoint = DRAM endurance
Resistive > DRAM capacity
Wasteland Magnetic < DRAM price

Painfully slow Moderate speed

Lotsa cheap bits Moderate endurance
DDR
DRAM
Low endurance Capacity range DDR
NRAM
 DDR4 NRAM Reference Internal Architecture 12
Bank Group 3 Bank Group 2 Bank Group 1 Bank Group 0

Bank & Row

Address Latches
Bank
Bank Bank Bank Bank
Decode

BG[1:0]
Address Column Address Latching Sense Amp Latching Sense Amp Latching Sense Amp Latching Sense Amp
BA[1:0]
A[16:0] Registers Latches

Column Column Column Column

C[2:0]
Chip ID Mapping Decode Decode Decode Decode
Registers CAM
CS_n I/O Multiplexer: 64 + 8 ECC
WE_n
CAS_n Command Built-In
RAS_n Decoder Self Test CA Parity, Write Multi Read
SECDED
Data CRC Data Purpose Data
ECC Engine
CK_t
Latches Registers Latches
CK_c Clock
CKE Control
DLL

Control
I/O Drivers
Logic ODT, Vref Training,
RESET_n Strobe & Control
Generator ZQ Calibration

Value Added Functions DQS DQ DBI ODT

Standard DDR Functions

Note: Reference design detail; may vary by customer
CNT Specific Functions
Crosspoint Tiles 13

V1<0>

V2<0>

V1<1>

V2<1>

V1<2>

V2<2>

V1<3>

V2<3>

V1<4>

V2<4>

V1<5>

V2<5>

V1<6>

V2<6>

V1<7>

V2<7>
H1<0>
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
H2<0> 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2

H1<1>
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
H2<1> 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2

H1<2>
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
H2<2> 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2

H1<3>
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
H2<3> 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2

Select
Decode
Logic Tile = 64 x 256 x 4

Latching sense amplification

Note: Reference design detail; may vary by customer

Timing Impact of On-the-fly ECC 14

DDR4 DDR4 DDR5

Carbon Timing SDRAM NRAM SDRAM
Nanotube ns ns ns
Arrays
Row cycle 47.00 46.25 50.18
72 bits Access time 17.14 13.50 18.18

ECC Engine Row to column 15.00 23.00 18.18

64 bits Precharge 15.00 14.25 18.18

Write recovery 15.00 23.00 45.00

FIFO
Activate to precharge 32.00 32.00 32.00

Data Strobes Refresh 350.00 0 350.00

Note: Reference design detail; may vary by customer

Bus Efficiency Comparison at Same Frequency 15

DDR4/DDR5 ~15%

NRAM
Base throughput

Elimination of refresh

Elimination of ACTIVATE restrictions

Elimination of bank group restrictions

Elimination of power states

128 GB NRAM LRDIMM or RDIMM 16

SPD
NRAM

NRAM

NRAM

NRAM

NRAM

NRAM

NRAM

NRAM

NRAM
RCD
Fully Deterministic
DDR Memory interface
SPD
…
Host reads SPD,
tAA configures memory
tRCD Host CPU interface per settings
tRP
etc
For Comparison, Industry NVDIMM-N 17

External
energy source
Flash backup
& regulation
for DRAM

Flash
Power
Half DRAM Supply
Half Flash Flash
DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM
NVC
DB

DB

DB

DB

DB

DB

DB

DB

DB
For Comparison, Industry NVDIMM-P 18

External energy
Non-deterministic protocol needed because
other NVMs have wear out and need leveling

Controller allocates
NVDIMM-P Many need cache credits for all R/W
Power
DRAM DRAM
Supply

NVC
NVM

NVM

NVM

NVM

NVM

NVM

NVM

NVM

NVM

NVM
DB

DB

DB

DB

DB

DB

DB

DB

DB

DB
All data buffered; all signals flow to centralized controller
Power Fail Comparison 19

NVDIMM-N, -P NRAM Module

…
Power fail Complete burst in process Complete burst in process

Switch power to battery

Save all pending operations

Copy DRAM to NVM

A minute or more…
Power restore Check save status Run

Copy NVM to DRAM

Run
Software Increasingly Persistence Aware 20

Windows, Linux
exploit persistent
memory
Summary 21

• Electrostatic effects set & reset each bit

• Resistance delta of 10X allows reliable sensing
• Dielectric-free cell shows no wear-out
• DDR4 NRAM includes a DRAM-compatible front end
• Defines a new category “Memory Class Storage”
• NRAM per die capacity scales far beyond DRAM
• Fully deterministic timing better than a DRAM
• On-the-fly ECC incorporated for server class reliability
• Module level NRAM products are plug and play compatible
• Industry is ready for persistent main memory
 22

Thank you for your time

Bill Gervasi
bilge@nantero.com