A SiC-based T-type Three-phase Three-level Grid-

tied Inverter
Mingchen Gu, Peng Xu Li Zhang Kai Sun
Jiangsu Key Lab of New Energy and College of Energy and Electrical State Key Lab of Power System
Power Conversion Engineering Department of Electrical
Nanjing University of Aeronautics Hohai University Engineering
and Astronautics Nanjing, China Tsinghua University
Nanjing, China zhanglinuaa@hhu.edu.cn Beijing, China
mingchengu@nuaa.edu.cn sun-kai@mail.tsinghua.edu.cn

Abstract—Due to the high thermal conductivity and the wide
band gap, SiC power devices have many advantages against Si
power devices such as higher operation temperature, higher
breakdown electric field, higher switching speed and less
switching loss. In this paper, a SiC-based T-type three-level
topology is investigated. Considering the body diode
characteristics of SiC power MOSFETs, three kinds of
bidirectional switching circuits are presented and compared. One
of them, with the lowest conduction loss, is used as the neutral
point clamping branch of the T-type three-level inverter.
Operation modes and modulation strategy of this inverter are
analyzed. A 6 kW prototype using SiC MOSFET is built. The
efficiency is tested and compared with a Si-based prototype.
Experimental results show that using SiC power devices can
improve the conversion efficiency obviously.
Keywords—silicon carbide power devices; T-type inverter;
efficiency; three-phase inverter
I. INTRODUCTION
Power electronics devices are key elements of power
electronics systems. Although silicon (Si) power devices have
served power electronics industry well for over five decades,
silicon-based technology is reaching its physical limits for
power handling and switch-frequency capabilities. On the
other hand, Si power devices normally cannot be used at high
temperatures in power electronics systems. However, the
growing demand for smaller power systems with higher
power densities requires the development of novel power
semi-conductor devices capable of operating at higher
frequencies, higher voltages, and higher temperatures [1]-[4].
The characteristics of silicon carbide (SiC) have been well
known for years [5]-[8], and it is taken for granted that SiC
power devices can operate at extremely high temperatures
without suffering from intrinsic conduction effects because of
the wide energy bandgap. SiC power devices also have some
advantages against Si power devices, such as higher thermal
conductivity and higher breakdown electric filed. Therefore,
This work was supported in part by the National Natural Science
Foundation of China, under Grant 51307096 and Grant 51177083, and
in part by the Industry-academic Joint Technological Innovations Fund
Project of Jiangsu, China, under Grant BY2014003-12.
large efforts have been devoted to the development of SiC
power MOSFETs for high-voltage and high switching speed
applications because of their much lower specific on-
resistance when compared with silicon MOSFETs [9]-[13].
In recent years, T-type three-level topology is widely used
as photovoltaic (PV) grid-tied inverters [14]. Compared with
two-level inverters, the three-level inverters have less output
harmonic, thus the volume of filter can be reduced. However,
T-type three-phase three-level inverters with SiC power
MOSFETs have never been presented. Due to the excellent
performance of SiC power MOSFETs, the SiC-based three-
phase three-level PV grid-tied inverter has the ability to
achieve higher efficiency, higher power density and lower
cost, comparing with Si-based three-phase three-level
inverters.
The contribution of paper is to clarify that the efficiency of
the T-type three-level inverter with SiC power devices is
higher than that of the Si-based T-type three-level inverter.
This paper is organized as follows. In Section II, the operation
modes of conventional T-type three-phase three-level inverter
are analyzed. The body diodes issues of SiC power
MOSFETs are described in Section III. On this basis, an
improved T-type three-phase three-level inverter topology is
introduced. The single-phase topology is taken as an example
to analyze the operation modes. Experimental results are
presented in Section IV, and Section V is the conclusion of
the paper.
II. TRADITIONAL T-TYPE TOPOLOGY AND OPERATION
MODES
The topology of conventional T-type three-phase three-
level inverter is shown in Fig. 1.
This three-level topology is constituted by a half-bridge
circuit and a clamp branch each phase. The single-phase
topology, as shown in Fig. 2, is taken as an example for
analysis. The input DC voltage UPV is the output of PV; Cdc1
and Cdc2 have the same capacitance to divide the input voltage
into two same voltage, namely Udc1=Udc2=0.5UPV; The output
voltage uo is the grid voltage. There are four switches in the

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topology S1~S4. S1 and S2 form a half-bridge. The voltage on turned ON, and the other switches are turned OFF. The
them is UPV. S3 and S4 are used for freewheeling and clamping inductor current is owing through S1. Although S3 is turned
and the voltage is 0.5UPV. The output filter is constituted by Lo ON, there is no current owing through it, and the switch S3
and Co. has no conduction loss in this mode. vUM = 0.5UPV.

Sa1 Sb1 Sc1 b) Mode II is the freewheeling mode at the positive half
Cdc1 La period of the utility grid voltage, as shown in Fig. 4 (b). S3 and
usa
S4 are turned ON; the other switches are turned OFF. The
U PV Sa4 Sa3 Lb inductor current is owing through the channel of S3 and S4.
O
usb
PV
vUM = 0.
S b4 Sb3 Lc usc P

Cdc2 Sc4 Sc3 Ca Cb Cc U PV S1

Cdc1
Sa2 S b2 Sc2
PV U iL Lo
M
S4 S3
Fig. 1 The topology of traditional T-type three-phase three-level inverter. Cdc2 S2 Co uo

N
P (a)
U PV S1 P
Cdc1
U PV S1
Lo Cdc1
PV M U iL
PV U iL Lo
S4 S3 M
Cdc2 S2 Co uo S4 S3
Cdc2 S2 Co uo
N
N
Fig. 2 The topology of traditional T-type single-phase three-level inverter.
(b)
P
The modulation strategy with unity power factor is shown
in Fig. 3. U PV S1
Cdc1
PV U iL Lo
M
uo
S4 S3
Cdc2 S2 Co uo

iL t N

(c)
ugs1 P
U PV S1
t Cdc1
ugs2
PV U iL Lo
M
t
ugs3 S4 S3
t Cdc2 S2 Co uo
ugs4
t N

Fig. 3 Schematic of gate drive signals with unity power factor
The operation modes of traditional T-type three-level
inverter are analyzed as follows.
a) Mode I is the active mode at the positive half period of
the utility grid voltage, as shown in Fig. 4(a). S1 and S3 are
(d)
Fig. 4 The operation modes of traditional T-type three-level topology. (a)
Active mode in the positive half period. (b) Freewheeling mode in the positive
half period. (c) Active mode in the negative half period. (d) Freewheeling
mode in the negative half period.
c) Mode III is the active mode at the negative half period of
the utility grid voltage, as shown in Fig. 4 (c). S2 and S4 are

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 turned ON; the other switches are turned OFF. The inductor diode when it is blocked, there will be the reverse recovery
current is owing through S2. Although S4 is turned ON, there problem.
is no current owing through it, and the switch S4 has no
Circuit (b) is a method in which current flows through one
conduction loss in this mode. vUM = -0.5UPV.
channel of a switch and the diode in series. This method avoids
d) Mode IV is the freewheeling mode at the negative half using the body diode of the switch. If the diode in series is a
period of the utility grid voltage, as shown in Fig. 4 (d). S3 and SiC diode, there is no reverse recovery problem.
S4 are turned ON, and the other switches are turned OFF. The
Circuit (c) is a method in which current flows through one
inductor current is owing through the channel of S4 and S3.
channel of a switch and two diodes. This method also avoids
vUM = 0.
using the body diode of the switch. However, in this circuit,
current flows through three devices and the conduction loss is
III. PROBLEMS WITH CONVENTIONAL TOPOLOGY AND large. Meanwhile, there are five devices in this circuit and the
IMPROVEMENTS cost increases as well.
According to the analysis above, when the inductor current
In conclusion, circuit (a) has the reverse recovery problem
is freewheeling, the current flows through the body diode of
and circuit (c) has a large conduction loss. Considering trade-
the switches S3 and S4. If the Si switches are replaced directly
off, the circuit (b) is chosen as the freewheeling branch.
by SiC switches, there will be large amount of conduction loss
as well as reverse recovery problems. As the properties of the The improved T-type three-level single-phase topology is
body diode of SiC MOSFET are not so satisfying, as shown in shown in Fig. 6.
TABLE I [15][16], when current flows through the body diode P
of SiC MOSFET, there will be large amount of conduction S1
loss. Meanwhile, there is a voltage drop on the body diode Cdc1
U PV
when it is blocked, so reverse recovery problem exists as well.
M U Lo
Thus the conventional topology cannot be used directly with S3 D1
PV
SiC MOSFETs.
Co uo
TABLE I. DEVICE PARAMETER COMPARISON S4 D2 S
Cdc2 2

body diode of SiC N

SiC diode
MOSFET
Forward Voltage(V) 3.2f0.1 1.5
Reverse recovery Fig. 6 The improved T-type three-level single-phase topology
40 0
time(ns)
As analyzed in Section II, the freewheeling branch works The input DC voltage, UPV is the output voltage of PV
as a bi-directional switch. There are three circuits of a bi- panel; Cdc1 and Cdc2 have the same capacitance to divide the
directional switch [17]-[19], as shown in Fig. 5. input voltage into two same voltage, namely Udc1=Udc2=0.5UPV.
The output voltage uo is the grid voltage. There are four
switches S1~S4 and two diodes D1~D2 in the topology. S1 and S2
S1 S2 form a half-bridge. S3, S4, D1 and D2 are used for freewheeling
(a) and clamping. The output filter is constituted by Lo and Co.
The modulation strategy with unity power factor is the
S1 D1 same as conventional T-type topology. There are four
operation modes as shown in Fig. 7.
a) Mode I is the active mode at the positive half period of
S2 D2 the utility grid voltage, as shown in Fig. 7 (a). S1 and S3 are
(b) turned ON, and the other switches are turned OFF. The
D1 D3 inductor current is owing through S1. Although S3 is turned
S1 ON, there is no current owing through it, and the switch S3
has no conduction loss in this mode. vUM = 0.5UPV.
D2 D4
b) Mode II is the freewheeling mode at the positive half
(c)
period of the utility grid voltage, as shown in Fig. 7 (b). S3 and
Fig. 5 Three circuits of a bi-directional switch. S4 are turned ON and the other switches are turned OFF. As S3
is always ON during the positive half period of the utility grid
Circuit (a) is the method used in conventional T-type
voltage, S3 has nearly no switching loss in this mode. The
topology. Current flows through one switch and the body diode
inductor current is owing through S3 and D1. vUM = 0.
of the other. This circuit has an advantage of using the least
devices. However, because of the voltage drop on the body

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 P is always ON during the positive half period of the utility grid
Cdc1
S1 voltage, S4 has nearly no switching loss in this mode. The
U PV inductor current is owing through S4 and D2. vUM = 0.
M iL Lo
S3 D1 U Specially, during the dead band time, all switches are
PV
turned OFF. In the Mode I, the voltage drop on S4 is 0.5UPV,
the output capacitor Coss is charging. During the dead band
Co
Cdc2
S4 D2 S between Mode I and Mode II, since all switches are turned
2
OFF, the charge in Coss cannot release, Coss has to divide the
N voltage with parasitic capacitance of D2, so the drain-source
voltage will drop a step and become zero when Mode II starts.
(a)
The analysis for the switch S3 is the same.
P
S1
Cdc1
U PV IV. EXPERIMENT RESULTS AND ANALYSIS
M iL Lo In order to validate the superiority of SiC MOSFET, a 6kW
S3 D1 U
PV SiC-based prototype is built. The three-phase topology is
shown in Fig. 8.
Co uo
S4 D2 S
Cdc2 2 Sa1 Sb1 S c1
Cdc1
N
Sa3 Da1
(b)
P
Sa4 Da2 La usa
S1
Cdc1
U PV U PV Lb
Sb3 Db1 usb
M iL Lo
S3 D1 U
PV PV Lc usc
Sb4 Db2
Cdc2 Ca Cb Cc
Co
S4 D2 S Sc3 Dc1
Cdc2 2
Dc2
N
Sc4 Sa2 S b2 Sc2
(c)
P
Fig. 8 SiC MOSFET based T-type three-phase three-level topology.
S1
Cdc1
U PV
The parameters are given in TABLE II.
M iL Lo
S3 D1 U
PV
TABLE II. PARAMETERS OF THE EXPERIMENTAL PROTOTYPE
Co uo
S4 D2 S Parameter Value
Cdc2 2
Rate power 6kW
N Input voltage 600~700VDC
Grid voltage/frequency 220VAC/50Hz
(d) Switching frequency 20kHz
Power devices S1,S2 (MOSFET) C2M0080120D
Fig. 7 The operation modes of improved topology. (a) Active mode in the Power devices S3,S4 (CoolMos) IPW60R099C6
positive half period. (b) Freewheeling mode in the positive half period. (c)
Power devices D1,D2(diode) C3D20060D
Active mode in the negative half period. (d) Freewheeling mode in the
negative half period. Specially, the switches used in the freewheeling branch are
CoolMos. As analyzed, the switches in the freewheeling
c) Mode III is the active mode at the negative half period of branch are ON in half period of the utility grid voltage and
the utility grid voltage, as shown in Fig. 7 (c). S2 and S4 are switching in another half period. Current flows through them
turned ON; the other switches are turned OFF. The inductor during the ON half, so there is almost no switching loss. If SiC
current is owing through S2. Although S4 is turned ON, there switches are used here, the advantage of low switching loss
is no current owing through it, and the switch S4 has no cannot be reflected. To reduce the cost, Si CoolMos is used in
conduction loss in this mode. vUM = -0.5UPV. freewheeling branch.
d) Mode IV is the freewheeling mode at the negative half
period of the utility grid voltage, as shown in Fig. 7 (d). S3 and
S4 are turned ON, and the other switches are turned OFF. As S4

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 iLB In the conventional T-type prototype for comparison, the
iLB devices are shown in TABLE III.
uA
uA TABLE III. PARAMETER OF THE COMPARISON PROTOTYPE
Parameter Value
uBC Power devices S1,S2 (IGBT) IRG4PH40UD2-E
uBC Power devices S3,S4 (IGBT) HGTG40N60A4
Fig. 12 is the conversion efciency comparison of
uOB conventional (Si) and improved (SiC) topologies under the
uOB
same condition. It is obvious that the efciency of the
improved topology is higher than that of the conventional
topology. The maximum efficiency and European efficiency
Fig. 9 Steady state waveforms
are shown in TABLE IV.
The steady state waveforms are shown in Fig. 9, where iLB 100%

is the inductor current of phase B, uA is the voltage between 98%

terminal U and midpoint M in phase A, uBC is the voltage 96%
between terminal U in phase B and terminal U in phase C, uOB SiC
ᬜ⥛ 94%
is the output voltage of phase B. It can be seen that the output Si
92%
voltage uA has three levels as 0.5UPV, 0, and í0.5UPV, which
indicates that the inverter is a typical three-level inverter. 90%

88%
The start waveforms are shown in Fig. 10. It can be seen 5% 10% 15% 20% 25% 30% 50% 75% 100%
that the inverter can start smoothly. The inductor current
increases slowly from 0 to rated current.
Fig. 12 Efciency comparison of SiC and Si prototype

iLB uA iLB
TABLE IV EFFICIENCY COMPARISON OF SIC AND SI PROTOTYPE

uA SiC inverter Si inverter

uOB uBC Maximum efficiency 98.4% 97.7%
iLB European efficiency 97.8% 97.2%
uBC The experimental results verify that using SiC devices can
uA increase the conversion efficiency effectively.
uBC
uOB
uOB V. CONCLUSION
SiC switches have the advantage of low switching loss, but
they haven’t been used in the T-type three-level inverter so far.
Fig. 10 Start waveforms This paper analyzes the operation modes of conventional T-
type three-phase three-level inverter. Meanwhile, the body
The Drain-Source voltages of S1 and S4 are shown in Fig.
diodes issues of SiC power MOSFETs are described. On this
11. As analyzed above, the parasitic capacitors of S4 and D2
basis, three kinds of bidirectional switching circuits are
divide voltage during the dead band. The step seen in Fig. 11
presented and compared. The one with the lowest conduction
verifies the analysis.
loss is used as the freewheeling branch of the T-type three-
level inverter. Operation modes and modulation strategy of the
improved topology are analyzed. A 6 kW prototype using SiC
uds1 MOSFET is built. The efficiency is tested and compared with a
uds1
Si-based prototype. Experimental results indicate the advantage
of SiC devices in improving conversion efficiency.

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