Tutorial
VWF Simulation within Quartus
EECS 3201, Digital Logic Design
Summer 2023
By Jaspal Singh, Engineering Technologist,
Lassonde School of Engineering. EECS
York University, Toronto.
1 WAVEFORM SIMULATION IN QUARTUS PRIME
This document describes, how to run a simulation, within Quartus Prime, by creating and using a Vector
Waveform File (VWF).
The advantage of this approach is that you don’t need to create a Testbench, around your design (the
Device Under Test, DUT) and can directly drive the inputs, by creating the VWF file.
While this saves time, this approach comes with a simulation time limit. However, there is a work-around, as
explained below.
Simulating your design is often a quick and efficient way to verify that your code is functionally correct.
Simulation makes it easier to observe and fix bugs in your design, as it allows you to view signals in a
waveform. As the design complexity increases, the value added by Simulation becomes easily evident.
Before you can run the simulation using this method, it is required that your design has no syntax violations
in it. That is, you have successfully completed at least the Analysis & Synthesis step.
Currently with the VWF file you can do only do Functional Simulation but not Timing simulation.
1.1 ON LINE VIDEO
Here is a 4 mins YouTube video, as a reference, on how to simulate your design within Quartus Prime itself.
https://www.youtube.com/watch?v=e_ksjHd6sY0
Credit: Professor Rania Hussain, University of Washington.
Note*: In the above YouTube video, a full-adder is used, created via Schematic entry. If you also want to
actually do the steps, instead of just understanding, you can use the two Verilog adder files, provided under
the Tutorial for Modelsim, on eClass. You do not need the test-bench (full_adderV_tb.v) file. Of course, you
will need to create a Quartus project first, and add the two design files. Then you can follow the steps
described below.
1.2 VWF TIME LIMITATION
Note that, when using the VWF file in Quartus, the maximum simulation time is limited to 100 us only!
However, this would be enough for simulating many circuits with simple gates and arithmetic operations.
In case you have a bigger, more complex design with longer data-paths, timing delays etc. In such situations
you have these options…
1a) Assuming your code is using a clock, then for the purpose of simulations only, when creating VWF
waveform file, set your clock at the fastest rate, so that you can still see / verify results within this time
limit. Note that VWF waveform file allows setting Clock rate as high as 500 MHz (2 nS period).
So if your design clock speed is 50MHz, simulating it with 500MHz in fact gives your 1 seconds
simulation, with the above limitation.
1b) For the purpose of the simulation only, you can reduce the delay values in your design. After the
verification, however do change them back to the intended values.
2) Alternatively, use the free Modelsim-Starter version, which comes with Quartus Prime, or any other
simulator of your choice. However you would then have to create a testbench around your design, i.e.
the DUT.
1.3 GENERATING THE WAVEFORM
1. Ensure your design has no syntax violations. That is, within Quartus ensure, that the Analysis &
Synthesis step runs successfully.
2. Do menu File -> New -> (under Verification/Debugging files choose) -> University Program VWF
and click OK
3. In the Waveform Editor, which opens, set appropriate End Time and Grid Size by
Menu -> Edit -> Set End Time / Grid Size
Note: If you previously created and saved a VWF file, you can re-open to view / edit via menu File ->
Open
4. To add your design’s top level signals and ports/pins to the waveform, do
Menu Edit -> Insert -> Insert Node or Bus.
In the pop-up window that appears, click on Node Finder.
In the open window use the default ‘Pins: all’ filter to select top level pins in your design.
You can replace the wildcard entry * as required, with your own pin names, to filter.
Note: If you want to capture, inner signals from your design, instead of just the top-level ports / pins, then
change the Filter option to (e.g. Registers: Post Synthesis) and then click on the List.
5. Once your signals / ports are shown under the ‘Nodes Found’ pane, select and move them to the
‘Selected Nodes’ pane and then click OK.
This takes you back to the ‘Insert Node or Bus’ window. Again click OK and the signals / ports are now
added to the Waveform.
Note: By default, the inputs are at 0 / low state and the outputs are at X / undefined state.
Note: You can now group signals, change their radix or move them up / down, as per your preference.
1.3.1 DRIVING INPUT PORTS / BUSSES
To drive your inputs, you have to create waveforms on the inputs ports.
Input waveforms can be drawn in different ways.
Since the inputs are low by default, they can be changed to High level for the time and duration required, by
clicking and dragging the mouse, so as to select the range you like and then clicking on the Forcing High
(1) icon , to force the input to be high there.
E.g. click the mouse on the x waveform near your start-point and then drag the mouse to the desired end-
point.
Change the value of the waveform to 1 by clicking on the Forcing High (1) icon
In a similar fashion, you can also drive your Reset input and other inputs.
If you chose to use the two full-adder Verilog design files, then you would be seeing three inputs a,
b and c at 0 value and two outputs fsum and fcarry_out at X value.
You can assign different possible values to the three inputs (e.g. from 000 to 111), to see the
response of the two outputs, after you have completed the 1.4 Running the Simulation step.
Note: In case you have multi-bit inputs or Busses, e.g. Address or Data Values, then after grouping them,
you can assign values to them, by selecting the range / zone and then right clicking. These could be
Signed, Unsigned or Incrementing values.
Watch for your grouping order! Typically MSB to LSB is the correct and preferred order, however you can
order them in reverse also.
1.3.2 DRIVING INPUT CLOCK
We will use a different approach to draw the waveform for y input, to show how to drive input clock. We want
this signal to alternate between logic values 0 and 1 at each 100-ns interval.
Such a regular pattern is indicative of a clock signal that is often used in many logic circuits.
Click on the y input (or your clock input port), which selects the entire simulation interval. Then, click on the
Overwrite Clock icon and set your Period and Duty Cycle values.
After you have created the input waveforms, your VWF file would appear as shown above.
1.3.3 SAVING WAVEFORM
Save the waveform file using the default name of ‘Waveform.vwf’.
As mentioned earlier, the extension vwf stands for vector waveform file.
Note: Do menu File -> Save As and save the Waveform.vwf file, under the Project folder.
If prompted, don’t save it under the ‘output_files’ folder. This is known to cause problems.
1.4 RUNNING THE SIMULATION
After you have saved the VWF file, click on the Functional Simulation icon (or menu Simulation -> Run
Functional Simulation). This starts some scripts (as per menu -> Simulation -> Simulation Settings), as
shown below. Once these are run successfully, the functional simulation results would be shown.
Once the Simulation is complete successfully, the output waveforms would get generated and displayed, to
help you verify the Functional behaviour of your design.
Before running the Timing simulation, first ensure that you have successfully Compiled your design. The
Fitter and Timing Analysis steps are required to be completed.
As mentioned earlier in section 1.3 Generating the Waveform, if required, you can also add lower level
signals to the waveform, to see their response.
Note, you drive only the inputs, as per sections 1.3.1 and 1.3.2 and not anything else.
1.5 VSIM_12110 ERROR MESSAGE
In case you get error messages related to (vsim-12110) –novopt option, when running the Simulation. You can
overcome it by removing it from the Settings by:
(menu Simulation -> Simulation Settings and remove it, from next to the vsim command, under the Modelsim script
pane, as shown in the second image below, where the –novopt option has already been removed.
Simulation Options, without –novopt flag in ModelSim Script. If needed, remove in Timing Simulation Settings also.
1.6 CONVERTING VCD TO VWF MESSAGE
Depending upon the size, complexity of the design and the clock rate and end time selected, you may
encounter the following message for a rather long time, as the Simulator generates the output Waveform.
If you find this is too long a time, then you would be better off, to write a Verilog testbench for your design
DUT and running the simulation using Modelsim, which should be much faster.
