TL1763 - Spec V1 (1) (1) .0 - 200612

LCD driver IC
Dec. 2006
VER. 1.0 TL1763
240 RGB X 320 Dot 1 Chip Driver with GRAM and Power circuit
for 260K Colors TFT-LCD Display
Tomato LSI Inc.

Ver .1.0
TL1763 240 RGB X 320 Dot 1 Chip Driver with GRAM and Power for 260K Colors TFT-LCD
CONTENTS
1. INTRODUCTION.......................................................................................................................................... 4
2. FEATURE..................................................................................................................................................... 4
3. BLOCK DIAGRAM........................................................................................................................................ 7
4. PIN DESCRIPTION...................................................................................................................................... 8
5. FUNCTIONAL DESCRIPTION................................................................................................................... 13
5-1. System interface................................................................................................................................. 13
5-2. External Display Interface (RGB interface, VSYNC interface)........................................................... 14
5-3. Address Counter (AC)........................................................................................................................ 14
5-4. Graphic RAM (GRAM)........................................................................................................................ 14
5-5. Gray Scale Voltage Generation Circuit.............................................................................................. 14
5-6. LCD Operating Voltage Circuit .......................................................................................................... 14
5-7. Timing Generation Circuit................................................................................................................... 14
5-8. Oscillation Circuit ............................................................................................................................... 14
5-9. Source Driver Circuit.......................................................................................................................... 14
5-10. Gate Driver Circuit............................................................................................................................ 14
5-11. Internal Logic Power Supply Regulator............................................................................................ 14
5-12. GRAM Address Map........................................................................................................................ 15
6. INSTRUCTIONS ........................................................................................................................................ 25
Instruction Table........................................................................................................................................ 27
6-1. Index/Status/Display control instruction............................................................................................. 29
(1) Index (IR) ..................................................................................................................................... 29
(2) Status read (SR)........................................................................................................................... 29
(3) Start Oscillation (R00h)................................................................................................................ 29
(4) Driver output control 1 (R01h)...................................................................................................... 30
(5) LCD Driving-Waveform Control (R02h)........................................................................................ 31
(6) Entry Mode (R03h) ...................................................................................................................... 32
(7) Driver output control 2 (R04h) .................................................................................................... 37
(8) Display Control 1 (R07h) ............................................................................................................. 38
(9) Display Control 2 (R08h) ..............................................................................................................40
(10) Display Control 3 (R09h) ........................................................................................................... 41
(11) Frame Cycle Control (R0Bh)...................................................................................................... 42
(12) External Display Interface Control (R0Ch)................................................................................. 44
(13) Equalize control (R0Eh)............................................................................................................. 46
6-2. Power Control Instruction ................................................................................................................ 48
(1) Power control 1 (R10h)................................................................................................................. 48
(2) Power control 2 (R11h)................................................................................................................. 50
(3) Power control 3 (R12h)................................................................................................................. 51
(4) Power control 4 (R13h)................................................................................................................. 51
6-3. RAM access instructions.................................................................................................................. 53
(1) Horizontal Address Set (R20h) .................................................................................................... 53
(2) Vertical Address Set (R21h)......................................................................................................... 53
(3) Write Data to RAM (22h) ............................................................................................................. 54
(4) Read Data to RAM (22h) ............................................................................................................. 61
6-4. Gamma-Control Instruction.............................................................................................................. 63
6-5. Display panel control instruction....................................................................................................... 64
(1) Gate Scan Control (R40h)............................................................................................................ 64
(2) Vertical Scroll Control (R41h)....................................................................................................... 65
(3) 1st Screen Driving Position (R42h/R43h)..................................................................................... 66
(4) 2nd Screen Driving Position (R44h/R45h).................................................................................... 66
6-6. Window Addressing Control Instruction............................................................................................ 67
(1) Horizontal RAM Address (End/Start address): R46h.................................................................... 67
(2) Vertical RAM Address (End address): R47h................................................................................. 67
(3) Vertical RAM Address (Start address): R48h…............................................................................ 67
TOMATO LSI Inc. 2

Ver .1.0
6-7. Source Driver Control Instruction…...............................................................................................67

(1) Source Driver Control 1: RA1h…...................................................................................................68
(2) Source Driver Control 2: RA4h…...................................................................................................68
7. RESET FUNCTION…................................................................................................................................ 69
8. INTERFACE SPECIFICATION.................................................................................................................. 70
8-1. System Interface................................................................................................................................ 71
8-2. VSYNC Interface............................................................................................................................... 85
8-3. External Display Interface (RGB interface)........................................................................................ 89
8-4. RGB Interface Timing........................................................................................................................ 90
8-5. Timing of LCD Panel Interface.......................................................................................................... 97
8-6. Window Address Function................................................................................................................. 99
8-7. Scan Mode Setting...........................................................................................................................102
8-8. N-raster-row Reversed AC Drive......................................................................................................103
8-9. Interlace Drive………………….........................................................................................................104
8-10. Frame Frequency Adjustment Function .........................................................................................107
8-11. Screen-division Driving Function................................................................................................... 108
8-12. Oscillation Circuit........................................................................................................................... 111
9. GAMMA ADJUSTMENT FUNCTION .......................................................................................................112
Gamma Correction Function....................................................................................................................112
Configuration of grayscale Amplifier .......................................................................................................113
Gamma Correction Registers..................................................................................................................115
Ladder resistors and 8 to 1 selector........................................................................................................116
8-color Display Mode.............................................................................................................................. 123
Low power consumption driving settings................................................................................................... 124
Power generation circuit block diagram..................................................................................................... 125
Specification on TL1763 power circuit and external elements................................................................... 126
Pattern Diagrams for Voltage Setting........................................................................................................ 127
Power supply setting flow.......................................................................................................................... 128
Instruction setting flow............................................................................................................................... 129
Standby, Sleep mode set/release.............................................................................................................. 130
8-color mode setting.................................................................................................................................. 131
10. SPECIFICATIONS................................................................................................................................. 132
Absolute Maximum Ratings ................................................................................................................... 132
DC Characteristics.................................................................................................................................. 133
AC Characteristics.................................................................................................................................. 135
11. CHIP FORMAT...................................................................................................................................... 140
12. BUMP .................................................................................................................................................... 142
13. ALIGN KEY............................................................................................................................................. 143
14. PAD CENTER COORDINATES............................................................................................................. 144
TOMATO LSI Inc. 3

Ver .1.0
1. INTRODUCTION
The TL1763 is 1-chip controller driver for TFT-LCD panel, source driver with built-in GRAM, gate driver and
power supply circuits are integrated on one chip. This IC can display to a maximum of 240RGB x 320-dot
graphics display on 260K colors TFT panel.
As a system interface with MPU, the TL1763 has high-speed 6/8/9/16/18 bit bus interface. The TL1763
also can display a moving picture with 6/16/18 bits RGB interface.
TL1763 has step up circuit and voltage follower circuit that generate necessary voltage for operating TFT
LCD panel. And the software enables generating grayscale voltage independently necessary for panel.
TL1763 has 8-color display function, optimized power management function such as standby and operation
control circuit suitable for optimum display.
The TL1763 is suitable for small mobile products as digital cell phone corresponding to WWW browser,
bi-direction pager, a small PDA and display module for any other portable system.
2. FEATURE
z LCD driver/controller outputs
- Source/Gate driver for 240RGB x 320-dot graphics display in 260K colors TFT LCD
- 720 channel source outputs / 320 channel gate outputs
z System interface
- High-speed 18/16/9/8/6-bit parallel bi-directional interface with 6800 / 8080-series MPU
- Serial Peripheral Interface (SPI)
z Moving picture display interface

- 18/16/6-bit RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, DB17-0)
- VSYNC interface (System interface + VSYNC)
z On-chip display data RAM capacity

- Display data RAM is compressed.
z High performance RAM writing function

- Window function to write data to a rectangular area of RAM specified by window address
- Write data to a rectangular RAM address area through a moving picture display interface
- Reduce data transmission by only transmitting data to be written on the area display moving picture
- Simultaneous display with internal RAM data displayed in still picture area
z Various display function

- Normal display mode : Display extension associated with maximum 240RGB x 320dot
- Partial display mode : 2 screens partial display at the arbitrary position
- Area scroll mode : Scroll display function by the arbitrary lines
- 8-color mode : Display drives only 8-colors for ultra-low power mode
- Standby mode : Display off and internal display clock off
- Simultaneous display of RAM data and still image
TOMATO LSI Inc. 4

Ver .1.0
z Low power consumption architecture

- standby mode, sleep mode
- 8-color ultra-low power mode display
- Partial display at the arbitrary position
- Voltage followers to decrease direct current flow in the LCD drive breeder-resistors
- Input power supply voltage Interface I/O power supply: IOVCC = 1.7 to 3.3V
Internal logic power supply: VCC = 2.4 to 3.3V
Analog circuit power supply1: VCI = 2.5 to 3.3V
Analog circuit power supply2: VCIF = 2.5 to 3.3V
z Power supply circuit for LCD operation

- Source driver for LCD and VCOM operation VLO-VSS = 5.0 to 6.6V
VCL-VSS = 0 to -3.3V
- For Gate operation VGH-VGL = 13.6 to 32V
VGH-VSS = 7.4 to 21.52V
VGL-VSS = -6.2 to -15.44V
- For VCOM operation (VCOM) VCOMH = 3.0 to (VREG1-0.5)V
VCOML = (VCL+0.5) to 1V
VCOMH-VCOML amplitude = 6V max
z Driving method
- Frame reverse driving & line reverse driving
- Capability of n line AC Liquid Crystal operation (Possible to reverse polarity at each optional line)
z Oscillator
- On-chip RC oscillator (Internal capacitance & External resistor)
- External clock available
z Incorporated LCD power-supply start-up sequence
z Cst structure (Common VCOM method)
z H/W reset function
z Available COG
TOMATO LSI Inc. 5

Ver .1.0
TL1763 LCD Power Supply
NO Item TL1763
1 Number of driver circuit for TFT source line 720
2 Structure for TFT-display retention volume Cst (Common to VCOM method)
S1 ~ S720 V0 to V63 grayscale level

LCD operation
3
output VCOMH = VCOMR //Electric volume
VCOM VCOMH-VCOML amplitude = Electric volume
IOVCC
1.7 to 3.3V
Interface voltage
VCC
2.4 to 3.3V
Logic regulator voltage(*1)
4 Input voltage
VCI
2.5 to 3.3V
LCD driver power supply voltage
VCIF
2.5 to 3.3V
Regulator power supply voltage
VLO 5.0 to 6.6V
VGH 7.4 to 21.52V

LCD operation
5 VGL -6.2 to -15.44V
voltage
VCL 0 to -3.3V
VGH - VGL 13.6 to 32V
VLO VCI x 2
VREG2 x 2 (+ VCI),
VGH
Internal step-up VREG2 x 3 (+ VCI)
6
circuit VREG2+ VCI,
VGL
VREG2 x 2(+ VCI)
VCL VCI x -1
Note 1) When internal logic regulator is in used.
TOMATO LSI Inc. 6

Ver .1.0
3. BLOCK DIAGRAM
Index VSS1
Register Control VSS2
(IR) Register VSS3
VSS4
Address VSS5
IOVCC Counter VSS6
IM3-1,IM0/ID
18 BGR
CSB System 18 Write Data 18
Circuit
Interface Latch
RS
- 18bit
LCD Driving Circuit

M Inversion Circuit
E_WRB/SCL - 16bit
Latch Circuit
Latch Circuit
Latch Circuit
RW_RDB - 9bit Display Data
Read Data 18
18 - 8bit RAM
DB17-0 Latch S1 ~ S720
- 6bit
SDI - SPI
SDO
VSYNC
External
HSYNC Display V63 ~ V0
Interface VGS
DOTCLK
r-Correction
ENABLE Timing
Generation
Grayscale
Voltage
Circuit
Circuit
Generation
Circuit
RESETB
FLM
3
M
OSC2 CL
OSC
OSC1
Gate control
VCC
Power Regulator Gate Driving Circuit G1 ~ G320
REGOFF
VCCL
LCD Driving Level Generation Circuit

C11+/C11-
C12+/C12-
C21+/C21-
C23+/C23-
C31+/C31-
VREG1
C22+/C22-
VGL
VLO
VGH
VCI
VCOMR
VCOMH
VCL
VREG2
VCOM
VCIF
VCOML
VSS1 = Logic/RAM VSS, VSS2 = I/O VSS, VSS3 = OSC VSS, VSS4 = G/S VSS, VSS5 = Analog VSS,
VSS6 = Driver VSS
TOMATO LSI Inc. 7

Ver .1.0
4. PIN DESCRIPTION
Power supply pin

Connected Unused
Signal I/O Function
to pins
Power Power supply for internal logic regulator circuit.
VCC - -
supply VCC = 2.4 to 3.3V, VCC ≥ IOVCC
Supply with the power supply voltage for interface pins

Power (IM3-0, RESETB, CSB, RS, E_WRB, RW_RDB, DB17-0,
IOVCC - -
supply VSYNC, HSYNC, DOTCLK, ENABLE).
IOVCC = 1.7 to 3.3V.
System ground.
VSS1,VSS2,
Power VSS1 = Logic/RAM VSS, VSS2 = I/O VSS, VSS3 = OSC VSS,
VSS3,VSS4, - -
supply VSS4 = G/S VSS, VSS5 = Analog VSS, VSS6 = Driver VSS
VSS5,VSS6
VSS1 = VSS2 = VSS3 = VSS4 = VSS5 = VSS6 = 0V
Capacitor for Output from internal logic regulated voltage.
VCCL O Open
stabilization Connect to a stabilizing capacitor.
Power Power supply for analog circuit.
VCI I -
supply Connect an external power supply VCI = 2.5 to 3.3V
Power supply for reference circuit.
Power
VCIF I Connect an external power supply VCIF = 2.5 to 3.3V -
supply
VCI = VCIF
Capacitor for Outputs step up voltage from VCI generated in step up circuit 1.
VLO I/O -
stabilization VLO = VCI X 2, 5.0 to 6.6V.
Output step up voltage form VCI and VREG2 generated in an
Capacitor for internal step up circuit 2. Step up magnification is set by
VGH I/O -
stabilization instruction (BT). Power supply for TFT gate on.
VGH = max. 21.52V
Output step up voltage from VCI and VREG2 generated in an
Capacitor for internal step up circuit 2. Step up magnification is set by
VGL I/O -
stabilization instruction (BT). Power supply for TFT off.
VGL = min. -15.44V
Power supply for operating VCOML.
Capacitor for Output VCI x(-1) from the step-up circuit2. No capacitor
VCL I/O -
stabilization connection required if VCOMG = 0 (VCOML = VSS)
Connect VCL = VSS. VCL = 0 to -3.3V
C11+, C11- Step-up
I/O Capacitor connection pin for the internal step up circuit 1. -
C12+, C12- capacitor
C21+, C21-
C22+, C22- Step-up Capacitor connection pin for the internal step up circuit 2.
I/O -
C23+, C23- capacitor Connect a capacitor according to the step up magnification.
C31+, C31-
Capacitor for Outputs magnified voltage set by the instruction (VRH) on a
VREG1 I/O -
stabilization basis of reference voltage REGP.
Capacitor for Outputs magnified voltage set by the instruction on a basis of
VREG2 I/O -
stabilization reference voltage REGP.
TOMATO LSI Inc. 8

Ver .1.0
Power supply pin

Connected Unused
Signal I/O Function
to pins
Power supply for TFT-display common electrode. Outputs
TFT
alternating voltage at the level of VCOMH-VCOML. Register set
VCOM O opposed Open
the alternation cycle. Operation and halt are set by register
electrode
(COM).
Capacitor for Outputs high-level of VCOM. Adjust output voltage with the
VCOMH O Open
stabilization internal voltage volume or VCOMR.
Outputs low-level of VCOM. Adjust output voltage by instruction
Capacitor for (DVD) setting. By setting VCOMG = 0 at a register, it can be
VCOML O Open
stabilization fixed to VSS without capacitor connection.
VCOML = (VCL + 0.5) ~ 1[V]
Variable This pin is used for adjusting VCOMH with an external variable
VCOMR I register or register. Select VCM<5:0>=111111 and insert a variable resistor Open
Open between VREG1 and VSS to adjust VCOMH.
VSS or Reference level for grayscale voltage generating circuit. Connect
VGS I external to an external variable resistor when adjusting a level for each -
resistor panel.
Internal logic regulator control input pin.
VSS /
REGOFF I Low : Use internal logic regulator for logic voltage(VCCL) VSS
IOVCC
High : Use external voltage for logic voltage(1.8V)
TOMATO LSI Inc. 9

Ver .1.0
Interface pin
Connected Unused
Signal I/O Function
to pins
Select pin an interface mode with MPU
System Using DB
IM3 IM2 IM1 IM0 Colors
Interface pin
68 system 16-bit DB17-10, 260K
0 0 0 0
interface DB8-1 Note1)
68 system 8-bit 260K
0 0 0 1 DB17-10
interface Note2)
80 system 16-bit DB17-10, 260K
0 0 1 0
interface DB8-1 Note1)
0 0 1 1 DB17-10
interface Note2)
Serial Peripheral 260K
0 1 0 ID SDI, SDO
Interface (SPI) Note1)
0 1 1 * Setting disabled - -
IM3-1 VSS/ 68 system 18-bit
I 1 0 0 0 DB17-0 260K -
IM0/ID IOVCC interface
68 system 9-bit
1 0 0 1 DB17-9 260K
interface
80 system 18-bit
1 0 1 0 DB17-0 260K
interface
80 system 9-bit
1 0 1 1 DB17-9 260K
interface
1 1 0 0 DB17-12
interface Note3)
1 1 1 0 DB17-12
interface Note3)
1 1 * 1 Setting disabled - -
Note1) 65K colors in single transfer mode.
Note2) 65K colors in 2 transfer mode.
Note3) 260K colors in 3 transfer mode.
Select TL1763.
CSB I MPU Low : Select (accessible) IOVCC
High : Not select (not accessible)
Select the register
RS I MPU Low : Index/Status register IOVCC
High : Control register
For 68-system bus interface, it becomes an enable signal to
activate data read/write operation.
E_WRB For 80-system bus interface, it becomes a write strobe signal,
I MPU IOVCC
/SCL and writes data at the low level.
For clock synchronized serial interface, it becomes a
synchronous clock signal.
For 68-system bus interface, it becomes a signal to select data
read/write operation. High : Read, Low : Write
RW_RDB I MPU IOVCC
For 80-system bus interface, it becomes a read strobe signal,
and reads data at the low level.
A serial data input (SDI) pin in SPI mode, Data are input on the VSS,
SDI I MPU
rising edge of the SCL signal. IOVCC
A serial data output (SDO) pin in SPI mode, Data are output on
SDO O MPU -
the falling edge of the SCL signal.
TOMATO LSI Inc. 10

Ver .1.0
Interface pin
Connected Unused
Signal I/O Function
to pins
18-bit bi-directional data bus.
When CPU interface :
18-bit interface : DB17-0
16-bit interface : DB17-10,8-1
DB17 to 0 I/O MPU VSS
When RGB interface :
16-bit interface : DB17-13,11-1
Fix unused pin to the VSS level.
MPU or
Reset pin. IC is initialized at low level. Conduct power on reset
RESETB I external R-C -
after turning on the power supply.
circuit
Data enable signal when using RGB interface.
Low : Select (accessible) VSS,
ENABLE I MPU
High : Not select (not accessible) IOVCC
Polarity of enable signal is reversed by EPL register setting.
VSS,
VSYNC I MPU Frame synchronized signal.
IOVCC
VSS,
HSYNC I MPU Line synchronized signal. Low active signal.
IOVCC
Dot clock signal. Timing of data read is specified at the rising VSS,
DOTCLK I MPU
edge. IOVCC
Output frame initial pulse.
FLM O MPU Use this pin when synchronizing RAM data write operation with Open
frames.
M O MPU Output of AC cycle signal Open
CL O MPU Output of one-raster-row cycle signal Open
Connect an external resistor for R-C oscillation.
OSC1 Oscillation
I/O When use the external clock, input external clock to OSC1 and -
OSC2 resistor
open OSC2.
TOMATO LSI Inc. 11

Ver .1.0
Display pin
Connected Unused
Signal I/O Function
to pins
Source driver output pins.
Shift direction of source signal can be switched by SS bit.
SS = 0 : RAM address “h00000” is output from S1.
S1 ~ S720 O LCD Display SS = 1 : RAM address “h00000” is output from S720. Open
S1, S4, S7…. are assigned for Red<R> display,
S2, S5, S8…. are assigned for Green<G> display,
S3, S6, S9…. are assigned for Blue<B> display. (SS = 0)
Gate driver output pins.
The output of driving circuit is whether VGH or VGL.
G1 ~ G320 O LCD Display Open
VGH : Gate On level
VGL : Gate Off level
Dummy pin
Connected Unused
Signal I/O Function
to pins
Use to fix the electric potential of unused interfaces or fixed
IOVCCDUM O - Open
pins. Leave open when not used.
Use to fix the electric potential of unused interfaces or fixed
IOGNDDUM O - Open
pins. Leave open when not used.
OSCDUM1~3 O Open Test pin. Leave open. Open
Short-circuit within the LSI for measuring COG connection
DUMMYR1,2 resistance.
- - Open
DUMMYR3,4 DUMMR1 – DUMMR2 : short-circuit
DUMMR3 – DUMMR4 : short-circuit
DUMMY1~29 - - Dummy pins. Leave open. Open
TOMATO LSI Inc. 12

Ver .1.0
5. FUNCTIONAL DESCRIPTION
5-1. System interface
The TL1763 has eleven high-speed system interfaces : an 6800/8080-system 18-bit/16-bit/9-bit/8-bit/6-bit

bus and a clocked serial peripheral (SPI : serial Peripheral Interface) port. The interface mode is selected by
the IM3-0 pins.
The TL1763 has three registers: a 16-bit index register (IR), an 18-bit write-data register (WDR), and an 18-
bit read-data register (RDR). The IR stores index information from the control registers and the GRAM. The
WDR temporarily stores data to be written into control registers and the GRAM, and the MPU is first written
into the WDR and then is automatically written into the GRAM by internal operation. Data is read through the
RDR when reading from the GRAM, and the first read data is invalid and the second and the following data
are normal.
Execution time for instruction excluding oscillation start is 0 clock and instructions can be written in
succession.
Register selection (6-bit/8-bit/9-bit/16-bit/18-bit parallel interface)

Common 6800-series 8080-series
Description
RS RW E WRB RDB
0 0 1 0 1 Writing index to IR
0 1 1 1 0 Read out internal status
1 0 1 0 1 Write to control registers and GRAM through WDR
1 1 1 1 0 Read from GRAM through RDR
Register selection (SPI)

Start byte
Description
RW bit RS bit
0 0 Writing index to IR
1 0 Read out internal status
0 1 Write to control registers and GRAM through WDR
1 1 Read from GRAM through RDR
TOMATO LSI Inc. 13

Ver .1.0
5-2. External Display Interface (RGB interface, VSYNC interface)

The TL1763 incorporates RGB and VSYNC interface as an external interface for moving picture display.
When the RGB interface is selected then display operation of TL1763 operated according to synchronous
signal (VSYNC, HSYNC and DOTCLK). The display data (DB17-0) are written in according to data enable
signal (ENABLE). Accordingly, the display on screen does not flicker when RAM data are being updated
internally.
When the VSYNC interface is selected, the operation is synchronized with internal clocks except frame
synchronization, which is synchronized with VSYNC signal. The display data is written to GRAM through a
system interface. In this case, there are constraints on the speed and methods of updating RAM data when
the VSYNC interface is selected. For details, see the “External display interface” section.
5-3. Address Counter (AC)

The address counter (AC) assigns addresses to the GRAM. When an address set instruction is written into
IR, the address information is sent from IR to the AC. After writing into GRAM, the AC is automatically
incremented or decremented by 1, while after data read from GRAM, the AC is not updated. A window
address function enables data write only in the rectangular area of GRAM specified by window address.
5-4. Graphic RAM (GRAM)

GRAM is a graphic RAM that stores 1,382,400bits bit-pattern data, where one pixel is expressed by 18 bits.
It can display maximum 240RGB x 320.
5-5. Gray Scale Voltage Generation Circuit

It makes a LCD operating voltage according to gray scale level.
It can display maximum 262,144 colors simultaneously.
5-6. LCD Operating Voltage Circuit

LCD operating voltage circuit makes levels of VLO, VGH, VGL and VCOM. The levels use LCD operating.
5-7. Timing Generation Circuit

Timing generation circuit makes timing signal to operate internal circuit as GRAM.
5-8. Oscillation Circuit

Between OSC1 pin and OSC2 pin connects external resister. Then, CR oscillator starts oscillations.
You can change OSC frequency with control of external resistor value. According to operating voltage and
display line volume and frame frequency, you have to control resistor value. Furthermore, it can receive an
external operating clock. In standby mode, CR oscillator stops, and we can suppress consumption power.
For details, refer to “OSC Circuit”
5-9. Source Driver Circuit

The liquid crystal display source driver circuit consists of 720 drivers (S1 to S720).
Display pattern data is latched when 720-channel data has arrived. The latched data then enables the source
drivers to generate drive waveform outputs. The SS bit can change the shift direction of 720-channel data by
selecting an appropriate direction for the device-mounted configuration.
5-10. Gate Driver Circuit

The liquid crystal display gate driver circuit consists of 320 gate drivers (G1 to G320).
The VGH or VGL level is output by the signal from the gate control circuit.
5-11. Internal Logic Power Supply Regulator

Internal logic power supply regulator generates power supply for internal logic.
TOMATO LSI Inc. 14

Ver .1.0
5-12. GRAM Address Map
Relation between GRAM address and Screen position (SS = 0, BGR = 0)
S709
S710
S711
S712
S713
S714
S715
S716
S717
S718
S719
S720
S10
S11
S12
S1
S2
S3
S4
S5
S6
S7
S8
S9
S/G Output ……
GS=0 GS=1 DB17……DB0 DB17……DB0 DB17……DB0 DB17……DB0 …… DB17……DB0 DB17……DB0 DB17……DB0 DB17……DB0
G1 G320 “00000”H “00001”H “00002”H “00003”H …… “000EC”H “000ED”H “000EE”H “000EF”H

G11 G310 “00A00”H “00A01”H “00A02”H “00A03”H …… “00AEC”H “00AED”H “00AEE”H “00AEF”H
G12 G309 “00B00”H “00B01”H “00B02”H “00B03”H …… “00BEC”H “00BED”H “00BEE”H “00BEF”H
G13 G308 “00C00”H “00C01”H “00C02”H “00C03”H …… “00CEC”H “00CED”H “00CEE”H “00CEF”H
G14 G307 “00D00”H “00D01”H “00D02”H “00D03”H …… “00DEC”H “00DED”H “00DEE”H “00DEF”H
G15 G306 “00E00”H “00E01”H “00E02”H “00E03”H …… “00EEC”H “00EED”H “00EEE”H “00EEF”H
G16 G305 “00F00”H “00F01”H “00F02”H “00F03”H …… “00FEC”H “00FED”H “00FEE”H “00FEF”H
: : : : : : : : : : :
: : : : : : : : : : :
G315 G6 “13A00”H “13A01”H “13A02”H “13A03”H …… “13AEC”H “13AED”H “13AEE”H “13AEF”H
G316 G5 “13B00”H “13B01”H “13B02”H “13B03”H …… “13BEC”H “13BED”H “13BEE”H “13BEF”H
G317 G4 “13C00”H “13C01”H “13C02”H “13C03”H …… “13CEC”H “13CED”H “13CEE”H “13CEF”H
G318 G3 “13D00”H “13D01”H “13D02”H “13D03”H …… “13DEC”H “13DED”H “13DEE”H “13DEF”H
G319 G2 “13E00”H “13E01”H “13E02”H “13E03”H …… “13EEC”H “13EED”H “13EEE”H “13EEF”H
G320 G1 “13F00”H “13F01”H “13F02”H “13F03”H …… “13FEC”H “13FED”H “13FEE”H “13FEF”H
TOMATO LSI Inc. 15

Ver .1.0
Relation between GRAM data and Display data (SS = 0, BGR = 0)
■ 68/80 mode 18-bit interface (one time transfer/pixel), TRI = *, DFM = *

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
GRAM Data
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin S(3n+1) S(3n+2) S(3n+3)

Note1) n = lower 8 bits of address (0~239)
Note2) 262,144 color display
■ 68/80 mode 16-bit interface (one time transfer/pixel) 1, TRI = 0, DFM = *

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
GRAM Data
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1

■ 68/80 mode 16-bit interface (two times transfer/pixel) 2, TRI = 1, DFM = 0

2nd
1st transmission transmission
GRAM Data
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 17 16


1st
transmission 2nd transmission
GRAM Data
2 1 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1

TOMATO LSI Inc. 16

Ver .1.0
■ 68/80 mode 9-bit interface (two times transfer/pixel), TRI = *, DFM = *

1st transmission 2nd transmission
GRAM Data
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9

■ 68/80 mode 8-bit interface / SPI (two times transfer/pixel), TRI = 0, DFM = *
GRAM Data
17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10

■ 68/80 mode 8-bit interface (three times transfer/pixel), TRI = 1, DFM = 0

1st transmission 2nd transmission 3rd transmission
GRAM Data
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12


GRAM Data
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12

TOMATO LSI Inc. 17

Ver .1.0
■ 68/80 mode 6-bit interface (three times transfer/pixel), TRI = 0, DFM = *

GRAM Data
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12


GRAM Data
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12

TOMATO LSI Inc. 18

Ver .1.0
■ 18-bit RGB interface (one time transfer/pixel)

GRAM Data
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

■ 16-bit RGB interface (one times transfer/pixel)

GRAM Data
17 16 15 14 13 11 10 9 8 7 6 5 4 3 2 1

■ 6-bit RGB interface (three times transfer/pixel)

GRAM Data
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12

TOMATO LSI Inc. 19

Ver .1.0
Relation between GRAM address and Screen position (SS = 1, BGR = 1)
S709
S710
S711
S712
S713
S714
S715
S716
S717
S718
S719
S720
S10
S11
S12
S1
S2
S3
S4
S5
S6
S7
S8
S9
S/G Output ……
GS=0 GS=1 DB17……DB0 DB17……DB0 DB17……DB0 DB17……DB0 …… DB17……DB0 DB17……DB0 DB17……DB0 DB17……DB0
G1 G320 “000EF”H “000EE”H “000ED”H “000EC”H …… “00003”H “00002”H “00001”H “00000”H

G11 G310 “00AEF”H “00AEE”H “00AED”H “00AEC”H …… “00A03”H “00A02”H “00A01”H “00A00”H
G12 G309 “00BEF”H “00BEE”H “00BED”H “00BEC”H …… “00B03”H “00B02”H “00B01”H “00B00”H
G13 G308 “00CEF”H “00CEE”H “00CED”H “00CEC”H …… “00C03”H “00C02”H “00C01”H “00C00”H
G14 G307 “00DEF”H “00DEE”H “00DED”H “00DEC”H …… “00D03”H “00D02”H “00D01”H “00D00”H
G15 G306 “00EEF”H “00EEE”H “00EED”H “00EEC”H …… “00E03”H “00E02”H “00E01”H “00E00”H
G16 G305 “00FEF”H “00FEE”H “00FED”H “00FEC”H …… “00F03”H “00F02”H “00F01”H “00F00”H
: : : : : : : : : : :
: : : : : : : : : : :
G315 G6 “13AEF”H “13AEE”H “13AED”H “13AEC”H …… “13A03”H “13A02”H “13A01”H “13A00”H
G316 G5 “13BEF”H “13BEE”H “13BED”H “13BEC”H …… “13B03”H “13B02”H “13B01”H “13B00”H
G317 G4 “13CEF”H “13CEE”H “13CED”H “13CEC”H …… “13C03”H “13C02”H “13C01”H “13C00”H
G318 G3 “13DEF”H “13DEE”H “13DED”H “13DEC”H …… “13D03”H “13D02”H “13D01”H “13D00”H
G319 G2 “13EEF”H “13EEE”H “13EED”H “13EEC”H …… “13E03”H “13E02”H “13E01”H “13E00”H
G320 G1 “13FEF”H “13FEE”H “13FED”H “13FEC”H …… “13F03”H “13F02”H “13F01”H “13F00”H
TOMATO LSI Inc. 20

Ver .1.0
Relation between GRAM data and Display data (SS = 1, BGR = 1)
■ 68/80 mode 18-bit interface (one time transfer/pixel), TRI = *, DFM = *

GRAM Data
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Output pin S(720-3n) S(719-3n) S(718-3n)

■ 68/80 mode 16-bit interface (one time transfer/pixel) 1, TRI = 0, DFM = *

GRAM Data
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1


nd
st 2
1 transmission transmission
GRAM Data
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 17 16


1st
GRAM Data
2 1 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1

TOMATO LSI Inc. 21

Ver .1.0
■ 68/80 mode 9-bit interface (two times transfer/pixel), TRI = *, DFM = *

GRAM Data
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9

■ 68/80 mode 8-bit interface/SPI (two times transfer/pixel), TRI = 0, DFM = *

GRAM Data
17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10


GRAM Data
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12


GRAM Data
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12

TOMATO LSI Inc. 22

Ver .1.0

GRAM Data
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12


GRAM Data
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12

TOMATO LSI Inc. 23

Ver .1.0
■ 18-bit RGB interface (one time transfers/pixel), TRI = *, DFM = *

GRAM Data
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

■ 16-bit RGB interface (one time transfer/pixel), TRI = *, DFM = *

GRAM Data
17 16 15 14 13 11 10 9 8 7 6 5 4 3 2 1

■ 6-bit RGB interface (three times transfer/pixel), TRI = *, DFM = *

GRAM Data
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12

TOMATO LSI Inc. 24

Ver .1.0
6. INSTRUCTIONS
The TL1763 uses the 18-bit bus architecture. Before the internal operation of the TL1763 starts, control
information is temporarily stored in the registers described below to allow high-speed interfacing with a high-
performance microcomputer. The internal operation of the TL1763 is determined by signals sent from the
microcomputer. These signals, which include the register selection signal (RS), the read/write signal (R/W),
and the data bus signals (DB17 to DB0), make up the TL1763 instructions. The accesses to the GRAM use
the internal 18-bit data bus. There are 8 categories of instructions.
(1) Specify the index

(2) Read the status
(3) Control the display
(4) Control power management
(5) Set address for internal GRAM
(6) Transmit and receiving data with internal GRAM
(7) Adjust gamma characteristics for display panels
(8) Set window address
Normally, instruction to write data on GRAM is used the most. The address of internal GRAM is updated
automatically after data are written to the GRAM. With window address function, this reduces the amount of
data transmission to minimum and thereby reduces the load on the program processed by the microcomputer.
Since the instructions are executed in 0 cycle, it is possible to write instructions consecutively.
TOMATO LSI Inc. 25

Ver .1.0
The 16-bit instruction assignment differs from interface-setup (6/8/9/16/18-bit, SPI), so instructions should be
fetched according to the data format shown below:
■ 68/80 mode 18-bit interface

Input pin
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB
Instruction Bit(IB)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
■ 68/80 mode 16-bit interface

Input pin
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
Instruction Bit(IB)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
■ 68/80 mode 9-bit interface (two times transfers)

st nd
1 transmission 2 transmission
Input pin
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
Instruction Bit(IB)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
■ 68/80 mode 8-bit interface / SPI (two times transfers)

st nd
Input pin
17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
Instruction Bit(IB)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
■ 68/80 mode 6-bit interface (three times transfers)

st nd rd
1 transmission 2 transmission 3 transmission
Input pin
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
Instruction Bit(IB)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOMATO LSI Inc. 26

Ver .1.0
Instruction Table
Reg
R
R Upper Code Lower Code
Register Name /
No. S
W IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
IR Index W 0 * * * * * * * * ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
SR Status Read R 0 0 0 0 0 0 0 0 L8 L7 L6 L5 L4 L3 L2 L1 L0
SVL2 SVL1 SVL0 EXT OSC

00h Start Power W 1 0 0 0 0 0 0 0 0 0 0 0
(0) (1) (1) (0) (1)
VSPL HSPL DPL EPL GS SS
01h Driver Output Control 1 W 1 0 0 0 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0)
LCD Driving-waveform FLD1 FLD0 B/C EOR NW5 NW4 NW3 NW2 NW1 NW0
02h Control
W 1 0 0 0 0 0 0
(0) (1) (0) (0) (0) (0) (0) (0) (0) (0)
TRI DFM BGR I/D1 I/D0 AM
03h Entry Mode W 1 0 0 0 0 0 0 0 0 0 0
(0) (0) (0) (1) (1) (0)
NL8 NL7 NL6 NL5 NL4 NL3 NL2 NL1 NL0
04h Driver Output Control 2 W 1 0 0 0 0 0 0 0
(1) (0) (1) (0) (0) (0) (0) (0) (0)
PT1 PT0 VLE2 VLE1 SPT GON DTE CL REV D1 D0
07h Display Control 1 W 1 0 0 0 0 0
(0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
FP3 FP2 FP1 FP0 BP3 BP2 BP1 BP0
08h Display Control 2 W 1 0 0 0 0 0 0 0 0
(1) (0) (0) (0) (1) (0) (0) (0)
PTG1 PTG0 ISC3 ISC2 ISC1 ISC0
09h Display Control 3 W 1 0 0 0 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0)
NO2 NO1 NO0 SDT2 SDT1 SDT0 DIV1 DIV0 RTN3 RTN2 RTN1 RTN0
0Bh Frame Cycle Control W 1 0 0 0 0
(0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
External Display RM DM1 DM0 RIM1 RIM0
0Ch W 1 0 0 0 0 0 0 0 0 0 0 0
Interface Control 1 (0) (0) (0) (0) (0)
VEM EQ2 EQ1 EQ0
0Eh Equalize Control W 1 0 0 0 0 0 0 0 0 0 0 0 0
(1) (0) (0) (0)
GAP2 GAP1 GAP0 BT3 BT2 BT1 BT0 AP2 AP1 AP0 SLP STB
10h Power Control 1 W 1 0 0 0 0
(0) (0) (0) (1) (0) (1) (0) (0) (0) (0) (0) (0)
DC12 DC11 DC10 DC02 DC01 DC00 VC2 VC1 VC0
11h Power Control 2 W 1 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0) (0) (0) (0)
COM PON VRH3 VRH2 VRH1 VRH0
12h Power Control 3 W 1 0 0 0 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0)
VCOMG VDV4 VDV3 VDV2 VDV1 VDV0 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0
13h Power Control 4 W 1 0 0 0 0
(0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
20h Horizontal Address Set W 1 0 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0) (0) (0)
AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8
21h Vertical Address Set W 1 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0) (0) (0) (0)
RAM Data Write W 1 Write Data to RAM

22h
RAM Data Read R 1 Read data from RAM
TOMATO LSI Inc. 27

Ver .1.0
Instruction Table (Continued)
Reg
R
R Upper Code Lower Code
Register Name /
No. S
W IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
PKP12 PKP11 PKP10 PKP02 PKP01 PKP00
30h Gamma Control 1 W 1 0 0 0 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0)
31h Gamma Control 2 W 1 0 0 0 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0)
32h Gamma Control 3 W 1 0 0 0 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0)
PRP12 PRP11 PRP10 PRP02 PRP01 PRP00
33h Gamma Control 4 W 1 0 0 0 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0)
PKN12 PKN11 PKN10 PKN02 PKN01 PKN00
34h Gamma Control 5 W 1 0 0 0 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0)
35h Gamma Control 6 W 1 0 0 0 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0)
36h Gamma Control 7 W 1 0 0 0 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0)
PRN12 PRN11 PRN10 PRN02 PRN01 PRN00
37h Gamma Control 8 W 1 0 0 0 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0)
VRP14 VRP13 VRP12 VRP11 VRP10 VRP04 VRP03 VRP02 VRP01 VRP00
38h Gamma Control 9 W 1 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
VRN14 VRN13 VRN12 VRN11 VRN10 VRN04 VRN03 VRN02 VRN01 VRN00
39h Gamma Control 10 W 1 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
SCN5 SCN4 SCN3 SCN2 SCN1 SCN0

40h Gate Scan Position W 1 0 0 0 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0)
VL8 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0
41h Vertical Scroll Control W 1 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0) (0) (0) (0)
1st Screen Driving SE18 SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10
42h Position 1
W 1 0 0 0 0 0 0 0
(1) (0) (0) (1) (1) (1) (1) (1) (1)
1st
Screen Driving SS18 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10
43h Position 2
W 1 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0) (0) (0) (0)
2nd
Screen Driving SE28 SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20
44h Position 1
W 1 0 0 0 0 0 0 0
(1) (0) (0) (1) (1) (1) (1) (1) (1)
2nd
Screen Driving SS28 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20
45h Position 2
W 1 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0) (0) (0) (0)
Horizontal RAM HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0
46h Address Position
W 1
(1) (1) (1) (0) (1) (1) (1) (1) (0) (0) (0) (0) (0) (0) (0) (0)
Vertical RAM Address VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0
47h Position 1
W 1 0 0 0 0 0 0 0
(1) (0) (0) (1) (1) (1) (1) (1) (1)
Vertical RAM Address VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0
48h Position 2
W 1 0 0 0 0 0 0 0
(0) (0) (0) (0) (0) (0) (0) (0) (0)
Source Driver Control SDVON SAP2 SAP1 SAP0
A1h 1
W 1 0 0 0 0 0 0 0 0 0 0 0 0
(0) (0) (0) (0)
Source Driver Control SRC3 SRC2 SRC1 SRC0 PSC3 PSC2 PSC1 PSC0
A4h 2
W 1 0 0 0 0 0 0 0 0
(1) (0) (1) (0) (0) (1) (0) (1)
Note 1) Numerals in parentheses are initial values.

Note 2) Do not access to the setting-disabled indexes.
TOMATO LSI Inc. 28

Ver .1.0
6-1. Index/Status/Display control instruction

(1) Index (IR)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W 0 * * * * * * * * ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
The index instruction specifies the control register and the RAM control indexes to be accessed (R00h to
RFFh). The register number is set in binary from “0000_0000” to “1111_1111” in binary form.
Those instruction bits of the index register which not allocated to the index register should not be accessed.
(2) Status Read (SR)

R 0 0 0 0 0 0 0 0 L8 L7 L6 L5 L4 L3 L2 L1 L0
Read the internal status of TL1763.

L [8:0]: Indicate the position of operating line, which is now operating LCD.
(3) Start Power (R00h)

W 1 0 SVL2 SVL1 SVL0 0 0 0 0 0 0 0 0 0 0 EXT OSC
R 1 0 0 0 1 0 1 1 1 0 1 1 0 0 0 1 1
SVL [2:0]: Internal logic voltage (VCCL) level control (default(011), VCCL = VCC x 0.65).
According to change of VCC voltage, set the SVL bits so that VCCL voltage is 1.8V±0.1V
Ex) When VCC=2.4V, then set SVL[2:0]=3’b101 (x0.75) so that VCCL = 2.4 x 0.75 = 1.80V
When VCC=2.8V, then set SVL[2:0]=3’b011 (x0.65) so that VCCL = 2.8 x 0.65 = 1.82V
SVL[2:0] Internal logic voltage (VCCL) SVL[2:0] Internal logic voltage (VCCL)
000 0.65 x VCC 100 0.70 x VCC
001 0.55 x VCC 101 0.75 x VCC
010 0.60 x VCC 110 0.80 x VCC
011 0.65 x VCC (Default) 111 0.85 x VCC
EXT: External clock select bit.

EXT = 0 : External clock Off, Internal oscillator use (default)
EXT = 1 : External clock On
OSC: Internal oscillator on/off bit.
OSC = 0 : Internal oscillator Off. External clock input.
OSC = 1 : Internal oscillator On (default)
The start oscillation restarts the oscillator from the halt state in the standby mode.
After issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction.
(See the Standby Mode section.)
If this register is read forcibly, “1763”H is read.
TOMATO LSI Inc. 29
Ver .1.0
(4) Driver Output Control 1 (R01h)
W 1 0 VSPL HSPL DPL EPL 0 GS SS 0 0 0 0 0 0 0 0
VSPL: Set the signal polarity of VSYNC pin.

VSPL = 0 : Low is active
VSPL = 1 : High is active
HSPL: Set the signal polarity of HSYNC pin.

HSPL = 0 : Low is active
HSPL = 1 : High is active
DPL: Set the signal polarity of DOTCLK pin.

DPL = 0 : Data are input on the rising edge of DOTCLK
DPL = 1 : Data are input on the falling edge of DOTCLK
EPL: Set the signal polarity of ENABLE pin.

EPL = 0 : Data writing from DB17 to DB0 is valid by ENABLE = 0. No data writing is valid by ENABLE = 1.
EPL = 1 : Data writing from DB17 to DB0 is valid by ENABLE = 1. No data writing is valid by ENABLE = 0.
Relationship EPL, ENABLE and RAM Access

EPL ENABLE RAM write RAM address
0 0 Valid Updated
0 1 Invalid Held
1 1 Valid Updated
1 0 Invalid Held
GS: Select the output shift direction of the gate driver.

GS = 0 : Assign G1 to G320 for scan direction.
GS = 1 : Assign G320 to G1 for scan direction.
SS: Select the output shift direction of the source driver.

SS = 0 : The output shift direction is from S1 to S720.
SS = 1 : The output shift direction is from S720 to S1.
Settings for both SS and BGR bits specify the assignment of RGB dots to the S1 ~ S720 pins.
When SS = 0 and BGR = 0, RGB are assigned interchangeably in this order from S1 to S720.
When SS = 1 and BGR = 1, RGB are assigned interchangeably in this order from S720 to S1.
Rewrite data to the RAM whenever you change the SS and BGR bits.
TOMATO LSI Inc. 30

Ver .1.0
(5) LCD Driving-waveform Control (R02h)
NW NW NW NW NW NW
W 1 0 0 0 0 FLD1 FLD0 B/C EOR 0 0
5 4 3 2 1 0
FLD [1:0]: Set number of the field that the n field inter-laced driving. For details, see the “Interlace Driver”
section.
FLD1 FLD0 Number of field

0 0 Setting disabled
0 1 1 Field (Default)
1 1 3 Field (Interlaced)
B/C: When B/C = 0, a frame inversion waveform is generated and the LCD-driving signal alternates at every
frame. When B/C = 1, an n-raster-row AC waveform is generated and its polarity alternates on each raster-
row specified by bits EOR and NW5-0 of the LCD-driving-waveform control register. For details, see the “N-
raster-row Reversed AC Drive” section.
EOR: When the line inversion waveform is set (B/C = 1) and EOR = 1, the odd/even frame-select signals
and the n-raster-row reversed signals are EOR (Exclusive-OR) for alternating drive. EOR is used when the
LCD is not alternated the set values of the LCD drive duty ratio and the n raster-row. For details, see the “N-
raster-row Reversed AC Drive” section.
NW [5:0]: Specify the number of raster-rows n that will alternate in the line inversion waveform setting (B/C =
1). NW5-0 alternate for every set value + 1 raster-row, and the first to the 64th raster-rows can be selected.
For details, see the “N-raster-row Reversed AC Drive” section.
TOMATO LSI Inc. 31

Ver .1.0
(6) Entry Mode (R03h)
W 1 TRI DFM 0 BGR 0 0 0 0 0 0 I/D1 I/D0 AM 0 0 0
The TL1763 modifies write data sent from the microcomputer before writing to GRAM. This enables high-
speed GRAM data update, and reduces the load on the microcomputer software.
TRI: RAM write data are transmitted in 3 times through 8-bit interface when TRI = 1. In case of 6-bit interface,
RAM write data format is for 65K color when TRI = 1. In case of 16-bit interface, RAM write data are
transmitted in 2 times through 16-bit interface when TRI = 1. TRI mode is used with DFM instruction. When
6-bit/8-bit/16-bit interface modes are not selected, set TRI to 0.
DFM: Specify the data format for the RAM write data transmission when TRI = 1 (SPI, 6-bit/8-bit/16-bit
interface mode only).
TRI DFM Serial Peripheral Interface(SPI) RAM write data transfer

SPI(2 transfer/pixel) 65,536 color
1st transm ission 2nd transm ission

D D D D D D
G RAM D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
15 14 13 12 11 10
0 *
RG B R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
SPI(3 transfer/pixel) 262,144 color
1st transm ission 2nd transm ission 3rd transm ission

D D D D D D D D D D D D D D D D D D
GRAM
21 20 19 18 17 16 13 12 11 10 9 8 5 4 3 2 1 0
1 *
RG B R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Note 1) Instruction setting is transmitted by 2 x 8 bits transmission regardless of TRI and DFM settings.
TOMATO LSI Inc. 32

Ver .1.0
TRI DFM 6-bit interface data format

68/80-system 6-bit interface(3 transfer/pixel) 262,144 color

GRAM
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
0 *
RGB R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

GRAM
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
1 *
TOMATO LSI Inc. 33

Ver .1.0


GRAM
17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
0 *

GRAM
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
0
1

GRAM
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
1
TOMATO LSI Inc. 34

Ver .1.0

GRAM
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
0 *
68/80-system 16-bit interface MSB mode(2 transfer/pixel) 262,144 color

2nd
GRAM
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 17 16
0
1
68/80-system 16-bit interface LSB mode(2 transfer/pixel) 262,144 color
1st
transmission
2nd transmission
GRAM
2 1 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
1
BGR: Change the order of 18-bit write data from I, (G) and (B) to (B), (G) and I.
BGR = 0 : The dot order I,(G),(B) is not changed when 18bit data are written to GRAM.
BGR = 1 : The dot order changes from I,(G),(B) to (B),(G),I.
I/D [1:0]: I/D set automatic increment (+1) and automatic decrement (-1) of address counter (AC) after
writing data to GRAM.
I/D = 0 : the address counter is incremented or decrement in horizontal direction (lower address: AD7-0)
I/D = 1 : the address counter is incremented or decrement in vertical direction (upper address: AD16-8)
The AM bit specifies the address transition direction when data are being written to GRAM.
AM: Set the automatic update method of the address counter after the data is written to GRAM.
AM = 0 : the address counter is updated in horizontal direction.
AM = 1 : the address counter is updated in vertical direction.
TOMATO LSI Inc. 35

Ver .1.0
When window address range is specified, data are written in the window address range specified within the
GRAM by I/D1-0 and AM settings.
I/D = 00 I/D = 01 I/D = 10 I/D = 11

Direction Horizontal : Decrement Horizontal : Increment Horizontal : Decrement Horizontal : Increment
setting Vertical : Decrement Vertical : Decrement Vertical : Increment Vertical : Increment
AM = 0
Horizontal
AM = 1
Vertical
Address direction setting
Note 1) When window address is set, write operation is executable only within GRAM window address
TOMATO LSI Inc. 36

Ver .1.0
(7) Driver Output Control 2 (R04h)
W 1 0 0 0 0 0 0 0 NL8 NL7 NL6 NL5 NL4 NL3 NL2 NL1 NL0
NL [8:0]: Specify number of lines for the LCD drive. Number of lines for the LCD drive can be adjusted for
every one raster-row. DDRAM address mapping does not depend on the setting value of the drive
duty ratio. Select the set value for the panel size or higher.
NL bits and Drive Duty (When SCN5-0 = 6’b000000)

NL NL NL NL NL NL NL NL NL Number of LCD Gate driver
Display size (dot)
8 7 6 5 4 3 2 1 0 operation line used
0 0 0 0 0 0 0 0 0 Setting disable Setting disable Setting disable
0 0 0 0 0 0 0 0 1 240 x 1 1 G1
0 0 0 0 0 0 0 1 0 240 x 2 2 G1 ~ G2
0 0 0 0 0 0 0 1 1 240 x 3 3 G1 ~ G3
0 0 0 0 0 0 1 0 0 240 x 4 4 G1 ~ G4
0 0 0 0 0 0 1 0 1 240 x 5 5 G1 ~ G5
0 0 0 0 0 0 1 1 0 240 x 6 6 G1 ~ G6
0 0 0 0 0 0 1 1 1 240 x 7 7 G1 ~ G7
0 0 0 0 0 1 0 0 0 240 x 8 8 G1 ~ G8
0 0 0 0 0 1 0 0 1 240 x 9 9 G1 ~ G9
0 0 0 0 0 1 0 1 0 240 x 10 10 G1 ~ G10
: : : : : : : : : : : :
: : : : : : : : : : : :
1 0 0 1 1 0 1 1 0 240 x 310 310 G1 ~ G310
1 0 0 1 1 0 1 1 1 240 x 311 311 G1 ~ G311
1 0 0 1 1 1 0 0 0 240 x 312 312 G1 ~ G312
1 0 0 1 1 1 0 0 1 240 x 313 313 G1 ~ G313
1 0 0 1 1 1 0 1 0 240 x 314 314 G1 ~ G314
1 0 0 1 1 1 0 1 1 240 x 315 315 G1 ~ G315
1 0 0 1 1 1 1 0 0 240 x 316 316 G1 ~ G316
1 0 0 1 1 1 1 0 1 240 x 317 317 G1 ~ G317
1 0 0 1 1 1 1 1 0 240 x 318 318 G1 ~ G318
1 0 0 1 1 1 1 1 1 240 x 319 319 G1 ~ G319
1 0 1 0 0 0 0 0 0 240 x 320 320 G1 ~ G320
9’b101000001 ~ 9’b111111111 Setting disable
Note 1) A FP(front porch) and BP(back porch) period will be inserted as blanking period (All gates output
VGL level and all source output Hi-Z) before / after the driver scan through all of the scans.
TOMATO LSI Inc. 37

Ver .1.0
(8) Display Control 1 (R07h)
W 1 0 0 0 PT1 PT0 VLE2 VLE1 SPT 0 0 GON DTE CL REV D1 D0
PT [1:0]: Normalize the source outputs when non-displayed area of the partial display is driven. For details,
see the Screen-division Driving Function section.
Source output for VCOM output for

non-display area non-display area Gate output for
PT1 PT0
Positive Negative Positive Negative non-display area
polarity polarity polarity polarity
0 0 V63 V0 VSS VCOMH PTG setting
1 0 VSS VSS VSS VSS PTG setting
1 1 Hi-Z Hi-Z VSS VSS PTG setting
VLE [2:1]: When VLE1 = 1, a vertical scroll is performed in the 1st screen. When VLE2 = 1, a vertical scroll is
performed in the 2nd screen. Vertical scrolling on the two screens cannot be controlled at the same time.
VLE2 VLE1 2nd Screen 1st Screen

0 0 Fixed display (default) Fixed display (default)
0 1 Fixed display Scroll display
1 0 Scroll display Fixed display
SPT: When SPT = 1, the 2-division LCD driver is performed. For details, see the Screen-division Driving
Function section.
Note: This function is not available when the external display interface (RGB or VSYNC interface) is in use.
GON / DTE: Gate outputs on/off control signal.
GON DTE Gate output

0 0 VGH (All gate output on level)
0 1 VGH (All gate output on level)
1 0 VGL (All gate output off level)
1 1 VGH/VGL (Normal operation)
CL: When CL = 1, 8-color mode is operative. Follow the setting sequence of 8-color display mode. This bit
stops the grayscale amplifier other than V0 and V63 level, and slows down (1/2 fDCDC) the step up clock
cycle. 8-color display mode, frame alternating cycle, and interval scan are available to display at low power
consumption.
CL Colors
0 260K
1 8
TOMATO LSI Inc. 38

Ver .1.0
REV: When REV = 1, the screen in the display area is reversed. A same data set can be used for display on
both normally white and normally black panels because grayscale level can be inverted.
Source output level in display area

REV GRAM data
Positive polarity Negative polarity
18’h00000 V63 V0
: : :
0
: : :
18’h3FFFF V0 V63
18’h00000 V0 V63
: : :
1
: : :
18’h3FFFF V63 V0
D [1:0]: When D1 = 1, it starts graphic display, and when D1 = 0, it turns off all displays. Display data is
stored in GRAM after display is off, and it can be displayed again when D1 = 1.
When D1 = 0 and all displays are turned off, the source output are all set to VSS. Therefore charge and
discharge current on LCD regarding LCD AC drive, will be reduced. When D = 2’b01, all displays are off, but
the internal display operation of TL1763 continues. When D = 2’b00 the internal display operation stops, and
all displays are off. See the section “Instruction setting flow” for details.
D[1:0] controls display On and Off with GON and DTE. See the section “Instruction setting flow” for details.
D1 D0 Source output Gate output VCOM output Internal display operation

0 0 VSS VGL VSS Halt
0 1 VSS VGL VSS Halt
1 0 Blank display Operate Operate Operate
1 1 Normal display Operate Operate Operate
Note 1) Data from a microcomputer can be written to GRAM irrespective of D bit setting.
Note 2) D = 2’b00 while standby mode. But register setting of D bit does not change.
TOMATO LSI Inc. 39

Ver .1.0
W 1 0 0 0 0 FP3 FP2 FP1 FP0 0 0 0 0 BP3 BP2 BP1 BP0
The blanking period in the start and end of the display area can be defined using this register.
When N-raster-row is driving, a blank period is inserted after all screens are drawn. Front and Back porch
can be adjusted using FP3-0 and BP3-0 bits (R08h).
FP [3:0]: Set the number of lines for front porch. (The blank period made before the end of display).
BP [3:0]: Set the number of lines for back porch. (The blank period made after the beginning of display).
When using the external display interface, a back porch (BP) starts at the falling edge of VSYNC and display
operation starts at the end of the back porch period. The front porch (FP) starts when data for the number of
raster-rows specified by the NL bits has been displayed. After the front porch period, the blank period
continues until next VSYNC input.
Number of Front porch line VSYNC

FP[3:0], BP[3:0]
Number of Back porch line
0000 Setting disable Back Porch
0001 Setting disable
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8 Display area
1001 9
1010 10
1011 11
1100 12
1101 13
1110 14
1111 Setting disable Front Porch
Precaution for setting BP, FP
■ Set BP and FP within the range indicated below.
FLD = 01 BP >= 2 line FP >= 2 line FP + BP <= 16 line

Internal clock operation
FLD = 11 BP = 3 line FP = 5 line FP + BP = 8 line
RGB interface BP >= 2 line FP >= 2 line FP + BP <= 16 line
VSYNC interface BP >= 2 line FP >= 2 line FP + BP = 16 line
TOMATO LSI Inc. 40

Ver .1.0
W 1 0 0 0 0 0 0 0 0 0 0 PTG1 PTG0 ISC3 ISC2 ISC1 ISC0
PTG [1:0]: Set the Gate scan mode at non-display area.
Gate output for Source output for

PTG1 PTG0 VCOM output
non-display area non-display area
0 0 Normal scan PT setting
0 1 Fixed to VGL PT setting
1 0 Interval scan mode PT setting
1 1 Setting disable -
ISC [3:0]: Set the scan frequency of non-display area gate bus lines. Interval scan mode is odd or even
frame and source output of interval scan frame. Gate output during the interval scan is same to the normal
scan mode.
Interval gate scan frequency

ISC[3:0] Scan period (fFLM) = 60Hz
4’h0 0 frame -
4’h1 3 frame 50 ms
4’hA 21 frame 351 ms
4’hB 23 frame 384 ms
4’hC 25 frame 418 ms
4’hD 27 frame 451 ms
4’hE 29 frame 484 ms
4’hF 31 frame 518 ms
TOMATO LSI Inc. 41

Ver .1.0
(11) Frame Cycle Control (R0Bh)
W 1 NO2 NO1 NO0 SDT2 SDT1 SDT0 0 0 DIV1 DIV0 0 0 RTN3 RTN2 RTN1 RTN0
NO [2:0]: Set non-overlap period of gate output.
Non-overlap time
NO2 NO1 NO0 RGB interface operation
Internal clock operation (1 clock = DOTCLK)
(1 clock = internal operating clock)
18-bit interface 6-bit interface
0 0 0 0 clock (default) 0 clock 0 clock
0 0 1 1 clocks 8 clocks 10 clocks
Note 1) The amount of delay of source output is measured from a falling edge of CL.
SDT [2:0]: Set the delay of source output from a falling edge of the gate output.
Source output delay time

SDT2 SDT1 SDT0 RGB interface operation
0 0 0 1 clock (default) 8 clocks 14 clocks
Note 1) The amount of delay of source output is measured from a falling edge of CL.
TOMATO LSI Inc. 42

Ver .1.0
DIV [1:0]: Set the division ratio of clocks for internal operation. Internal operation is executed according to
division clock set by DIV. Frame frequency can be adjusted in conjunction with IH period (RTN). In case of
changing the number of drive raster-rows, an adjustment is necessary to the frame frequency. This function
is not available while using RGB interface.
DIV1 DIV0 Division ratio Clock frequency for internal operation

0 0 Divide by 1 fOSC / 1 (default)
0 1 Divide by 2 fOSC / 2
RTN [3:0]: Set 1H (line) period.
RTN3 RTN2 RTN1 RTN0 Number of clock per Line

0 0 0 0 22 (default)
0 0 0 1 23
0 0 1 0 24
: : : : :
: : : : :
1 1 1 0 36
1 1 1 1 37
Formula for the frame frequency

fOSC
Frame frequency = [Hz]
Number of clock per line x Division ratio x (Line + B)
fOSC : R-C oscillation frequency

Number of clock per line : RTN bit
Division ratio : DIV bit
Line : Number of drive raster-row (NL bit)
B : Blank period (Back porch + Front porch)
TOMATO LSI Inc. 43

Ver .1.0
(12) External Display Interface Control (R0Ch)
RIM RIM
W 1 0 0 0 0 0 0 0 RM 0 0 DM1 DM0 0 0 1 0
RM: Set a RAM access interface. RAM access is made only through the interface specified by the RM
setting. Set RM to 1 when writing display data through the RGB interface. This setting is valid irrespective of
the display operation mode. Changes in display data can be made by setting RM to 0, which enables RAM
data overwrite through a system interface, even while the screens are displayed through the RGB interface
mode.
RM Interface for RAM access

0 System interface / VSYNC interface
1 RGB interface
DM [1:0]: Set a display operation mode. An interface for display operation is selected by the DM setting. DM
allows switching between the internal clock operation mode and the external display interface mode. Do not
try to switch between the external interface mode (RGB interface and VSYNC interface)
DM1 DM0 Display interface

0 0 Internal clock operation
0 1 RGB interface
1 0 VSYNC interface
RIM [1:0]: Set RGB interface mode when RGB interface is selected with DM and RM bits. Setting must be
done before the display through an external display interface and no change in setting should be done during
the display.
RIM1 RIM0 RGB interface mode Colors

0 0 18-bit RGB interface (one transfer/pixel) 262,144
0 1 16-bit RGB interface (one transfer/pixel) 65,536
1 0 6-bit RGB interface (three transfers/pixel) 262,144
1 1 Setting disabled -
Note 1) Setting of instruction register is possible by only system interface.
Note 2) Data transmission and DOTCLK input must be done by RGB unit when 6-bit RGB interface is selected.
TOMATO LSI Inc. 44

Ver .1.0
An interface is set according to each following display state by setting external display interface control.
Display operation mode

Display state Operation mode RAM access setting (RM)
(DM1-0)
Still picture Internal clock System interface (RM = 0) Internal Clock (DM1-0 = 00)
Moving picture RGB interface (1) RGB interface (RM = 1) RGB interface (DM1-0 = 01)
Write-over on still area
RGB interface (2) System interface (RM = 0) RGB interface (DM1-0 = 01)
during moving picture display
Moving pictures VSYNC interface SYSTEM interface (RM = 0) VSYNC interface (DM1-0 = 10)
Note 1) The setting of instruction register is possible only through system interface.
Note 2) No alternation between RGB interface and VSYNC interface is possible.
Note 3) No change in setting of RGB interface mode (RIM) is possible during RGB interface operation.
Note 4) See “External display interface” section, for reference flowchart of each operation mode is changed.
Internal clock mode: All display operation is executed in synchronization with signal generated by internal
operating clock in internal operation mode. Input through external display interface is invalid. Access to RAM
is executable exclusively through system interface.
RGB interface mode (1): Display operation is executed by frame synchronizing signal (VSYNC), line
synchronizing signal (HSYNC) and dot clock (DOTCLK) in RGB interface mode. During display in RGB
interface mode, all these signals must be supplied consecutively.
A pixel unit from DB17 to DB0 executes transmission of display data. All display data are stored in RAM.
Window address functions enable simultaneous display of moving picture area and RAM data. This enables
transmission of display data during write-over operation, thereby reduces the number of data transmission
operations to minimum.
Front porch (FP), back porch (BP) and display duration (NL) are automatically generated within the TL1763
by internally counting the line synchronizing signal (HSYNC) from the frame synchronizing signal (VSYNC).
Transmit the pixel data through DB17-0 in accordance to the aforementioned settings.
RGB interface mode (2): Write-over of RAM data is also possible through system interface when RGB
interface is selected. Write-over must be done during ENABLE = High period when display data transmission
is not executed through RGB interface. To return to display data transmission through RGB interface,
change the aforementioned setting and then make a new address set and the index.
VSYNC interface mode: Synchronization of internal display operation can be executed by frame
synchronizing signal (VSYNC) in VSYNC interface mode. By writing on RAM at a regular speed through
system interface from falling edge of frame synchronizing signal (VSYNC), moving picture display is possible
with a conventional system interface. See “External display interface” section with regard to the restriction on
the speed and methods of writing on RAM with the conventional system interface.
Only VSYNC input is valid in VSYNC interface mode. Other signal input than VSYNC input through external
display interface is invalid.
Front porch (FP), back porch (BP) and display duration (NL) are automatically generated according to each
register setting inside TL1763 from frame synchronizing signal VSYNC.
TOMATO LSI Inc. 45

Ver .1.0
(13) Equalize Control (R0Eh)
W 1 0 0 0 0 0 0 0 0 0 0 0 VEM 0 EQ2 EQ1 EQ0
VEM: Set the VCOM equalization mode.
VEM VCOM equalization mode

0 Not equalized
1 VCI/GND short-circuit (default)
Note 1) Power consumption saving effects may vary according to a displayed picture and the size of a panel.
VCOM is short-circuited with GND during VCOM falling in the EQ period and short-circuited with VCI during
VCOM rising in the EQ period to save power consumption.
When using this mode, VCI and GND must be VCI < VCOMH, GND > VCOML.
EQ [2:0]: Set the VCOM equalization period to the number of clocks.

The equalization equalizes only VCOM AC lines.
VCOM equalization period

EQ2 EQ1 EQ0 RGB interface operation
0 0 0 No EQ (default) No EQ (default) No EQ (default)
TOMATO LSI Inc. 46

Ver .1.0
1H period 1H period
CL
Gn
Gate line non-overlap period(NO)

Gn+1
Sn
VCOM
EQ
(interanl)
Delay amount of the source output(SDT)

Equalizing period(EQ)
Equalizing Period and Delay Amount
TOMATO LSI Inc. 47

Ver .1.0
6-2. Power Control Instruction
(1) Power Control 1 (R10h)
GAP GAP GAP

W 1 0 BT3 BT2 BT1 BT0 0 AP2 AP1 AP0 0 0 SLP STB
2 1 0
GAP [2:0]: Adjust the amount of fixed current from the current source in the operational amplifier for the
Gray scale. When the amount of fixed current is large, LCD driving ability and the display quality become
high, but the current consumption is increased. Adjust the fixed current considering the display quality and
the current consumption.
During non-display, when GAP2-0 = “000”, the current consumption can be reduced by halt the operational
amplifier operation.
GAP2 GAP1 GAP0 Amount of current in operational amplifier

0 0 0 Operation of the operational amplifier halts
0 0 1 Small
0 1 0 Small or medium
0 1 1 Medium
1 0 0 Medium or large
1 0 1 Large
1 1 0 Setting disable
AP [2:0]: Adjust the constant current in the operational amplifier circuit of the LCD power supply circuit.
If constant current flow rate of operation amplifier is set large, display quality is enhanced due to increased
LCD driving capacity, while current consumption is also increased. It is necessary to adjust between display
quality and current consumption.
To reduce current consumption, set AP2-0 = “000” during display Off to halt the operational amplifier
operation.
AP2 AP1 AP0 LCD power op-amp current flow rate

0 0 1 Small
0 1 1 Medium
1 0 1 Large
TOMATO LSI Inc. 48

Ver .1.0
BT [3:0]: Change output scale factor of step-up circuit. Adjust step-up scale factor according to the voltage
to be used. The smaller the step-up scale factor is, the lower the power consumption will be.
BT[3:0] VLO VCL VGH VGL Capacitor connect

-(VREG2x2 + VCI) VLO,VGH,VGL,VCL
4’h0
[x -5] C11,C12,C21,C22,C23,C31
VREG2x3 + VCI -(VREG2x2) VLO,VGH,VGL,VCL
4’h1 [x 7] [x -4] C11,C12,C21,C22,C31
-(VREG2 + VCI) VLO,VGH,VGL,VCL
4’h2
[x -3] C11,C12,C21,C22,C23,C31
4’h3
[x -5] C11,C12,C21,C22,C23,C31
VREG2x3 -(VREG2x2) VLO,VGH,VGL,VCL
4’h4
[x 6] [x -4] C11,C12,C21,C22,C31
VCI x 2 -VCI -(VREG2 + VCI) VLO,VGH,VGL,VCL
4’h5 [x 2] [x -1] [x -3] C11,C12,C21,C22,C23,C31
4’h6
[x -5] C11,C12,C21,C22,C23,C31
VREG2x2 + VCI -(VREG2x2) VLO,VGH,VGL,VCL
4’h7
[x 5] [x -4] C11,C12,C21,C22,C31
-(VREG2 + VCI) VLO,VGH,VGL,VCL
4’h8
[x -3] C11,C12,C21,C22,C23,C31
-(VREG2x2) VLO,VGH,VGL,VCL
4’h9
VREG2x2 [x -4] C11,C12,C21,C22,C31
[x 4] -(VREG2 + VCI) VLO,VGH,VGL,VCL
4’hA
[x -3] C11,C12,C21,C23,C31
4’hB~4’hF Setting disable
Note 1) Scale factor in bracket [ ] is a step-up scale factor from VCI.
Note 2) Capacitor connect pins are a step-up capacitor necessary for using VLO, VCL, VGH, VGL.
Note 3) Set the voltage within the following limit.
VLO = max 6.6V, VCL = max -3.3V. VGH-VGL = max 32V, VGH = max 21.52V, VGL = min -15.44V
Note 4) VREG2 = REGP x 2
SLP: When SLP = 1, TL1763 enters into sleep mode, in which the internal display operations are halted
except for the R-C oscillator, thus reducing current consumption. During sleep mode, any changes in the
GRAM data or instruction set are not executable, but retained.
STB: When STB = 1, TL1763 enters into the standby mode, in which display operation completely stops,
halting all internal operations including the internal R-C oscillator. In addition, no external clock pulses are
supplied. During standby mode, any changes in the GRAM data or instruction set are not executable. Only
the following instructions can be executed during standby mode. For details, see the Standby Mode section.
(1) Release of standby mode (STB = 0)
(2) Oscillation start
TOMATO LSI Inc. 49

Ver .1.0
(2) Power Control 2 (R11h)
DC1 DC1 DC1 DC0 DC0 DC0

W 1 0 0 0 0 0 0 0 VC2 VC1 VC0
2 1 0 2 1 0
DC0 [2:0]: Select the operation frequency of step-up circuit 1. If step-up operation frequency is set high,
display quality is enhanced due to increased driving capacity of step-up circuit, while power consumption is
also increased. It is necessary to adjust between display quality and power consumption.
DC1 [2:0]: Select the operation frequency of step-up circuit 2. If step-up operation frequency is set high,
display quality is enhanced due to increased driving capacity of step-up circuit, while power consumption is
also increased. It is necessary to adjust between display quality and power consumption.
Boosting circuit 1, Boosting circuit 2,

DC0[2:0] DC1[2:0]
Boosting clock frequency (fDCDC1) Boosting clock frequency (fDCDC2)
000 Step-up circuit 1 operation halt 000 Step-up circuit 2 operation halt
001 Fosc/4 001 Fosc/8
010 Fosc/8 010 Fosc/16
011 Fosc/16 011 Fosc/32
100 Fosc/32 100 Fosc/64
101 Fosc/64 101 Fosc/128
110 Setting disable 110 Setting disable
111 Setting disable 111 Setting disable
Note 1) Set fDCDC1 > fDCDC2
VC [2:0]: Reference voltages of VREG1 voltage, REGP voltage are adjusted according to VCIF.
VC[2:0] REGP
000 0.92 x VCIF
001 0.89 x VCIF
010 0.86 x VCIF
011 0.83 x VCIF
100 0.80 x VCIF
101 0.77 x VCIF
110 0.74 x VCIF
111 Setting disable
TOMATO LSI Inc. 50

Ver .1.0
(3) Power Control 3(R12h)
VRH VRH VRH VRH

W 1 0 0 0 COM 0 0 0 0 0 0 0 PON
3 2 1 0
COM: Control output from VCOM. Set COM, VCOMG according to power ON flow.
COM VCOMG VCOM output

0 0 VSS
0 1 VSS
1 0 VCOMH / VSS
1 1 VCOMH / VCOML
PON: Set operation/halt of VGL. Set PON according to power start sequence.
VRH [3:0]: Take in the value set at VC bits (REGP) and set amplification scale of VREG1.
VRH[3:0] VREG1
0000 ~ 0111 Halt (Hi-Z)
1000 REGP x 1.38
1001 REGP x 1.45
1010 REGP x 1.53
1011 REGP x 1.60
1100 REGP x 1.68
1101 REGP x 1.75
1110 REGP x 1.83
1111 REGP x 1.90
Note 1) Set VREG1 voltage to 5.0V or less at VC, VRH bits
(4) Power Control 4(R13h)
VCO VDV VDV VDV VDV VDV VCM VCM VCM VCM VCM VCM
W 1 0 0 0 0
MG 4 3 2 1 0 5 4 3 2 1 0
VCOMG: Set the output level of VCOML.

VCOMG = 0 : The low-side outputs of VCOM is fixed to VSS. The instruction (VDV) setting is invalid.
Outputs from VCOML and VCL are stopped.
VCOMG = 1 : The low-side outputs of VCOM is VCOML respectively.
The output voltage of VCOML is set by instruction (VDV) setting.
VCOMG = 1 is valid when PON = 1.
TOMATO LSI Inc. 51

Ver .1.0
VDV [4:0]: Set the amplitude of VCOM voltage within the range of VRGE1 x 0.54 ~ 1.23.
VDV[4:0] VCOM amplitude VDV[4:0] VCOM amplitude

00000 VREG1 x 0.54 10000 VREG1 x 1.02
00001 VREG1 x 0.57 10001 VREG1 x 1.05
00010 VREG1 x 0.60 10010 VREG1 x 1.08
00011 VREG1 x 0.63 10011 VREG1 x 1.11
00100 VREG1 x 0.66 10100 VREG1 x 1.14
00101 VREG1 x 0.69 10101 VREG1 x 1.17
00110 VREG1 x 0.72 10110 VREG1 x 1.20
00111 VREG1 x 0.75 10111 VREG1 x 1.23
01000 VREG1 x 0.78 11000 Setting disable
Note 1) Set VCOMH voltages to 3.0V ~ (VREG1 – 0.5)V.
VCM [5:0]: Set the settings for the VCOMH voltage when electrical volume is selected.
VRGE1 voltage can be amplified by 0.34 ~ 0.96 times.
When VCM[5:0] = 111111, select the potential setting of VCOMH with VCOMR (external resistances).
VCM[5:0] VCOMH VCM[5:0] VCOMH

000000 VREG1 x 0.34 010000 VREG1 x 0.50
000001 VREG1 x 0.35 010001 VREG1 x 0.51
000010 VREG1 x 0.36 010010 VREG1 x 0.52
000011 VREG1 x 0.37 010011 VREG1 x 0.53
000100 VREG1 x 0.38 010100 VREG1 x 0.54
000101 VREG1 x 0.39 010101 VREG1 x 0.55
000110 VREG1 x 0.40 010110 VREG1 x 0.56
000111 VREG1 x 0.41 010111 VREG1 x 0.57
001000 VREG1 x 0.42 : :
001001 VREG1 x 0.43 : :
001010 VREG1 x 0.44 111010 VREG1 x 0.92
001011 VREG1 x 0.45 111011 VREG1 x 0.93
001100 VREG1 x 0.46 111100 VREG1 x 0.94
001101 VREG1 x 0.47 111101 VREG1 x 0.95
001110 VREG1 x 0.48 111110 VREG1 x 0.96
001111 VREG1 x 0.49 111111 VCOMR
Note 1) Set VCOM max amplitude less 6.0V
Note 2) The aforementioned setting is valid for VCOMH when electrical volume is selected.
TOMATO LSI Inc. 52

Ver .1.0
6-3. RAM access instructions
(1) Horizontal Address Set (R20h)

(2) Vertical Address Set (R21h)
AD AD AD AD AD AD AD AD
W 1 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0
AD AD AD AD AD AD AD AD AD
W 1 0 0 0 0 0 0 0 16 15 14 13 12 11 10 9 8
AD [16:0]: Initialize GRAM address at AC (Address Counter). Consecutive writing is possible without
resetting address by automatic update of AC according to AM and I/D bits after writing GRAM data.
After reading out GRAM data, no automatic update of AC is executed.
[GRAM Address Range]

AD[16:0] GRAM Data setting
“00000”H ~ “000EF”H Bitmap data for G1
: :
: :
“13C00”H ~ “13CEF”H Bitmap data for G317
“13D00”H ~ “13DEF”H Bitmap data for G318
“13E00”H ~ “13EEF”H Bitmap data for G319
“13F00”H ~ “13FEF”H Bitmap data for G320
Note 1) Setting of address at AD bits of each frame is executed at the falling edge of VSYNC when RGB
interface (RM = 1) is selected
Note 2) Setting of address is executed when instructions are executed when internal clock operation or
VSYNC interface is selected.
Note 3) Make sure address setting is executed when accessing RAM after releasing standby.
TOMATO LSI Inc. 53

Ver .1.0
(3) Write Data to RAM (22h)
R/W RS
W 1 RAM write data (WD17-0). The pin assignment for DB17-0 varies for each interface
RGB
RAM write data (WD17-0). The pin assignment for DB17-0 varies for each interface
interface
WD [17:0]: All data are expanded into 18-bits internally before being written to GRAM. Each interface has its
own way of expanding data to 18-bits.
The grayscale level is determined by the GRAM data. The address is automatically updated by the bits of
AM and I/D after GRAM writing. During the standby mode, no access is allowed to GRAM. When the 8 or 16-
bit interface modes are selected, the data in the MSB of R and B pixels are also written to the LSB of R and
B pixels respectively to expand the 8/16-bit data into the 18-bit data internally.
During the RGB interface mode, when writing data to RAM through a system interface, make sure to avoid
conflicts between writing through the RGB interface and writing through system interface.
When the 18-bit RGB interface is in use, 18-bit data is written to RAM through DB17-0 and 262,144 colors
are available. When the 16-bit RGB interface is in use, the MSB is written to its LSB and 65,536 colors are
available.
TOMATO LSI Inc. 54

Ver .1.0
1) MPU 18-bit Interface (262,144 colors), TRI = *, DFM = *

Input pin
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
GRAM data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
2) MPU 16-bit interface

a. One times transfer/pixel (65,536 colors), TRI = 0, DFM = *
Input pin
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
GRAM data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
b. Two times transfer/pixel 1 (262,144 colors), TRI = 1, DFM = 0

2nd
Input pin
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 17 16
GRAM data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
c. Two times transfer/pixel 2 (262,144 colors), TRI = 1, DFM = 1

1st
Input pin
2 1 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
GRAM data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
TOMATO LSI Inc. 55

Ver .1.0
3) MPU 9-bit interface (262,144 colors), TRI = *, DFM = *

st nd
Input pin
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
GRAM data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

a. Two times transmission (65,536 colors), TRI = 0, DFM = *
st nd
Input pin
17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
GRAM data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
b. Three times transmission (262,144 colors), TRI = 1, DFM = 0

st nd rd
Input pin
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
GRAM data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
c. Three times transmission (65,536 colors), TRI = 1, DFM = 1

st nd rd
Input pin
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
GRAM data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
TOMATO LSI Inc. 56

Ver .1.0

a. Three times transmission (262,144 colors), TRI = 0, DFM = *
st nd rd
Input pin
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
GRAM data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
b. Three times transmission (65,536 colors), TRI = 1, DFM = *

st nd rd
Input pin
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
GRAM data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
TOMATO LSI Inc. 57

Ver .1.0
6) RGB18-bit interface (262,144 colors), TRI = *, DFM = *

Input pin
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GRAM data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
7) RGB16-bit interface (65,536 colors), TRI = *, DFM = *

Input pin
17 16 15 14 13 11 10 9 8 7 6 5 4 3 2 1
GRAM data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
8) RGB 6-bit interface (three times transfers) (262,144 colors), TRI = *, DFM = *
st nd rd
Input pin
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
GRAM data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
TOMATO LSI Inc. 58

Ver .1.0
GRAM Data and LCD Output Level (REV = 0)

GRAM data Selected grayscale level GRAM data Selected grayscale level
RGB RGB
Negative Positive Negative Positive
6’h00 V0 V63 6’h20 V32 V31
6’h01 V1 V62 6’h21 V33 V30
6’h02 V2 V61 6’h22 V34 V29
6’h03 V3 V60 6’h23 V35 V28
6’h04 V4 V59 6’h24 V36 V27
6’h05 V5 V58 6’h25 V37 V26
6’h06 V6 V57 6’h26 V38 V25
6’h07 V7 V56 6’h27 V39 V24
6’h08 V8 V55 6’h28 V40 V23
6’h09 V9 V54 6’h29 V41 V22
6’h0A V10 V53 6’h2A V42 V21
6’h0B V11 V52 6’h2B V43 V20
6’h0C V12 V51 6’h2C V44 V19
6’h0D V13 V50 6’h2D V45 V18
6’h0E V14 V49 6’h2E V46 V17
6’h0F V15 V48 6’h2F V47 V16
6’h10 V16 V47 6’h30 V48 V15
6’h11 V17 V46 6’h31 V49 V14
6’h12 V18 V45 6’h32 V50 V13
6’h13 V19 V44 6’h33 V51 V12
6’h14 V20 V43 6’h34 V52 V11
6’h15 V21 V42 6’h35 V53 V10
6’h16 V22 V41 6’h36 V54 V9
6’h17 V23 V40 6’h37 V55 V8
6’h18 V24 V39 6’h38 V56 V7
6’h19 V25 V38 6’h39 V57 V6
6’h1A V26 V37 6’h3A V58 V5
6’h1B V27 V36 6’h3B V59 V4
6’h1C V28 V35 6’h3C V60 V3
6’h1D V29 V34 6’h3D V61 V2
6’h1E V30 V33 6’h3E V62 V1
6’h1F V31 V32 6’h3F V63 V0
TOMATO LSI Inc. 59

Ver .1.0
RAM Access through RGB interface and System interface
All the data for display is written to the RAM in TL1763 when RGB interface is in use. In this method, data,
including that in both the moving picture area and the screen update frame, can only be transmitted through
RGB interface. Data for display that is not in the moving picture area or the screen update frame can be
rewritten through the system interface.
RAM can be accessed through the system interface when RGB interface is in use. When data is written to
RAM during RGB interface mode, the ENABLE bit should be high to stop data writing through RGB interface,
because RAM writing is always performed in synchronization with the DOTCLK input when ENABLE is low.
After this RAM access through the system interface, a waiting time is needed for a write/read bus cycle
before the next RAM access starts through RGB interface.
Updating Updating
Note1)
VSYNC
ENABLE
DOTCLK
PD15 to PD0
Note2)
Index Setting Index Updating data in the area Setting Index

System interface R22
RM=0
address R22 other than moving picture area address
RM=1
R22
Updating of moving Updating of moving

picture area Updating of still picture area picture area
Note 1) An address set is made every falling edge of VSYNC in the RGB interface.
Note 2) An address set and an index set (R22h) must be made before RAM access through the RGB interface.
6/25 00:00 6/25 00:00
Moving picture area Moving picture area
Updating still picture area during displaying a moving picture
TOMATO LSI Inc. 60

Ver .1.0
(4) Read Data from GRAM (R22h)
R/W RS
R 1 RAM read data (RD[17:0]) The pin assignment for DB[17:0] varies for each interface
RD [17:0]: Read 18-bit data from GRAM. The RAM read data (RD[17:0]) are assigned differently to the
DB[17:0] pins according to an interface mode.
When the data is read to the microcomputer, the first-word read immediately after the GRAM address setting
is latched from the GRAM to the internal read-data latch. The data in the data bus (DB17–0) becomes invalid
and the second-word read is valid.
When the 8-/16-bit interface is in use, the GRAM data in the LSB of R and B pixels are not read out.
When RGB interface is in use, this function is not available.
●18-bit interface
GRAM Data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD
Read data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
Output
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
●16-bit interface
Read data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
Output
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
●9-bit interface (two times transfers)

Read data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
Output
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
st nd
TOMATO LSI Inc. 61

Ver .1.0
●8-bit interface (two times / three times transfers)

Read data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
Output
17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
st nd
●6-bit interface (three times transfers)

Read data [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
Output
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
st nd rd
Set the I/D, AM, HSA/HEA

and VSA/VEA bits
Address M Set : Set AD
Dummy read(invalid data)

First word
RAM Æ Read data latch
Read(Address M data)
Second word
Read data latch Æ DB17-0
Address N set : Set AD
Dummy read(invalid data)

First word
GRAM Æ Read data latch
Read(Address N data)
Second word
Read data latch Æ DB17-0
Read data to MPU
GRAM data read sequence
TOMATO LSI Inc. 62

Ver .1.0
6-4. Gamma Control Instruction (1)~(9), (R30h ~ R39h)
PKP PKP PKP PKP PKP PKP

W 1 0 0 0 0 0
12 11 10
0 0 0 0 0
02 01 00

W 1 0 0 0 0 0
32 31 30
0 0 0 0 0
22 21 20

W 1 0 0 0 0 0
52 51 50
0 0 0 0 0
42 41 40
PRP PRP PRP PRP PRP PRP

W 1 0 0 0 0 0
12 11 10
0 0 0 0 0
02 01 00
PKN PKN PKN PKN PKN PKN

W 1 0 0 0 0 0
12 11 10
0 0 0 0 0
02 01 00

W 1 0 0 0 0 0
32 31 30
0 0 0 0 0
22 21 20

W 1 0 0 0 0 0
52 51 50
0 0 0 0 0
42 41 40
PRN PRN PRN PRN PRN PRN

W 1 0 0 0 0 0
12 11 10
0 0 0 0 0
02 01 00
VRP VRP VRP VRP VRP VRP VRP VRP VRP VRP
W 1 0 0 0
14 13 12 11 10
0 0 0
04 03 02 01 00
VRN VRN VRN VRN VRN VRN VRN VRN VRN VRN
W 1 0 0 0
14 13 12 11 10
0 0 0
04 03 02 01 00
PKP5-0 [2:0]: Fine-adjusting register for positive polarity output

PRP1-0 [2:0]: Gradient-adjusting register for positive polarity output
PKN5-0 [2:0]: Fine-adjusting register for negative polarity output
PRN1-0 [2:0]: Gradient-adjusting register for negative polarity output
VRP1 [4:0], VRP0 [4:0]: Adjustment register for amplification adjustment of the positive polarity output
VRN1 [4:0], VRN0 [4:0]: Adjustment register for amplification adjustment of the negative polarity output
TOMATO LSI Inc. 63

Ver .1.0
6-5. Display Panel Control Instructions
(1) Gate Scan Position (R40h)
SCN SCN SCN SCN SCN SCN

W 1 0 0 0 0 0 0 0 0 0 0
5 4 3 2 1 0
SCN [5:0]: Set the scan start point of the gate driver.
Scanning start position

SCN5 SCN4 SCN3 SCN2 SCN1 SCN0
GS = 0 GS = 1
0 0 0 0 0 0 G1 (default) G320
0 0 0 0 0 1 G9 G312
0 0 0 0 1 0 G17 G304
0 0 0 0 1 1 G25 G296
0 0 0 1 0 0 G33 G288
0 0 0 1 0 1 G41 G280
0 0 0 1 1 0 G49 G272
0 0 0 1 1 1 G57 G264
: : : : : : : :
: : : : : : : :
0 1 0 0 0 0 G129 G192
0 1 0 0 0 1 G137 G184
0 1 0 0 1 0 G145 G176
0 1 0 0 1 1 G153 G168
0 1 0 1 0 0 G161 G160
0 1 0 1 0 1 G169 G152
0 1 0 1 1 0 G177 G144
0 1 0 1 1 1 G185 G136
Relation between NL set value and SCN set value.
TOMATO LSI Inc. 64

Ver .1.0
(2) Vertical Scroll Control (R41h)
W 1 0 0 0 0 0 0 0 VL8 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0
VL [8:0]: Specify scroll length at the scroll display for vertical smooth scrolling. Any raster-row from the first
to 320th can be scrolled according to the value of VL8-0. After 320th raster-row is displayed, the display
restarts from the first raster-row. The scroll length (VL8-0) is valid when VLE1 = 1 or VLE2 = 1. The raster-
row display is fixed when VLE2-1 = 00.
VL8 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0 Scroll Length
0 0 0 0 0 0 0 0 0 0 line
0 0 0 0 0 0 0 0 1 1 line
0 0 0 0 0 0 0 1 0 2 line
0 0 0 0 0 0 0 1 1 3 line
: : : : : : : : : :
: : : : : : : : : :
1 0 0 1 1 1 1 0 1 317 line
1 0 0 1 1 1 1 1 0 318 line
1 0 0 1 1 1 1 1 1 319 line
Note : Do not set any higher raster-row then 319(13FH). Also, make sure that SS + VL < 512.
TOMATO LSI Inc. 65

Ver .1.0
(3) 1st Screen Driving Position (R42h/R43h)
W 1 0 0 0 0 0 0 0 SE18 SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10
W 1 0 0 0 0 0 0 0 SS18 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10
SS [18:10]: Specify the driving start position for the first screen in a line unit. The LCD driving starts from the
‘set value+1’ gate driver
SE [18:10]: Specify the driving end position for the first screen in a line. The LCD driving is performed to the
‘set value+1’ gate driver.
For instance, when SS18-10 = 07H and SE18-10 = 10H are set, the LCD driving is performed from G8 to
G17 and non-display driving is performed for G1 to G7, G18 to others.
Ensure that SS18-10 ≤ SE18-10 ≤ 13FH. For details, see the Screen-division Driving Function section.
(4) 2nd Screen Driving Position (R44h/R45h)
W 1 0 0 0 0 0 0 0 SE28 SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20
W 1 0 0 0 0 0 0 0 SS28 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20
SS [28:20]: Specify the driving start position for the second screen in a line unit. The LCD driving starts from
the ‘set value +1’ gate driver. The second screen is driven when SPT = 1.
SE [28:20]: Specify the driving end position for the second screen in a line unit. The LCD driving is
performed to the ‘set value + 1’ gate driver.
For instance, when SPT = 1, SS28-20 = 20H, and SE28-20 = 9FH are set, the LCD driving is performed from
G33 to G160.
Ensure that SS18-10 ≤ SE18-10 < SS28-20 ≤ SE28-20 ≤ 13FH. For details, see the Screen-division Driving
Function section.
TOMATO LSI Inc. 66

Ver .1.0
6-6. Window Addressing Control Instruction
(1) Horizontal RAM Address (End/Start address): R46h

(2) Vertical RAM Address (End address): R47h
(3) Vertical RAM Address (Start address): R48h
HEA HEA HEA HEA HEA HEA HEA HEA HSA HSA HSA HSA HSA HSA HSA HSA
W 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
VEA VEA VEA VEA VEA VEA VEA VEA VEA

W 1 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0
VSA VSA VSA VSA VSA VSA VSA VSA VSA

W 1 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0
HSA [7:0]: Specify the horizontal start position of a window address for access in memory
HEA [7:0]: Specify the horizontal end position of a window address for access in memory. Data can be written
to a rectangular area within GRAM from the address specified by HSA to HEA. Note that an address must be
set before RAM is written to. Ensure 8’h00 ≤ HSA ≤ HEA ≤ 8’hEF.
VSA [8:0]: Specify the vertical start position of a window address for access in memory.
VEA [8:0]: Specify the vertical end position of a window address for access in memory. Data can be written
to a rectangular area within GRAM from the address specified by VSA to VEA. Note that an address must be
set before RAM is written to. Ensure 9’h000 ≤ VSA ≤ VEA ≤ 9’h13F.
[GRAM Address Space]

1 7 'h 0 0 0 _ 0 0
HSA HEA
VSA
Window address setting range

8’h00 ≤ HSA ＜ HEA ≤ 8’hEF
W in d o w 9’h000 ≤ VSA ＜ VEA ≤ 9’h13F
a d d re s s a re a
VEA
G R A M a d d re s s s p a c e
1 7 'h 1 3 F _ E F
Note 1) Set a window address range to be within the GRAM address map.
Note 2) Make an address set within the window address area.
TOMATO LSI Inc. 67

Ver .1.0
6-7. Source Driver Control Instruction
(1) Source Driver Control 1: RA1h

(2) Source Driver Control 2: RA4h
SDV SAP SAP SAP

W 1 0 0 0 0 0 0 0 0 0 0 0 0
ON 2 1 0
SRC SRC SRC SRC PSC PSC PSC PSC

W 1 0 0 0 0 0 0 0 0
3 2 1 0 3 2 1 0
SDVON: Set operation/halt of Source Driver.
SAP [2:0]: Adjust the amount of fixed current from the current source in the operational amplifier for the
source driver. When the amount of fixed current is large, LCD driving ability and the display quality become
high, but the current consumption is increased. Adjust the fixed current considering the display quality and
the current consumption.
During non-display, when BAP2-0 = “000”, the current consumption can be reduced by halt the operational
amplifier operation.
SAP2 SAP1 SAP0 Amount of current in operational amplifier

0 0 1 Small
0 1 1 Medium
1 0 1 Large
SRC [3:0]: Adjust the slew rate of operational-amplifier in source driver. SRC value can be different
according to pannel condition.
PSC [3:0]: This setting makes power consumption reduced. However, the setting value can be different
according to pannel condition. And keep “SRC > PSC” condition.
TOMATO LSI Inc. 68

Ver .1.0
7. RESET FUNCTION
TL1763 is internally initialized by RESETB input. During the reset period, internal settings are initialized.
No instruction or GRAM data access from the MPU is accepted during the reset period. The gate-driver and
the power supply are automatically reinitialized when TL1763 is reset. The reset input must be held for at
least 1 ms. Do not access the GRAM or initially set the instructions until the R-C oscillation frequency is
stable after power has been supplied (10 ms).
Instruction Set Initialization

1. Start power (SVL = “011”, EXT = “0”, OSC = “1”)
2. Driver output control 1 (VSPL = “0”, HSPL = “0”, DPL = “0”, EPL = “0”, SM = “0”, GS = “0”, SS = “0”)
3. LCD driving waveform control (FLD1-0 = “01”, B/C = “0”, EOR = “0”, NW5-0 = “000000”)
4. Entry mode set (TRI = “0”, DFM = “0”, BGR = “0”, I/D1-0 = “11”, AM = “0”)
5. Driver output control 2 (NL8-0 = “101000000”)
6. Display control 1 (PT1-0 = “00”, VLE2-1 = “00”, SPT = “0”, GON = “0”, DTE = “0”, CL = “0”, REV = “0”,
D1-0 = “00”)
7. Display control 2 (FP3-0 = “1000”, BP3-0 = “1000”)
8. Display control 3 (PTG1-0 = “00”, ISC3-0 = “0000”)
9. Frame cycle control (NO2-0 = “000”, SDT2-0 = “000”, DIV1-0 = “00”, RTN3-0 = “0000”)
10. External display interface (RM = “0”, DM1-0 = “00”, RIM1-0 = “00”)
11. Equalize control (VEM = “1”, EQ2-0 = “000”)
12. Power control 1 (GAP2-0 = “000”, BT3-0 = “1010”, AP2-0 = “000”, SLP = “0”, STB = “0”)
13. Power control 2 (DC12-10 = “000”, DC02-00 = “000”, VC2-0 = “000”)
14. Power control 3 (COM = “0”, PON = “0”, VRH3-0 = “0000”)
15. Power control 4 (VCOMG = “0”, VDV4-0 = “00000”, VCM5-0 = “000000”)
16. RAM address set (AD16-0 = “00000”h)
17. Gamma control
( PKP02-00 = “000”, PKP12-10 = “000”, PKP22-20 = “000”, PKP32-30 = “000”,
PKP42-40 = “000”, PKP52-50 = “000”, PRP02-00 = “000”, PRP12-10 = “000”,
PKN02-00 = “000”, PKN12-10 = “000”, PKN22-20 = “000”, PKN32-30 = “000”,
PKN42-40 = “000”, PKN52-50 = “000”, PRN02-00 = “000”, PRN12-10 = “000”,
VRP14-10 = “00000”, VRP04-00 = “00000”, VRN14-10 = “00000”, VRN04-00 = “00000” )
18. Gate scan starting position (SCN5-0 = “000000”)
19. Vertical scroll (VL8-0 = “000000000”)
20. 1st split-screen (SE18-10 = “100111111”, SS18-10 = “000000000”)
21. 2nd split-screen (SE28-20 = “100111111”, SS28-20 = “00000000”)
22. Horizontal RAM address position (HEA7-0 = “11101111”, HSA7-0 = “00000000”)
23. Vertical RAM address position (VEA8-0 = “100111111”, VSA8-0 = “000000000”)
24. Source driver control 1 (SDVON = “0”, SAP2-0 = “000”)
25. Source driver control 2 (SRC3-0 = “1010”, PSC3-0 = “0101”)
GRAM Data Initialization

This is not automatically initialized by reset input but must be initialized by software while display is off
(D1-0 = 00).
Output Pin Initialization

1. LCD driver output pins (Source outputs) : Output VSS level
(Gate outputs) : Output VGL level
2. VCOM : Halt (Output VSS)
3. FLM, M, CL : Halt (Output VSS)
4. Oscillator output pin : Outputs oscillation signal
TOMATO LSI Inc. 69

Ver .1.0
8. INTERFACE SPECIFICATION
The TL1763 incorporates a system interface for making instruction setting and an external display interface
for displaying a moving picture. By selecting an optimum interface according to a displayed picture (moving
or still), it can effectively transmit display data.
The external display interface consists of RGB interface and VSYNC interface, which enables flicker-free
screen update.
The RGB interface executes display operation according to synchronization signals (VSYNC, HSYNC, and
DOTCLK). In synchronization with these signals, data to be displayed are written according to the values of
the data enable signal (ENABLE) and display data (DB17-0). All data to be displayed are stored in RAM,
thereby only necessitates data transmission when there is a switching between the panels. In addition, the
use of window address function enables the rewriting of only RAM area used to display a moving picture,
thereby enables a simultaneous display of moving picture area as well as RAM data written beforehand.
In VSYNC interface mode, a synchronization signal (VSYNC) regulates the synchronization of internal
display operations. By writing data on RAM in a regular speed through system interface on the falling edge of
VSYNC, a moving picture display is possible even with a conventional system interface. In this case, there
may be constraints in the RAM writing speed and methods.
TL1763 has 4 operation modes according to display operations. The setting for each mode can be made
through control instructions for the external display interface. Transitions between modes should follow the
transition flow.
Operation modes and interfaces

Operation mode RAM Access Setting (RM) Display Operation Mode (DM1-0)
Internal operating clock only System interface Internal operating clock
(Displaying still picture) (RM = 0) (DM1-0 = 00)
RGB interface (1) RGB interface RGB interface
(Displaying moving picture) (RM = 1) (DM1-0 = 01)
RGB interface (2)
System interface RGB interface
(Rewriting still picture while
(RM = 0) (DM1-0 = 01)
displaying moving pictures)
VSYNC interface System interface VSYNC interface
(Displaying moving pictures) (RM = 0) (DM1-0 = 10)
Note 1) Instructions are set only through a system interface.
Note 2) RGB interface and VSYNC interface cannot be used at the same time.
Note 3) RGB interface mode (RIM1-0) cannot be set while RGB interface is operating.
Note 4) For mode transitions, see the section on the external display interface.
TOMATO LSI Inc. 70

Ver .1.0
8-1. System Interface
The following interfaces are available as system interface. It is determined by setting bits of IM3-0.
Instructions and RAM accesses can be performed through the system interface.
CSB
System RS
interface E_WRB
RW_RDB
DB17-0
18 / 16 / 9 / 8 / 6
System TL1763
ENABLE
RGB VSYNC
interface HSYNC
DOTCLK
Interface specification
IM3 IM2 IM1 IM0 Interface mode with MPU Using DB pin Available Colors
0 0 0 0 68 system 16-bit interface DB17-10, 8-1 262,144
0 0 0 1 68 system 8-bit interface DB17-10 262,144
0 0 1 0 80 system 16-bit interface DB17-10, 8-1 262,144
0 1 0 ID Serial Peripheral Interface (SPI) SDI, SDO 65,536
0 1 1 * Setting disabled - -
1 1 * 1 Setting disabled - -
Note 1) 262,144 colors in 16-bit data bus 2-transmission mode, 65,536 colors in 16-bit data bus 1-
transmission mode.
Note 2) 262,144 colors in 8-bit data bus 3-transmission mode, 65,536 colors in 8-bit data bus 2-transmission
mode
TOMATO LSI Inc. 71

Ver .1.0
68 / 80-system 18-bit interface
68 / 80-system 18-bit parallel data transfer can be used by setting IM3/2/1/0 pins.
CSN CSB
A1 RS TL1763
MPU HWR E_WRB
(RD*) (RW_RDB)
18
D31-0 DB17-0
Example of Interface with the 18-bit Microcomputer
[Data format for 18-bit interface]

● Instruction
Input pin
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction code
● RAM data write

Input pin
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GRAM write data R5 R4 R3 R2 R1 R5 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B5
1 pixel
TOMATO LSI Inc. 72

Ver .1.0
CSN CSB
A1 RS TL1763
MPU HWR E_WRB
(RD*) (RW_RDB)
16
D31-0 DB17-10,8-1
DB9,0

● Instruction
Input pin
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
Instruction
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction code
● RAM data write

Input pin
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
1 pixel
Data transmission synchronization in 16-bit bus interface mode.
The TL1763 supports the data transmission synchronization function which reset the counter that counts
the number of data transmission of upper 2bits and lower 16bits or upper 16bits and lower 2bits in the 16-bit
data bus interface 2-transmission mode. When a discrepancy occurs in the data transmission of the
upper/lower bits due to effects from noise and so on, the”0000”H instruction is written 4times consecutively to
reset the upper/lower counter so that data transmission restarts with the upper bit transmission. Periodical
execution of synchronization function allows the display system to recover from execution.
RS
RW_RDB
E_WRB
DB17~10 Upper "0000"H "0000"H "0000"H "0000"H Upper Lower Upper

Lower
DB8~1
16-bit data transfer synchronization
Data Transfer Synchronization
TOMATO LSI Inc. 73
Ver .1.0
16-bit instruction is divided into two parts, which are lower and upper, and the upper eight bits are first
transferred. The LSB of the bus is not used. RAM data is also divided into two parts, which are lower and
upper, and the upper nine bits are first transferred. Unused pins (DB8-0) must be fixed to the VCC or VSS
level. Ensure that upper bytes have to be written when writing the index register.
CSN CSB
A1 RS TL1763
MPU HWR E_WRB
(RD*) (RW_RDB)
9
D15-0 DB17-9
DB8-0
● Instruction
st nd
Input pin
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
Instruction
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction code
● RAM data write

st nd
Input pin
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
1 pixel
TOMATO LSI Inc. 74

Ver .1.0
the number of data transmission of upper 9bits and lower 9bits in the 9-bit data bus interface 2-transmission
mode. When a discrepancy occurs in the data transmission of the upper/lower bits due to effects from noise
and so on, the”00”H instruction is written 4times consecutively to reset the upper/lower counter so that data
transmission restarts with the upper bit transmission. Periodical execution of synchronization function allows
the display system to recover from execution.
RS
RW_RDB
E_WRB
Upper
DB17~9 Lower
"00"H "00"H "00"H "00"H Upper Lower Upper

TOMATO LSI Inc. 75

Ver .1.0
16-bit instruction is divided into two parts, which are lower and upper, and the upper eight bits are first
transferred. The LSB of the bus is not used. RAM data is also divided into two parts, which are lower and
upper, and the upper nine bits are first transferred. Data for RAM write is expanded to 18-bit data in this LSI.
Unused pins (DB9-0) must be fixed to the VCC or VSS level. Ensure that upper bytes have to be written
when writing the index register.
CSN CSB
A1 RS TL1763
MPU HWR E_WRB
(RD*) (RW_RDB)
8
D15-0 DB17-10
DB9-0

● Instruction
st nd
Input pin
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
Instruction
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction code
● RAM data write

st nd
Input pin
17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
1 pixel
TOMATO LSI Inc. 76

Ver .1.0
the number of data transmission of upper 8bits and lower 8bits in the 8-bit data bus interface 2-transmission
mode. When a discrepancy occurs in the data transmission of the upper/lower bits due to effects from noise
and so on, the”00”H instruction is written 4times consecutively to reset the upper/lower counter so that data
transmission restarts with the upper bit transmission. Periodical execution of synchronization function allows
the display system to recover from execution.
RS
RW_RDB
E_WRB
Upper
DB17~10 Lower
"00"H "00"H "00"H "00"H Upper Lower Upper

TOMATO LSI Inc. 77

Ver .1.0
16-bit instruction is divided into three parts, which are lower, middle and upper, and the upper six bits are first
transferred. The LSB of the bus is not used. RAM data is also divided into three parts, which are lower,
middle and upper, and the upper six bits are first transferred. Data for RAM write is expanded to 18-bit data
in this LSI. Unused pins (DB11-0) must be fixed to the VCC or VSS level. Ensure that upper bytes have to be
written when writing the index register.
CSN CSB
A1 RS TL1763
MPU HWR E_WRB
(RD*) (RW_RDB)
6
D15-0 DB17-12
DB11-0

● Instruction
st nd rd
Input pin
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
Instruction
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction code
● RAM data write

st nd rd
Input pin
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
1 pixel
TOMATO LSI Inc. 78

Ver .1.0
the number of data transmission of 1st 6bits, 2nd 6bits and 3rd 6bits in the 6-bit data bus interface 3-
transmission mode. When a discrepancy occurs in the data transmission of the upper/lower bits due to
effects from noise and so on, the”00”H instruction is written 4times consecutively to reset the upper/lower
counter so that data transmission restarts with the upper bit transmission. Periodical execution of
synchronization function allows the display system to recover from execution.
RS
RW_RDB
E_WRB
DB17~12 1st,2nd,3rd "00"H "00"H "00"H "00"H 1st 2nd 3rd

TOMATO LSI Inc. 79

Ver .1.0
Serial clock synchronized interface (SPI)
The Serial Peripheral Interface (SPI) is selected by setting the IM3/IM2/IM1 pins to VSS/IOVCC/VSS levels.
The SPI is available through the chip select line (CSB), serial transfer clock line (SCL), serial data input (SDI),
and serial data output (SDO). For the SPI, the IM0/ID pin function uses as ID pin. If the chip is set up for
serial interface, the DB15-2 pins which are not used, must be fixed at IOVCC or VSS.
TL1763 initiates serial data transmission by transmitting the start byte at the falling edge of CSB input. It
ends serial data transmission at the rising edge of CSB input.
TL1763 is selected when the 6-bit chip address in the start byte transmitted from the transmitting device
matches the 6-bit device identification code assigned to TL1763. TL1763, when selected, receives the
subsequent data string. The least significant bit of the identification code can be determined by the ID pin.
The five upper bits must be 01110. Two different chip addresses must be assigned to a single TL1763
because the seventh bit of the start byte is used as a register select bit (RS): that is, when RS = 0, index
register write or status read is executed, When RS = 1, instruction write or RAM data read/write is executed.
The eighth bit of the start byte is to specify read or write (R/W bit). The data is received when the R/W bit is 0,
and is transmitted when the R/W bit is 1.
When writing to RAM through this serial interface, the data is written to the GRAM after two-byte data has
been transmitted. The MSB of RB data is added to its LSB so that data to be written to the RAM will be 18
bits.
After receiving the start byte, TL1763 receives or transmits the subsequent data byte-by-byte. The data is
transmitted with the MSB first. All TL1763 instructions are 16 bits. Two bytes are received with the MSB first
(DB15 to 0), then the instructions are internally executed. Data for RAM write is expanded to 18-bit data in
this LSI.) After the start byte has been received, the first byte is fetched internally as the upper eight bits of
the instruction and the second byte is fetched internally as the lower eight bits of the instruction.
The five bytes of RAM read data after the start byte are invalid. TL1763 starts to read valid RAM data from
the 6th-byte data.
Start byte format

Transmitted bit S 1 2 3 4 5 6 7 8
Device ID code
Start byte format Transmission start RS R/W
0 1 1 1 0 ID
Note) ID bit is selected with the IM0/ID pin.
Function of RS, R/W bit

RS bit R/W bit Function
0 0 Set index register
0 1 Reads status
1 0 Writes instruction or RAM data
1 1 Reads instruction or RAM data
TOMATO LSI Inc. 80

Ver .1.0
[Data format for Serial Peripheral Interface]
● Instruction
st nd
D D D D D D
Input D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
15 14 13 12 11 10
Instruction
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction code
● RAM data write 1, TRI = 0, DFM = *

st nd
D D D D D D
Input D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
15 14 13 12 11 10
1 pixel
● RAM data write 2, TRI = 1, DFM = *

st nd rd
D D D D D D D D D D D D D D D D D D
Input pin
21 20 19 18 17 16 13 12 11 10 9 8 5 4 3 2 1 0
1 pixel
TOMATO LSI Inc. 81

Ver .1.0
RAM data transfer in SPI mode when TRI = 0 and DFM = *
a) Clock synchronization serial transmission (Basic)

Transfer start Transfer end
CSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCL
MSB LSB
SDI "0" "1" "1" "1" "0" ID RS RW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RS RW
Device ID code
Start byte Index register set, instruction set, RAM data write
SDO
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(Output)
Status read, Instruction read, RAM data read
b) Clock synchronization serial transmission (Consecutive data)

CSB
SCL
SDI Start byte Data (1): upper 8 bits Data (1): lower 8 bits Data (2): upper 8 bits Data (2): lower 8 bits
Start End
Data (1) Data (2)
execution time execution time
※The first byte after the start byte is always the upper eight bits
c) RAM data read-out transmission

CSB
SCL
Start byte
SDI RS=1,
R/W=1
SDO Dummy Dummy Dummy Dummy Dummy RAM read: RAM read:
(Output) read 1 read 2 read 3 read 4 read 5 upper 8 bits lower 8 bits
Start End
※ The 5 bytes right after start byte are dummy read, and invalid data are read out to RAM.
The 6th byte after start byte is real data for RAM read.
TOMATO LSI Inc. 82

Ver .1.0
RAM data transfer in SPI mode when TRI = 1 and DFM = *
a) Clock synchronization serial transmission (Basic)
Transfer start Transfer end
CSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SCL
MSB LSB
D D D D D D D D D D D D D D
SDI "0" "1" "1" "1" "0" ID RS RW
23 22 21 20 19 18 17 16 15 14 13 12 11 10
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RS RW
Device ID code
Start byte
MSB LSB
SDO D D D D D D D D D D D D D D
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
23 22 21 20 19 18 17 16 15 14 13 12 11 10
(Output)
b) Clock synchronization serial transmission (Consecutive data)
CSB
SCL
Start byte RAM data(1) RAM data(1) RAM data(1) RAM data(1) RAM data(1) RAM data(1)
SDI 1st transfer 2nd transfer 3rd transfer 1st transfer 2nd transfer 3rd transfer
End
Start
Note: The first byte of RAM data are transferred following RAM data (1) RAM data (2)
the start byte. execution time execution time
c) RAM data read-out transmission
CSB
SCL
Start byte
SDI RS=1
RW=1
SDO Dummy Dummy Dummy Dummy Dummy RAM read RAM read RAM read
read 1 read 2 read 3 read 4 read 5 1st transfer 2nd transfer 3rd transfer
(Output)
Start End
※ The 5 bytes right after start byte are dummy read, and invalid data are read out to RAM.
The 6th byte after start byte is real data for RAM read.
TOMATO LSI Inc. 83

Ver .1.0
Status read / Instruction read when TRI = * and DFM = *
CSB
SCL
S ta rt b y te
SDI RS = 0
R /W = 1
SDO D um m y S ta tu s /In s tru c tio n re a d : S ta tu s /In s tru c tio n re a d :

(O u tp u t) re a d 1 u p p e r 8 b its lo w e r 8 b its
S ta rt End
※ The 1 byte right after start byte is dummy, and invalid data are read out from internal register.
The 2nd byte is real data.
Serial Peripheral Interface: data transfer
TOMATO LSI Inc. 84

Ver .1.0
8-2. VSYNC Interface
The TL1763 incorporates a VSYNC interface, which enables moving picture display with a system interface
and the frame synchronization signal (VSYNC) only. This interface enables the display of moving pictures
with minimum modification to the conventional system.
VSYNC
CSB
LCDC RS TL1763
/ MPU
E_WRB
18
DB17-0
When DM1-0 = 10 and RM = 0, VSYNC interface is available. In this interface the internal display operation
is synchronized with VSYNC. By writing data to RAM through the system interface in a speed that is higher
for more than a fixed speed than the internal display operation speed, it enables moving picture display
through a system interface and flicker-free screen update.
Display operation can be achieved by using the internal clock generated by the internal oscillator and the
VSYNC input. Because all the data for display is written to RAM, only the data to be rewritten is transferred.
This method reduces the amount of data transferred during moving picture display operation.
[Moving picture data transmission in VSYNC interface]
VSYNC
System interface
RAM data write
Display execution
with internal clock
The VSYNC interface requires taking the minimum speed for RAM writing through the system interface and
the frequency of the internal clock into consideration. RAM writing should be performed with higher speed
than the result obtained from the calculation shown below.
Internal clock frequency (fosc) [Hz]

= Frame frequency × (Display raster-row(NL) + Front porch (FP) + Back porch (BP))
× 22 Clock × Fluctuation
Minimum speed for RAM writing [Hz]

> 240 × Display raster-row(NL) / {((Back porch(BP) + Display raster-row(NL) – Margin)
× 22 Clocks) / fosc}
TOMATO LSI Inc. 85

Ver .1.0
When RAM writing does not start immediately after the falling edge of VSYNC, the period from the falling
edge of VSYNC to the start of RAM write must also be considered.
An example of calculations for the internal clock frequency and RAM writing speed when displaying moving
picture in VSYNC interface mode is shown below.
– Display size 240RGB x 320 raster-rows

– Display line number 320 raster-rows (NL = 101000000)
– Back, Front porch 14 lines / 2 lines (BP = 1110, FP = 0010)
– RTN[3:0] bit 22 clocks (RTN = 0000)
– DIV[1:0] bit 1 div (DIV = 00)
– Frame frequency 60Hz
Internal clock frequency (fosc) [Hz]

= 60Hz x (320 + 2 + 14) raster-rows × 22 clocks × 1.1 / 0.9 = 542 [KHz]
When calculating an internal clock frequency, requires a consideration for the fluctuation. In the above case
+- 10% fluctuation from the center value, and the range of the frequency must be within the VSYNC cycle.
The fluctuation includes LSI production variation and air temperature fluctuation. Other fluctuations, including
those for the external resistors and the supplied power, are not included in this example. Please keep in
mind that a margin for these factors is also needed.
Minimum RAM writing speed [Hz]

> 240 x 320 / {((14 + 320 - 2) raster-rows × 16 clocks) / 542 KHz} = 5.7 [MHz]
In this case RAM writing starts immediately after the falling edge of VSYNC.
The margin for display raster-row should be two raster-rows or more at the completion of RAM writing for one
frame.
Therefore, when RAM writing starting immediately after the falling edge of VSYNC is performed at 5.7 MHz
or more, the data for display can be rewritten before display operation starts. This means that flicker-free
display operation is achieved.
VSYNC Line
RC oscillator
10%
Back Porch(14 line) 320 RAM write RAM write RAM write
RAM write
10MHz 7MHz 5.7MHz

FP = 2H
Dispaly Operation
Display Operation
Executed
Moving Picture Display(320 line) line
Front Porch(2 line)

[ms]
Blank period 7.68 10.13 13.56 16.67
BP = 14H 60Hz
VSYNC
TOMATO LSI Inc. 86

Ver .1.0
Moving picture in VSYNC interface mode

Set window address to display moving picture in VSYNC interface mode.
Line
RC oscillator
10%
Back Porch(14 line) 320
RAM write
300 FP = 2H
21
RAM write
Dispaly Operation
5.7MHz
Display Operation
Moving Picture Display(280 line)
301
20
Front Porch(2 line)
[ms]
Blank period 11.79 13.56 16.67
BP = 14H 60Hz
VSYNC
Display in VSYNC interface mode
Condition on using VSYNC interface

1. The example above of calculation is just a result of calculation. In actual settings, causes for the
fluctuation such as internal oscillator and so on should be taken into consideration. It is necessary to
make a setting for RAM write speed with enough margins.
2. The example above is a calculated value of rewriting the whole screen. A limitation of the moving
picture area generates a margin for the RAM write speed.
3. A front porch period continues after the completion of 1 frame display and until the next input of
VSYNC
4. The transition between the internal clock operation mode (DM1-0 = 00) and the VSYNC interface
mode becomes valid after displaying one frame made during instruction setting.
5. Partial display, vertical scroll functions are not available on VSYNC interface mode.
6. The VSYNC interface is performed by the above method, therefore, AM bit should be 0.
TOMATO LSI Inc. 87

Ver .1.0
Internal clock opration -> VSYNC interface ->

VSYNC interface change flow Internal clock operation change flow
Internal clock operation VSYNC interface operation

Display operation in
synchronization with
AM = 0 VSYNC
Internal clock mode setting
(DM1-0=00, RM = 0) The value set in DM1-0
Display operation in and RM will be valid after
Address Setting 1-frame display
synchronization with the
internal clock
Wait more than 1 frame
VSYNC interface mode setting
(DM1-0 = 10, RM = 0) Display operation in
internal clock
Index resister setting The value set in DM1-0 and RM will Internal clock operation
(R22h) be valid after 1-frame display
Note) When swithcing to internal clock mode, please keep supplying
VSYNC signal for more than 1 frame
VSYNC Interface
Writing RAM data
synchronization with VSYNC
VSYNC interface operation
Internal clock mode setting

(DM1-0=00, RM= 0)
Internal clock operation
Note) VSYNC signal must be supplied before setting

DM1-0,RM when swithcing to the VSYNC interface
Transition between the Internal Clock Operation Mode and VSYNC Interface Mode
TOMATO LSI Inc. 88

Ver .1.0
8-3. External Display Interface (RGB interface)
The following interfaces are available as external display interface. It is determined by setting bits of RIM1-0.
RAM accesses can be performed through the RGB interface.
RIM1 RIM0 External Interface DB Pin
0 0 18-bit interface DB17-0
0 1 16-bit interface DB17-13,11-1
1 0 6-bit interface DB17-12
1 1 Setting disabled -
Note 1) It is not possible to use multiple interfaces at the same time.
The RGB interface is performed in synchronization with VSYNC, HSYNC and DOTCLK.
The window address enables transmission only the screen to be updated and reduce the power consumption.
VSYNC ENABLE(V)
Back porch
period(BP3-0)
First display area

(NL)
Moving picture
display area
Front porch
period(FP3-0)
HSYNC
DOTCLK
ENABLE(H)
DB17-0
VSYNC: Frame synchronization signal Back porch period (BP): 14 >= BP >= 2
HSYNC: Raster-row synchronization signal Front porch period (FP): 14 >= FP >= 2
DOTCLK: DOT clock FP + BP = 16
ENABLE: Data enable signal
DB17-0: RGB(6:6:6) display data Display period : NL =< 320
The line number of 1 frame : FP + NL + BP
Note: When using RGB interface, display area for moving picture must be smaller than display area for RAM data.
In RGB interface mode, each synchronizing signal (VSYNC, HSYNC and DOTCLK) must be supplied for
more than the duration for panel display. Even while displaying a moving picture on, it is possible to
continuously data on the internal RAM by setting ENABLE = Low period.
The polarity of VSYNC, HSYNC, ENABLE, DOTCLK signals can be changeable by instruction settings
(VSPL, HSPL, EPL and DPL). Change them appropriately to a system.
TOMATO LSI Inc. 89

Ver .1.0
8-4. RGB Interface Timing
■16 /18 bits RGB interface

Each signal timing relationship is like as below in RGB interface using.
1Frame
Back porch period Front porch period
VSYNC VLW >= 1H
HSYNC
DOTCLK
ENABLE
DB17-0
1H
HLW>=1CLK
HSYNC
1CLK
DOTCLK
DTST >= SDT + HLW + 3CLK

ENABLE
DB17-0
Valid data
VLW VSYNC “Low” Period

HLW HSYNC “Low” Period
DTST Data Transfer Start Time
TOMATO LSI Inc. 90

Ver .1.0
6bits RGB interface

Each signal timing relationship for RGB interface using is as follows
1 Frame
Back porch period Front porch period
VSYNC
HSYNC
DOTCLK
ENABLE
DB17-0
VLW >= 1H
VSYNC
1H
HSYNC HLW>=1CLK
1CLK
DOTCLK
DTST >= SDT + HLW + 3CLK
ENABLE
R G B R G B R G B R G B R G B R G B R G B R G B
DB17-0
Valid data
VLW VSYNC “Low” Period

HLW HSYNC “Low” Period
DTST Data Transfer Start Time
Each signal timing relationship for RGB interface using is as follows

Note 1) VSYNC, HSYNC, ENABLE, DOTCLK and DB17-0 should be transmitted in units of three clocks.
TOMATO LSI Inc. 91

Ver .1.0
Accessing RAM through system interface in RGB interface mode
While RGB interface is in use, RAM is also accessible through a system interface. In RGB interface mode,
RAM writing continues in response to DOTCLK input during ENABLE = Low. For this reason, display data
writing through RGB interface must be intermitted by setting ENABLE = High, when writing data on RAM
through the system interface. By setting RM to 0, RAM is accessible through the system interface.
When reverting to RGB interface mode, make sure to wait for a write/read base cycle before setting RM to 1.
Then, start accessing RAM through RGB interface after setting RM = 1 to make index settings R22h state. In
case of conflicting RAM access through RGB and system interfaces, data written on RAM will not be
guaranteed.
The following is an example of making changes in data displayed in still picture area through the system
interface while moving picture is displayed through RGB interface mode.
Updating Updating
VSYNC
ENABLE
DOTCLK
DB17-0
Note3) Note3)
System Index
RM=0
Setting of Index Updating of area other Setting of
RM=1
Index
interface R22 address R22 than moving picture area address R22
Updating Updating
Updating
of moving picture area of moving picture area
of still picture area
Note 1) Address set is made every falling edge of VSYNC in RGB interface mode.
Note 2) Address set and index set (R22h) should be made before RAM access starts in RGB interface mode.
Note 3) Transfer from RGB interface to system interface mode must be executed after waiting at least 1 write
cycle (tcycw).
6/25 00:00 6/25 00:00
Moving picture area Moving picture area
Display data updating in still picture area during moving picture display
TOMATO LSI Inc. 92

Ver .1.0
6-bit RGB Interface
6-bit RGB interface can be used by setting RIM1-0 pins to 10. Display operation is synchronized with VSYNC,
HSYNC and DOTCLK signals. Data for display is transmitted to the RAM through 6-bit RGB interface (DB17-
12) and the data enable signal (ENABLE). Unused pins (DB11 to 0) must be fixed to the VCC or VSS level.
Instructions should be set through the system interface.
VSYN C
HSYN C
DOTC LK
LCDC ENABLE TL1763
/MPU
DB17-12
6
DB11-0
12
6-bit RGB interface example
[ 6-bit Interface data format ]

st nd rd
Input
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12

1 pixel
262,144 colors with 6-bit interface
The TL1763 incorporates a transmission counter to count the first, second and third data transmission in the
6-bit RGB interface mode. The transmission counter is always reset to the first transmission of first, second
and third data, the counter is reset to the first data transmission at the start of each frame (the falling edge of
VSYNC) and the data transmissions restarts in the correct order from the next frame. In case of displaying
moving pictures, which requires consecutive data transfer, this function minimizes the effect from the
discrepancy in the data transmission and facilitates to return to the normal display.
VSYNC
ENABLE
DOTCLK
DB17~12
2nd 1st 2nd 3rd 1st 2nd 3rd
transfer transfer transfer transfer transfer transfer transfer
Transfer synchronization
6-bit Transfer Synchronization
TOMATO LSI Inc. 93

Ver .1.0
16-bit RGB Interface
16-bit RGB interface can be used by setting RIM1-0 pins to 01. Display operation is synchronized with
VSYNC, HSYNC and DOTCLK signals. Data for display is transmitted to the RAM in synchronization with
display operation through 16-bit RGB data bus (DB17-13 and 11-1) and data enable signal (ENABLE).
Instructions should be set through the system interface.
VSYNC
HSYNC
DOTCLK
LCDC
TL1763
/MPU
ENABLE
DB17-13,11-1
16
DB12,0
2
16-bit RGB Interface Example
[ Data format for 16-bit Interface]

Input
17 16 15 14 13 11 10 9 8 7 6 5 4 3 2 1

1 pixel
65,536 colors with 16-bit interface
TOMATO LSI Inc. 94

Ver .1.0
18-bit RGB Interface
18-bit RGB interface can be used by setting RIM1-0 pins to 10. Display operation is synchronized with
VSYNC, HSYNC and DOTCLK signals. Data for display is transmitted to the RAM in synchronization with
display operation through 18-bit RGB data bus (DB17-0) and data enable signal (ENABLE). Instructions
should be set through the system interface.
VSYNC
HSYNC
DOTCLK
LCDC
TL1763
/MPU
ENABLE
DB17-0
18
18-bit RGB Interface Example
[ Data format for 18-bit Interface ]

Input
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 pixel
262,144 colors with 18-bit RGB interface
TOMATO LSI Inc. 95

Ver .1.0
Note to the External Display Interface
1. When external display interface is in use, the following functions are not available.
Function External Display Interface Internal Display Operation
Partial display Not available Available
Scroll function Not available Available
Interlace operation Not available Available
2. VSYNC, HSYNC and DOTCLK signals should be supplied during display operation through RGB
interface.
3. Please make sure that when setting bits of NO1-0, SDT1-0, and EQ1-0 in RGB interface, the clock
on which operations are based changes from the internal operating clock to DOTCLK.
4. RGB data is transmitted for three clock cycles in 6-bit RGB interface.
5. Interface signals, VSYNC, HSYNC, DOTCLK, ENABLE and DB17-0 should be set in units of RGB
(pixels) to match RGB transmission.
6. Transitions between internal operation mode and external display interface should follow the mode
transition sequence shown below.
7. During the period between the completion of displaying one frame data and the next VSYNC signal,
the display will remain front porch period.
8. An address set is done on the falling edge of VSYNC every frame in RGB interface.
[Internal clock operation -> [RGB interface(1) ->

RGB interface(1) change flow] Internal clock operation change flow]
Internal clock operation RGB I/F operation
AM = 0 Internal clock mode setting VSYNC,HSYNC,DOTCLK
(DM1-0 = 00, RM = 0)
The value set in DM1-0
and RM will be valid after
Display operation in 1-frame display
Address Setting synchronization with the
internal clock Wait more than 1 frame
RGB I/F Setting synchronization with
The value set in DM1-0
(DM1-0 = 01, RM = 1) the internal clock
and RM will be valid after
1-frame display Internal clock operation
Index resister setting

Note) When switching to internal clock operation, please input the
(R22h) VSYNC, HSYNC, DOTCLK and ENABLE for at least 1-frame
RGB I/F
Writing RAM Data VSYNC,HSYNC,DOTCLK
RGB interface operation

Note) When the interface mode is switched, VSYNC, HSYNC, DOTCLK
and ENABLE should be input before setting of DM1-0 and RM
Transition between the Internal Operating Clock Mode and RGB Interface Mode.
TOMATO LSI Inc. 96

Ver .1.0
8-5. Timing of LCD Panel Interface
18-bit RGB interface
Back Porch
VAW 1H
VSYNC
HSYNC
DOTCLK
ENABLE
FLM
G1
G2
1H NO NO
EQ
VCOM
S1~S720 1 2 3 4 5 6 7
HAW 1CLK
HSYNC
DOTCLK
1CLK
240 CLK
ENABLE DTST SDT + HAW + 3CLK (18-bit interface mode)
DB[17:0] RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB
Valid data write for first line
Display Data write timing during the RGB interface
TOMATO LSI Inc. 97

Ver .1.0
6-bit RGB interface
Back Porch
VAW 1H
VSYNC
HSYNC
DOTCLK
ENABLE
FLM
G1
G2
1H NO NO
EQ
VCOM
S1~S864 1 2 3 4 5 6 7
HAW 1CLK
HSYNC
DOTCLK
1CLK
240 x 3 CLK
ENABLE DTST SDT + HAW + 3CLK (6-bit interface mode)
DB[17:12] B R G B R G B R G B R G B R B R G B
Valid data write for first line
Display Data write timing during the RGB interface
TOMATO LSI Inc. 98

Ver .1.0
8-6. Window Address Function
When data is written to the on-chip GRAM, a window address-range which is specified by the horizontal
address register (start : HSA7-0, end : HEA7-0) or the vertical address register (start : VSA8-0, end : VEA8-
0) can be written to consecutively.
Data are written to addresses in the direction specified by the AM bit (increment/decrement). When image
data, etc. is being written, data can be written consecutively without constraints from data wrap positions in
doing this.
The window must be specified to be within the GRAM address area described below. Addresses must be set
within the window address.
[Restriction on window address-range settings]

(Horizontal direction) 8’h00 ≤ HSA ≤ HEA ≤ 8’hEF
(Vertical direction) 9’h000 ≤ VSA ≤ VEA ≤ 9’h13F
[Restriction on address settings during the window address]

(RAM address) HSA ≤ AD[7:0] ≤ HEA
VSA ≤ AD[16:8] ≤ VEA
GRAM address map

17'h000-00 17'h000-EF
17'h020-10 17'h020-2F
17'h021-10 17'h021-2F
Window address area
17'h05F-10 17'h05F-2F
17'h13F-00 17'h13F-EF
Example of Address Operation in the Window Address Specification
TOMATO LSI Inc. 99

Ver .1.0
Window Address Setting
I/D SS = 0 SS = 1
HSA = 8'h0A(d10) HSA = 8'h0A(d10)
HEA = 8'h28(d40) HEA = 8'h28(d40)
VSA = 9'h1E(d30) VSA = 9'h1E(d30)
VEA = 9'h46(d70) VEA = 9'h46(d70)
AD[16:0] = 17'h46 - 28 AD[16:0] = 17'h46 - 28
HSA HEA HSA HEA
G1 G1
G2 G2
VSA VSA
G3 G3
. .
Decrement
Decrement
Window . Window .
Area . Area .
. .
. .
Decrement Decrement
VEA . VEA .
AD . AD .
2’b00 . .
LCD Panel .
.
LCD Panel .
.
. .
. .
. .
. .
. .
. .
. .
. .
G318 G318
G319 G319
G320 G320
S1,S2,S3 ........ S718,S719,S720 S720,S719,S718 ........ S3,S2,S1

TL1763 TL1763
(Bump view) (Non-Bump view)
HSA = 8'h0A(d10) HSA = 8'h0A(d10)

HEA = 8'h28(d40) HEA = 8'h28(d40)
VSA = 9'h1E(d30) VSA = 9'h1E(d30)
VEA = 9'h46(d70) VEA = 9'h46(d70)
AD[16:0] = 17'h46 - 0A AD[16:0] = 17'h46 - 0A
HSA HEA HSA HEA
G1 G1
G2 G2
VSA VSA
G3 G3
.
Decrement
.
Decrement
Window . Window .
Area . Area .
. .
. .
VEA Increment Increment
. VEA .
AD . AD .
. .
LCD Panel .
. LCD Panel .
.
. .
. .
. .
. .
. .
. .
. .
. .
G318 G318
G319 G319
G320 G320
S1,S2,S3 ........ S718,S719,S720 S720,S719,S718 ........ S3,S2,S1
TL1763 TL1763
TOMATO LSI Inc. 100

Ver .1.0
I/D SS = 0 SS = 1
HSA = 8'h0A(d10) HSA = 8'h0A(d10)
HEA = 8'h28(d40) HEA = 8'h28(d40)
VSA = 9'h1E(d30) VSA = 9'h1E(d30)
VEA = 9'h46(d70) VEA = 9'h46(d70)
AD[16:0] = 17'h1E - 28 AD[16:0] = 17'h1E - 28
HSA HEA HSA HEA

G1 G1
VSA Decrement AD
G2 Decrement AD G2
G3 VSA G3
. .
Increment
Increment
Window . .
Window
Area . .
Area
. .
. .
VEA . VEA .
. .
2’b10 . .
LCD Panel .
. LCD Panel .
.
. .
. .
. .
. .
. .
. .
. .
. .
G318 G318
G319 G319
G320 G320
S1,S2,S3 ........ S718,S719,S720 S720,S719,S718 ........ S3,S2,S1

TL1763 TL1763
HSA = 8'h0A(d10) HSA = 8'h0A(d10)

HEA = 8'h28(d40) HEA = 8'h28(d40)
VSA = 9'h1E(d30) VSA = 9'h1E(d30)
VEA = 9'h46(d70) VEA = 9'h46(d70)
AD[16:0] = 17'h1E - 0A
AD[16:0] = 17'h1E - 0A
HSA HEA HSA HEA

G1 G1
Increment G2 Increment G2
VSA G3 VSA G3
AD AD
. .
Increment
Increment
Window . Window .
Area . Area .
. .
. .
VEA . VEA .
. .
2’b11 . .
LCD Panel .
. LCD Panel .
.
. .
. .
. .
. .
. .
. .
. .
. .
G318 G318
G319 G319
G320 G320
S1,S2,S3 ........ S718,S719,S720 S720,S719,S718 ........ S3,S2,S1

TL1763 TL1763
TOMATO LSI Inc. 101

Ver .1.0
8-7. Scan Mode Setting
The TL1763 allows for changing the shift direction of gate signal output in the following 2 different ways with
GS bits. This allow various connections between the TL1763 and LCD panel.
Scan direction
Left/Right Interchange Forward scan Left/Right Interchange Reverse scan
GS = 0 GS = 1
1 320
2 319
3 318
4 317
GS = 0 GS = 1
320 320
317 4
318 3
240 319 240 2
320 1
TL1763 TL1763
(Non-Bump view) (Non-Bump view)
Scan order Scan order

G1->G2->G3->G4->...->G318->G319->G320 G320->G319->G318->G317->...->G3->G2->G1
Scan mode with GS
TOMATO LSI Inc. 102

Ver .1.0
8-8. N-raster-row Reversed AC Drive
The TL1763 supports not only the LCD reversed AC drive in a one-frame unit, but also the n-raster-row
reversed AC drive which alternates in an n-raster-row unit from one to 256 raster-rows. When a problem
affecting display quality occurs, the n-raster-row reversed AC drive can improve the quality.
Determine the number of the raster-rows n (NW bit set value + 1) for alternating after confirmation of the
display quality with the actual LCD panel. However, if the number of AC raster-row is reduced, the LCD
alternating frequency becomes high. So, the charge or discharge current is increased in the LCD cells.
1 Frame 1 Frame
Back Front Back Front

porch porch porch porch
1 2 3 4 321 322 336 1 2 3 4 321 322 336
Frame AC driving
320 raster-row driving
N-raster-row driving
320 raster-row driving
3 raster-row reversed
EOR = 1
Note 1) In an n-raster row driving, EOR should be “1” so that DC bias voltage is not applied.
Example of an AC signal under n-raster-row reversed AC drive
TOMATO LSI Inc. 103

Ver .1.0
8-9. Interlace Drive
The TL1763 supports the interlace drive to protect from the display flicker. It splits one frame into n fields and
drives. Determine the n fields (FLD bit setting value) after confirming on the actual LCD display.
Following table indicates n fields: the gate selecting position when it is 1 or 3. And the diagram below
indicates the output waveform when the field interlace driver is active.
GS = "0" GS = "1"
FLD1-0 : Setting Value 01 11 FLD1-0 : Setting Value 01 11
Field Field
Gate
- (1) (2) (3)
Gate
- (1) (2) (3)
G1 O O G320 O O
G2 O O G319 O O
G3 O O G318 O O
G4 O O G317 O O
G5 O O G316 O O
G6 O O G315 O O
G7 O O G314 O O
G8 O O G313 O O
G9 O O G312 O O
. .
. .
. .
G317 O O G4 O O
G318 O O G3 O O
G319 O O G2 O O
G320 O O G1 O O
TOMATO LSI Inc. 104

Ver .1.0
1 F ra m e
B la n k
P e rio d
F ie ld (1 ) F ie ld (2 ) F ie ld (3 ) F ie ld (1 )
A C P o la rity
G0
G1
G2
G3
G4
G5
G 3n+1
G 3n+2
G 3n+3
Gate output timing on the 3 field interlace
TOMATO LSI Inc. 105

Ver .1.0
Timing of Changing Polarity
Following diagram indicates the timing of changing polarity on the each AC drive method. LCD drive
polarity is changed after every frame. After the AC this timing, the blank (all outputs from the gate : VGL
output) in 8H period is inserted. Also, LCD drive polarity is change after every field when it is on the
interlace drive and a blank is inserted in every timing. When the reversed n-raster-row is driving, a blank
period is inserted after all screens are drawn. Front and Back porch can be adjusted using FP3-0 and
BP3-0 bits (R08h).
Normal drive (Frame inversion) 3 Field interlace drive N-raster-row reversed AC drive
Back porch (BP) Back porch

AC
n-raster-row
Field 1 AC
n-raster-row
AC
n-raster-row
AC Blank period 1 AC
n-raster-row
1 Frame period
1 Frame period
1 Frame period
AC
n-raster-row
Frame 1 AC
Field 2 n-raster-row
AC
n-raster-row
AC
AC Blank period 2 n-raster-row
AC
n-raster-row
AC
n-raster-row
Field 3 AC
n-raster-row
AC
Front porch (FP)
AC Front porch
Blank period 3
Blank period Blank period Blank period = Back porch

= Back porch (BP) = Blank period 1 + Front porch
+ Front porch (FP) + Blank period 2
= 16H + Blank period 3
= 16H
Timing of changing polarity
TOMATO LSI Inc. 106

Ver .1.0
8-10. Frame Frequency Adjustment Function
The TL1763 has an on-chip frame-frequency adjustment function. The frame frequency can be adjusted by
the instruction setting (DIV, RTN) during the LCD driver as the oscillation frequency is always same.
If the oscillation frequency is set to high, animation or a static image can be displayed in suitable ways by
changing the frame frequency. When a static image is displayed, the frame frequency can be set low and the
low-power consumption mode can be entered. When high-speed screen switching for an animated display,
etc. is required, the frame frequency can be set high.
Relation between LCD Drive Duty and Frame Frequency
The relationship between the LCD driver duty and the frame frequency is calculated by the following
expression. The frame frequency can be adjusted in the 1H period adjusting bit (RTN) and in the operation
clock division bit (DIV) by the instruction.
Formula for the frame frequency

fOSC
Frame frequency = [Hz]
Number of clock per line x Division ratio x (Line + B)
fOSC : R-C oscillation frequency

Number of clock per line : RTN bit
Division ratio : DIV bit
Line : Number of drive raster-row (NL bit)
B : Blank period (Back porch + Front porch)
Example Calculation In case of maximum frame frequency = 60 Hz
Number of drive raster-rows : 320

1-H period : 22 clock cycles (RTN3-0 = 4’b0000)
Operation clock division ratio : 1 division
fosc = 60Hz × 22 clock × 1 division × (320+2+14) lines = 443 [KHz]
In this case, the R-C oscillation frequency becomes 443 KHz. The external resistance value of the R-C
oscillator must be adjusted to be 443 KHz.
TOMATO LSI Inc. 107

Ver .1.0
8-11. Screen-division Driving Function
The TL1763 can select and drive two screens at any position with the screen-driving position registers
(R42h/R43h and R44h/R45h). Any two screens required for display are selectively driven and reducing LCD-
driving voltage and power consumption.
For the 1st division screen, the start line (SS18 to 10) and the end line (SE18 to 10) are specified by the 1st
screen-driving position register (R42h/R43h). For the 2nd division screen, the start line (SS28 to 20) and the
end line (SE28 to 20) are specified by the 2nd screen-driving position register (R44h/R45h). The 2nd screen
control is effective when the SPT bit is “1”. The total count of selection-driving lines for the 1st and 2nd screen
must correspond to the LCD-driving duty set value.
Display Example in 2-screen Division Driving
Number of driving line : NL8-0 = 101000000 (320 line)

1st display setting : SS18-10 = ”00”H, SE18-10 = ”06”H
2nd display setting : SS28-20 = ”12”H, SE18-20 = ”1D”H, SPT = ”1”
TOMATO LSI Inc. 108

Ver .1.0
Restrictions on the 1st/2nd Screen Driving Position Register Settings
The following restrictions must be satisfied when setting the start line (SS18 to 10) and end line (SE18 to 10)
of the 1st screen driving position register (R42h/R43h), and the start line (SS28 to 20) and end line (SE28 to
20) of the 2nd screen driving position register (R44h/R45h) for the TL1763. Note that incorrect display may
occur if the restrictions are not satisfied.
Restrictions on the 1st/2nd Screen Driving Position Register Settings
1st Screen Driving (SPT = 0)

Register setting Display Operation
Full screen display
( SE18 to 10 ) - ( SS18 to 10 ) = NL
Normally it displays (SE18 to 10) to (SS18 to 10)
Partial display
Normally it displays (SE18 to 10) to (SS18 to 10)
( SE18 to 10 ) < NL
In all other display area refers to the output level based
on the PT setting. (non-display )
( SE18 to 10 ) - ( SS18 to 10 ) > NL Setting disabled
Note 1) SS18 to 10 ≤ SE18 to 10 ≤ 13Fh
Note 2) Setting SE28 to 20 and SS28 to 20 are invalid.
2nd Screen Driving (SPT = 1)

Register Setting Display Operation
((SE18 to 10) - (SS18 to 10)) Full Screen display
+ ((SE28 to 20) - (SS28 to 20)) = NL Normally it displays (SE28 to 20) to (SS18 to 10)
Partial display
((SE18 to 10) - (SS18 to 10)) Normally it displays (SE28 to 20) to (SS18 to 10)
+ ((SE28 to 20) - (SS28 to 20)) < NL In all other display area refers to the output level based
on the PT setting. (non-display )
((SE18to 10) - (SS18 to 10))
Setting disabled
+ ((SE28 to 20) - (SS28 to 20)) > NL
Note 1) SS18 to 10 ≤ SE18 to 10 < SS28 to 20 ≤ SE28 to 20 ≤ 13Fh
Note 2) (SE28 to 20) – (SS18 to 10) ≤ NL
The driver output level can be set for non-display area during the partial display. Determine based on
characteristic of the display panels.
Setting non-display area level during the partial display mode

Source output for VCOM output for
non-display area non-display area Gate output for
PT1 PT0
Positive Negative Positive Negative non-display area
polarity polarity polarity polarity
1 0 VSS VSS VSS VSS PTG setting
1 1 Hi-Z Hi-Z VSS VSS PTG setting
TOMATO LSI Inc. 109

Ver .1.0
Refer to the following flow to set up the partial display.
Full Screen Dispaly
PT1-0 = 00
Set SS/SE bits Screen division drive

Set up flow
Wait ( more then 2 Frames )
Set
PT1-0 = 01 if necessary
or PT1-0 = 10
or PT1-0 = 11
Partial Display ON
Full Screen drive

Set SS/SE bits Set up flow
Full Screen Dispaly
Partial Display Setting Flow
TOMATO LSI Inc. 110

Ver .1.0
8-12. Oscillation Circuit
The TL1763 can oscillate between the OSC1 and OSC2 pins using an internal R-C oscillator with an external
oscillation resistor. Note that in R-C oscillation, the oscillation frequency is changed according to the external
resistance value, wiring length, or operating power-supply voltage. If Rf is increased or power supply voltage
is decrease, the oscillation frequency decreases. For the relationship between Rf resistor value and
oscillation frequency, see the Electric Characteristics Notes section
OSC1
The Rf resistance must be located near the
Rf OSC1/OSC2 pin on the master side.
OSC2
TL1763
OSC1
Make sure not to arrange OSC1 and OSC2 close
to each other, nor to arrange other wiring beneath
OSC1/OSC2 wiring to avoid the effects from
coupling.
OSC2
TL1763
External oscillation resistor mode
TOMATO LSI Inc. 111

Ver .1.0
9. GAMMA ADJUSTMENT FUNCTION

Gamma Correction Function
TL1763 incorporates a Gamma -correction function to simultaneously display 262,144 colors. The Gamma -
correction operation specifies eight levels of grayscale with gradient-adjustment and fine-adjustment
registers. Select the polarity of these registers to match the LCD panel used. These registers are available
for both polarities.
GRAM
M SB ------------------------------------------------------------------------------------------------------------------------------- LSB
Display data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Positive polarity Negative polarity V0

register register
6 6 6
V1
PKP0[2:0] PKN0[2:0]
PKP1[2:0] PKN1[2:0]
PKP2[2:0] PKN2[2:0] Gray 64 grayscale 64 grayscale 64 grayscale
8 64
PKP3[2:0] PKN3[2:0] scale control control control
PKP4[2:0] PKN4[2:0] AM P <R> <G> <B>
PKP5[2:0] PKN5[2:0]
PRP0[2:0] PRN0[2:0] V63
PRP1[2:0] PRN1[2:0]
LCD driver LCD driver LCD driver
VRP0[4:0] VRN0[4:0]
VRP1[4:0] VRN1[4:0]
R G B
LCD
TOMATO LSI Inc. 112

Ver .1.0
Configuration of grayscale Amplifier
Eight levels (VIN0-7) are specified by the gradient-adjustment and fine-adjustment registers.
Each level specified by the registers is divided into more detailed levels, generating 64 levels (V0-63).
G radient adjustm ent Am plitude adjustment

Fine adjustm ent register (6 x 3bit)
register register
PR P/N 0 PR P/N 1 PKP/N 0 PKP/N 1 PKP/N 2 PKP/N 3 PKP/N 4 PKP/N 5 VR P/N 0 VR P/N 1
VR EG 1
3 3 3 3 3 3 3 3 5 5
VIN P0
/ VIN N 0
V0
VIN P1
/ VIN N 1
V1
8 to 1 V2
selector V3
VIN P2
/ VIN N 2
V8
8 to 1 V9
selector
VIN P3
/ VIN N 3
V20
8 to 1 V21
selector
VIN P4
Ladder / VIN N 4 G ray
Scale V43
resistor
block AM P V44
8 to 1
block
selector
VIN P5
/ VIN N 5
V55
8 to 1 V56
selector V57
VIN P6
/ VIN N 6
V62
8 to 1
selector
VIN P7
/ VIN N 7
V63
VG S
Configuration of Grayscale Amplifier
TOMATO LSI Inc. 113

Ver .1.0
VREG1
VRN0 V R N 0 < 4 :0 >

VRP0 V R P 0 < 4 :0 >
2~30R 2~30R
KVP0
KVP0 V IN N 0
V IN P 0
5R RP0 P K P 0 < 2 :0 > 5R RN0 P K N 0 < 2 :0 >
KVP1 KVN1
RP1 KVP2 RN1 KVN2
RP2 KVP3 RN2 KVN3
RP3 KVP4 RN3 KVN4
4R RP4 KVP5
8 to 1 V IN P 1 4R RN4 KVN5
8 to 1 V IN N 1
RP5 KVP6
SEL RN5 KVN6
SEL
RP6 KVP7 RN6 KVN7
RP7 KVP8 RN7 KVN8
VRHP VRHN
0~28R P R P 0 < 2 :0 > P K P 1 < 2 :0 > 0~28R P x R N 0 < 2 :0 > P x K N 1 < 2 :0 >
KVP9 KVN9
RP8 KVP10 RN8 KVN10
RP9 KVP11 RN9 KVN11
RP10 KVP12 R N10 KVN12
1R RP11 KVP13
8 to 1 V IN P 2 1R R N11 KVN13
8 to 1 V IN N 2
RP12 KVP14
SEL R N12 KVN14
SEL
5R RP15 P K P 2 < 2 :0 > 5R R N15 P K N 2 < 2 :0 >
KVP17 KVN17
1R RP19 KVP21
8 to 1 V IN N 3
RP20 KVP22
SEL R N20 KVN22
SEL
16R RP23 P K P 3 < 2 :0 > 16R R N23 P K N 3 < 2 :0 >
KVP25 KVN25
1R RP27 KVP29
8 to 1 V IN N 4
RP28 KVP30
SEL R N28 KVN30
SEL
5R RP31 P K P 4 < 2 :0 > 5R R N31 P x K N 4 < 2 :0 >
KVP33 KVN33
1R RP35 KVP37
8 to 1 V IN N 5
RP36 KVP38
SEL R N36 KVN38
SEL
VRLP VRLN
0~28R P R P 1 < 2 :0 > P K P 5 < 2 :0 > 0~28R P R N 1 < 2 :0 > P K N 5 < 2 :0 >
KVP41 KVN41
4R RP42 KVP45
8 to 1 V IN N 6
RP43 KVP46
SEL R N43 KVN46
SEL
5R RP46 5R R N46
KVP49 KVN49
V IN P 7 V IN N 7
VRP1 VRN1
V R P 1 < 4 :0 > V R N 1 < 4 :0 >
0~31R 0~31R
8R RP47 8R R N47
VSS
Ladder Amplifiers and 8 to 1 Selectors
TOMATO LSI Inc. 114

Ver .1.0
GAMMA Correction Registers
This block has register groups for specifying a grayscale voltage that meets the Gamma -characteristics for
the LCD panel used. These registers are divided into four groups, which correspond to the gradient,
amplitude, average value and fine adjustment of the grayscale characteristics for the voltage. The polarity of
each register can be specified independently. (Average value and R, G and B are common.)
G ra d ie n t A d ju s tm e n t A m p litu d e A d ju s tm e n t F in e A d ju s tm e n t
Grayscale Voltage
Grayscale Voltage
Grayscale Voltage
G ra y s c a le N u m b e r G ra y s c a le N u m b e r G ra y s c a le N u m b e r
Gamma Adjustment
1. Gradient adjustment registers: The gradient adjustment registers are used to adjust the gradient in the
middle of the grayscale characteristics for the voltage without changing the dynamic range. This function is
implemented by controlling the variable resistor (VRHP(N)/VRLP(N)) in the ladder resistor block for
grayscale voltage generation. A register can be separated into positive/negative polarities to perform an
asymmetric drive.
2. Amplitude adjustment registers: The amplitude adjustment registers are used to adjust the amplitude of
the grayscale voltage. This function is implemented by controlling the variable resistor (VRP(N)1/0) under the
ladder resistor block for grayscale voltage generation. There is an independent register on the
positive/negative polarities as well as the gradient adjustment register.
3. Fine adjustment registers: The fine adjustment register is to make subtle adjustment of the grayscale
voltage level. To accomplish the adjustment, it controls the each reference voltage level by the 8 to 1
selectors towards the 8-leveled reference voltage generated from the ladder resistor. Also, there is an
independent register on the positive/negative polarities as well as other adjustment register.
Gamma-Correction Registers
Resistor Groups Positive Polarity Negative Polarity Description
PRP0[2:0] PRN0[2:0] Variable resistor VRHP(N)

Gradient adjustment
PRP1[2:0] PRN1[2:0] Variable resistor VRLP(N)
Amplitude VRP0[4:0] VRN0[4:0] Variable resistor VRP(N) 0

adjustment VRP1[4:0] VRN1[4:0] Variable resistor VRP(N) 1
PKP0[2:0] PKN0[2:0] 8 to 1 selector (voltage level of grayscale 1)
Fine adjustment
TOMATO LSI Inc. 115

Ver .1.0
Ladder resistors and 8 to 1 selector
Block configuration
The block consists of two ladder resistors including variable one, and 8 to 1 selector which select one voltage
level generated by the ladder resistors and outputs the reference voltage for grayscale voltage.
Furthermore, the block has pins to connect a variable resistor. It can adjust the variation between panels.
Variable Resistor
The variable resistors are three types, gradient adjustment (VRHP(N)/VRLP(N)), the amplitude adjustment 1
(VRP(N)0), and amplitude adjustment 2 (VRP(N)1). The resistances are set by the gradient adjustment and
amplitude adjustment registers. Their relationship is shown below.
Gradient Adjustment Amplitude Adjustment (1) Amplitude Adjustment (2)

Register Resistor Value
Register Resistor Value Register Resistor Value
PRP(N) VRHP(N)
VRP(N)[4:0] VRP(N) 0 VRP(N)[4:0] VRP(N) 1
0/1[2:0] VRLP(N)
000 0R 00000 0R 00000 0R
001 4R 00001 1R 00001 1R
010 8R 00010 2R 00010 2R
011 12R : : : :
100 16R : : : :
101 20R 11101 29R 11101 29R
110 24R 11110 30R 11110 30R
111 28R 11111 31R 11111 31R
8 to 1 selector
In the 8 to 1 selector, the voltage level can be selected from the levels, which are generated by ladder
resistors. And output the six types of the reference voltage, the VIN-1 to VIN6. Following table explains the
relationship between the find-adjustment register and the selecting voltage.
The relationship between the fine-adjusting register and the selecting voltage
Register Value Selected Value

PKP(N) [2:0] VINP(N)1 VINP(N)2 VINP(N)3 VINP(N)4 VINP(N)5 VINP(N)6
000 KVP(N)1 KVP(N)9 KVP(N)17 KVP(N)25 KVP(N)33 KVP(N)41
TOMATO LSI Inc. 116

Ver .1.0
The grayscale levels are determined by the following formulas.

Voltage calculation formula (positive polarity) 1
Pin Equation Fine adjustment register value Reference voltage

KVP0 VREG1-∆V*VRP0 / SUMRP − VINP0
KVP1 VREG1-∆V*(VRP0+5R) / SUMRP PKP02_00 = “ 000 “
VINP1
KVP9 VREG1-∆V*(VRP0+33R+VRHP) / SUMRP PKP12_00 = “ 000 “
VINP2
VINP3
VINP4
VINP5
KVP41 VREG1-∆V*(VRP0+87R+VRHP+VRLP) / SUMRP PKP52_00 = “ 000 “
VINP6
KVP49 VREG1-∆V*(VRP0+120R+VRHP+VRLP) / SUMRP - VINP7
Note 1) Sum of ladder resistors with positive polarity = 128R+VRHP+VRLP+VRP0+VRP1

Note 2) Sum of ladder resistors with negative polarity = 128R+VRHN+VRLN+VRN0+VRN1
Note 3) ∆V : Electric potential difference between VREG1 and VGS
TOMATO LSI Inc. 117

Ver .1.0
Voltage calculation formula (positive polarity)
Gray scale Equation Gray scale Equation

V0 VINP0 V32 V20-(V20-V43)*12/23
V1 VINP1 V33 V20-(V20-V43)*13/23
V2 V1-(V1-V8)*(9/24) V34 V20-(V20-V43)*14/23
V3 V1-(V1-V8)*(12.5/24) V35 V20-(V20-V43)*15/23
V4 V1-(V1-V8)*(16/24) V36 V20-(V20-V43)*16/23
V5 V1-(V1-V8)*(18/24) V37 V20-(V20-V43)*17/23
V6 V1-(V1-V8)*(20/24) V38 V20-(V20-V43)*18/23
V7 V1-(V1-V8)*(22/24) V39 V20-(V20-V43)*19/23
V8 VINP2 V40 V20-(V20-V43)*20/23
V9 V8-(V8-V12)*6/24 V41 V20-(V20-V43)*21/23
V10 V8-(V8-V12)*12/24 V42 V20-(V20-V43)*22/23
V11 V8-(V8-V12)*18/24 V43 VINP4
V12 V8-(V8-V20)*8/24 V44 V43-(V43-V47)*6/24
V13 V12-(V12-V16)*6/24 V45 V43-(V43-V47)*12/24
V14 V12-(V12-V16)*12/24 V46 V43-(V43-V47)*18/24
V15 V12-(V12-V16)*18/24 V47 V43-(V43-V55)*8/24
V16 V8-(V8-V20)*16/24 V48 V47-(V47-V51)*6/24
V17 V16-(V16-V20)*6/24 V49 V47-(V47-V51)*12/24
V18 V16-(V16-V20)*12/24 V50 V47-(V47-V51)*18/24
V19 V16-(V16-V20)*18/24 V51 V43-(V43-V55)*16/24
V20 VINP3 V52 V51-(V51-V55)*6/24
V21 V20-(V20-V43)*1/23 V53 V51-(V51-V55)*12/24
V22 V20-(V20-V43)*2/23 V54 V51-(V51-V55)*18/24
V23 V20-(V20-V43)*3/23 V55 VINP5
V24 V20-(V20-V43)*4/23 V56 V55-(V55-V62)*2/24
V25 V20-(V20-V43)*5/23 V57 V55-(V55-V62)*4/24
V26 V20-(V20-V43)*6/23 V58 V55-(V55-V62)*6/24
V27 V20-(V20-V43)*7/23 V59 V55-(V55-V62)*8/24
V28 V20-(V20-V43)*8/23 V60 V55-(V55-V62)*11.5/24
V29 V20-(V20-V43)*9/23 V61 V55-(V55-V62)*15/24
V30 V20-(V20-V43)*10/23 V62 VINP6
V31 V20-(V20-V43)*11/23 V63 VINP7
Note 1) Make sure VLO – V0 > 0.5V, VLO – V8 > 1.1.V
TOMATO LSI Inc. 118

Ver .1.0
Table Equations of voltage calculation
Pin Equation Fine adjustment register value Reference voltage

KVP0 VREG1-∆V*VRP0 / SUMRN − VINN0
KVN1 VREG1-∆V*(VRN0+5R) / SUMRN PKN02_00 = “ 000 “
VINN1
KVN9 VREG1-∆V*(VRN0+33R+VRHN) / SUMRN PKN12_00 = “ 000 “
VINN2
VINN3
VINN4
VINN5
KVN41 VREG1-∆V*(VRN0+87R+VRHN+VRLN) / SUMRN PKN52_00 = “ 000 “
VINN6
KVN49 VREG1-∆V*(VRN0+120R+VRHN+VRLN) / SUMRN - VINN7
Note 1) Sum of ladder resistors with positive polarity = 128R+VRHP+VRLP+VRP0+VRP1

Note 2) Sum of ladder resistors with negative polarity = 128R+VRHN+VRLN+VRN0+VRN1
Note 3) ∆V : Electric potential difference between VREG1 and VGS
TOMATO LSI Inc. 119

Ver .1.0
Voltage calculation formula (negative polarity)
Gray scale Equation Gray scale Equation

V0 VINP0 V32 V20-(V20-V43)*12/23
V1 VINP1 V33 V20-(V20-V43)*13/23
V2 V1-(V1-V8)*(9/24) V34 V20-(V20-V43)*14/23
V3 V1-(V1-V8)*(12.5/24) V35 V20-(V20-V43)*15/23
V4 V1-(V1-V8)*(16/24) V36 V20-(V20-V43)*16/23
V5 V1-(V1-V8)*(18/24) V37 V20-(V20-V43)*17/23
V6 V1-(V1-V8)*(20/24) V38 V20-(V20-V43)*18/23
V7 V1-(V1-V8)*(22/24) V39 V20-(V20-V43)*19/23
V8 VINP2 V40 V20-(V20-V43)*20/23
V9 V8-(V8-V12)*6/24 V41 V20-(V20-V43)*21/23
V10 V8-(V8-V12)*12/24 V42 V20-(V20-V43)*22/23
V11 V8-(V8-V12)*18/24 V43 VINP4
V12 V8-(V8-V20)*8/24 V44 V43-(V43-V47)*6/24
V13 V12-(V12-V16)*6/24 V45 V43-(V43-V47)*12/24
V14 V12-(V12-V16)*12/24 V46 V43-(V43-V47)*18/24
V15 V12-(V12-V16)*18/24 V47 V43-(V43-V55)*8/24
V16 V8-(V8-V20)*16/24 V48 V47-(V47-V51)*6/24
V17 V16-(V16-V20)*6/24 V49 V47-(V47-V51)*12/24
V18 V16-(V16-V20)*12/24 V50 V47-(V47-V51)*18/24
V19 V16-(V16-V20)*18/24 V51 V43-(V43-V55)*16/24
V20 VINP3 V52 V51-(V51-V55)*6/24
V21 V20-(V20-V43)*1/23 V53 V51-(V51-V55)*12/24
V22 V20-(V20-V43)*2/23 V54 V51-(V51-V55)*18/24
V23 V20-(V20-V43)*3/23 V55 VINP5
V24 V20-(V20-V43)*4/23 V56 V55-(V55-V62)*2/24
V25 V20-(V20-V43)*5/23 V57 V55-(V55-V62)*4/24
V26 V20-(V20-V43)*6/23 V58 V55-(V55-V62)*6/24
V27 V20-(V20-V43)*7/23 V59 V55-(V55-V62)*8/24
V28 V20-(V20-V43)*8/23 V60 V55-(V55-V62)*11.5/24
V29 V20-(V20-V43)*9/23 V61 V55-(V55-V62)*15/24
V30 V20-(V20-V43)*10/23 V62 VINP6
V31 V20-(V20-V43)*11/23 V63 VINP7
Note 1) Make sure VLO – V0 > 0.5V, VLO – V8 > 1.1.V
TOMATO LSI Inc. 120

Ver .1.0
Relationship between RAM data and output level
V0
Negative Polarity
Output Level
Positive Polarity
V63
"000000" RAM Data "111111"
RAM Data and Output Voltage
Sn
Negative Polarity
VCOM Positive Polarity
Source output and VCOM
TOMATO LSI Inc. 121

Ver .1.0
GRAM data and LCD Grayscale level (REV = 0)
GRAM Data Selected gray level GRAM Data Selected gray level
RGB Negative Positive RGB Negative Positive
6’h00 V0 V63 6’h20 V32 V31
6’h01 V1 V62 6’h21 V33 V30
6’h02 V2 V61 6’h22 V34 V29
6’h03 V3 V60 6’h23 V35 V28
6’h04 V4 V59 6’h24 V36 V27
6’h05 V5 V58 6’h25 V37 V26
6’h06 V6 V57 6’h26 V38 V25
6’h07 V7 V56 6’h27 V39 V24
6’h08 V8 V55 6’h28 V40 V23
6’h09 V9 V54 6’h29 V41 V22
6’h0A V10 V53 6’h2A V42 V21
6’h0B V11 V52 6’h2B V43 V20
6’h0C V12 V51 6’h2C V44 V19
6’h0D V13 V50 6’h2D V45 V18
6’h0E V14 V49 6’h2E V46 V17
6’h0F V15 V48 6’h2F V47 V16
6’h10 V16 V47 6’h30 V48 V15
6’h11 V17 V46 6’h31 V49 V14
6’h12 V18 V45 6’h32 V50 V13
6’h13 V19 V44 6’h33 V51 V12
6’h14 V20 V43 6’h34 V52 V11
6’h15 V21 V42 6’h35 V53 V10
6’h16 V22 V41 6’h36 V54 V9
6’h17 V23 V40 6’h37 V55 V8
6’h18 V24 V39 6’h38 V56 V7
6’h19 V25 V38 6’h39 V57 V6
6’h1A V26 V37 6’h3A V58 V5
6’h1B V27 V36 6’h3B V59 V4
6’h1C V28 V35 6’h3C V60 V3
6’h1D V29 V34 6’h3D V61 V2
6’h1E V30 V33 6’h3E V62 V1
6’h1F V31 V32 6’h3F V63 V0
TOMATO LSI Inc. 122

Ver .1.0
8-color Display Mode
TL1763 incorporates an 8-color display mode. The grayscale level to be used is V0 and V63, and the other
levels (V1-V62) are stopped. In addition to AC frequency and interval scan, the step-up clocks are reduced to
1/2 FDCDC, thereby power consumption is reduced.
Gamma -fine-adjustment registers, PKP0-PKP5 and PKN0-PKN5 are invalid in 8-color display mode. Since
V1-V62 are stopped, the RGB data in the GRAM should be set to 000000 or 111111 before setting the mode
so that V0 or V63 is selected.
GRAM
MSB -------------------------------------------------------------------------------------------------------------------------------- LSB
Display data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
V0
Positive polarity Negative polarity 6 6 6
register register
PKP0[2:0] PKN0[2:0]
PKP1[2:0] PKN1[2:0] Gray 2 grayscale 2 grayscale 2 grayscale
8 2
PKP2[2:0] PKN2[2:0] scale control control control
PKP3[2:0] PKN3[2:0] AMP <R> <G> <B>
PKP4[2:0] PKN4[2:0]
PKP5[2:0] PKN5[2:0] V63
PRP0[2:0] PRN0[2:0]
PRP1[2:0] PRN1[2:0] LCD driver LCD driver LCD driver
VRP0[4:0] VRN0[4:0]
VRP1[4:0] VRN1[4:0]
R G B
LCD
Gray scale control to display 8 colors
TOMATO LSI Inc. 123

Ver .1.0
Low power consumption driving settings
TL1763 has various settings for a low power consuming display.

The low power consumption and the display quality are in trade-off, and the power-saving effect may vary
according to a panel. Make appropriate settings on the following items taking power-saving effects and
screen quality into consideration.
8 colors display mode (CL bit)

When this mode is selected (CL = 1), voltage generation for grayscale levels other than V0 and V63 levels
are terminated. By reducing step-up clocks to 1/2 FDCDC, only 8 colors can be available for display, thereby
saving power consumption.
Interval Scan mode

The interval gate scan setting enables reduction of power consumption to minimum by generating gate scan
at frame frequency set with ISC bits. Longer scan generation frequency may affect the quality of display.
Make appropriate setting by taking trade-off between power-saving effects and display quality.
Frame frequency setting

Frame frequency adjusting functions allows changing LCD AC frequency through instruction. Frame
frequency can be reduced to low power consumption when a low-power-consuming display method such as
partial display is employed. See “frame frequency adjustment function” section.
Generally, lower frame frequency and quality of display are in trade-off. Power-saving effects and quality of
display also varies according to a panel. Check actual quality of display on the panel before use. See “Flame
frequency adjustment function”
LCD AC method setting

TL1763 allows to select LCD AC method through instructions (B/C, EOR, NW) from frame reversed AC
driving, 3 field interlace driving, and n-raster-raw reversed AC driving. Select an appropriate method for
display.
Generally, lower frame frequency and quality of display are in trade-off. Power-saving effects and quality of
display also varies according to a panel. Check actual quality of display on the panel before use. See “AC
drive timing”
Optimization of step-up scale ratio

By optimizing step-up scale ratio (adoption of lower VGH and VGL scale), power loss can be minimized
when LCD is being driven. Make appropriate settings for each LCD panel. VGH and VGL step-up scale ratio
is set with BT bits.
VCOML = VSS (VCOMG bit = 0)

By setting VCOMLG bit to 0, operations of VCOML generation circuits and VCL voltage generation can be
halted, thereby saving power consumption. VCL connection capacitor is not required in this mode. Note that
availability of this mode depends on an LCD panel.
TOMATO LSI Inc. 124

Ver .1.0
Power generation circuit block diagram
VCIF
VREG2
INTERNAL GRAY SCALE
VSS REFERENCE REGP VREG1 GENERATOR
VOLTAGE
GENERATOR
S1 ~ S720
VREG1
VREG1
SOURCE DRIVER
REGULATOR
VREG2 VGH
VREG2 GATE DRIVER G1 ~ G 320
REGULATOR VGL
VCOMR
VCOM LEVEL
CONTROLER
C11+ CNT
VCOMH
C11-
VCOMH
GENERATOR
C12+ VOLTAGE
BOOSTING
CIRCUIT1 VCOML
C12- VCOML
GENERATOR
VLO
VCOMH VCOM
VCOM
DRIVER
VCOML
C21+
VCC
C21- INTERNAL
LOGIC
REGULATOR VSS
C22+
VCCL
C22-
C23+
IOVCC
C23-
VOLTAGE
BOOSTING
C31+ CIRCUIT2
VCI VCI
C31-
VGH
VGL
Note 1,2
VCL
Note 1,2
Note 3
TL1763
Note 1 ) Place a schottky diode (VF = about 0.4V/ 20mA , VR> = 30V).
Note 2 ) Wiring from GND and VGL to the schottky dioode must be 10Ω or less.
Note 3 ) Capacitors are not required when VCOMG = 0 ( VCOML= GND).
TL1763 LCD drive voltage generation circuit
TOMATO LSI Inc. 125

Ver .1.0
Specification on TL1763 power circuit and external elements
The following tables show the specification on external elements connected to a power circuit.
Capacitor
Capacitance Recommended
Connection pin
capacity capacitor voltage
VCCL, VREG1, VREG2, VCL
6V
VCOMH, VCOML, C11-/+, C12-/+, C31+/-
1uF
10V VLO, C21+/-, C22+/-, C23+/-
25V VGH, VGL

Note 1) Capacitor connection does not always required according to the modes.
Schottky diode
Specification Pin connection
VSS to VGL
VF < 0.4V/20mA@25°C,VR≥30V VSS to VCL
(VGH to VCI)
Variable resistor
Specification Pin connection
> 200kΩ VCOMR
TOMATO LSI Inc. 126

Ver .1.0
Pattern Diagrams for Voltage Setting
■ The following are examples of pattern diagram and waveform of TL1763.
VGH(+7.4~+21. 52 V)
BT
VCIx2
VLO(5.0~6.6V)
VCI(2.5~3.3V) REGPx2
VREG2(3.70~6.072V)
VREG1
VCIF(2.5~3.3V) VC x2 VREG1(3.0~(VREG2-0.5)V)
VCM
REGP VRH
VCC(2.4~3.3V) VCOMH(3.0~(VREG1-0.5)V)
VCOMG VDV
IOVCC(1.7~3.3V)
VSS(0V)
VCOML((VCL+0.5)~1V)
-VCI
VCL(0~-3.3V)
BT
VGL(-6.2~-15.44V)
Pattern diagram for voltage setting
Note 1) Each VLO, VGH, VGL and VCL output depends on current consumption required for each of these
outputs. The voltage may drop from set voltage (ideal voltage). (VREG2-VREG1) > 0.5V,
(VCOML – VCL) > 0.5V show the relationship in relation to actual voltage.
When AC frequency of VCOM occurs at a higher rate (e.g. alternation occurs every line), current
consumption is large. In such a case, check voltage before use.
VGH
VREG1
VCOMH
VCOM
VCOML
Sn (Source driver output)
VGL
Gn (Gate driver output )
Pattern diagram of applying voltage to TFT display
TOMATO LSI Inc. 127

Ver .1.0
Power supply setting flow
The following show the sequence regarding power ON and OFF. Follow these sequences when executing
display ON/OFF, standby set/off, sleep set/off.
[ Power On sequence ] [ Power Off sequence ]
Power supply(VCC, VCI, VCIF, IOVCC) On

Standard display D=2'h3,GON=1
VCI,VCIF
IOVCC
VCC
GND Difplay off sequence

VCC => IOVCC => VCI => VCIF or
VCC,IOVCC,VCI,VCIF simultaneously
Power off set Power supply stop set bits
instruction (1) VCOMG=0, SAP=0
Power on reset 1ms or

Display off bits
over
1ms or D=2'h0,GON=0
over PON=0,,VCOMG=0 Power supply stop set bits
Power off set
Source driver instruction (2) AP=3'h0, PON=0
oscillation start
stable time of
10ms or
oscillation circuit
over Power user set
D=2'h1 VC,VRH,VCM,VDV,COM set Power supply(VCC, VCI, IOVCC) Off
Power initial set bits VCI,VCIF

Power starting set VCOMG=0,PON=0 IOVCC
instruction BT=0000,DC0=110,DC1=000 VCC
GND
Power starting set Power action starting set bits
instruction (1) AP set VCIF => VCI => IOVCC => VCC or
PON=1 VCC,IOVCC,VCI,VCIF simultaneously
40ms or Stable time of

over boosting circuit
Power supply operation setting bit

Power starting set VCOMG=1
100ms or instruction (2) Power supply user setting
over Stable time of BT,DC0,DC1
OP-AMP Other modes set
Power supply user setting
instruction
SAP=1
Display On flow
Power supply ON/OFF sequence
TOMATO LSI Inc. 128

Ver .1.0
Instruction setting flow
Follow the following sequence when making an instruction setting with TL1763.
Display ON/OFF flow
[ Display off ] [ Display on ]
Display off
Power supply setting
GON = 1
DTE = 1
D1-0 = 10
Display on
GON = 0
DTE = 0
D1-0 = 00
Wait (2 frames or more)

Display off
GON = 0
DTE = 0
D1-0 = 00
Display on
GON = 0
DTE = 0
D1-0 = 01
"Display off"
Display on
GON = 1
DTE = 1
D1-0 = 01
Display on
GON = 1
DTE = 1
D1-0 = 11
"Display on"
Note 1) See “Power supply setting flow” section for setting a power supply.
TOMATO LSI Inc. 129
Ver .1.0
Standby, Sleep mode set/release
[Standby mode] [Sleep mode]
Display off flow Display off flow
Standby Sleep
Standby set (STB = 1) set Sleep set (SLP = 1) set
: :
: :
: :
Continue more than 5 frame Continue more than 5 frame
: :
: :
: :
Standby release (STB = 0) Sleep release (SLP = 0)

Standby Sleep
release release
Wait more than 2 frame Wait more than 2 frame
Display on flow Display on flow
TOMATO LSI Inc. 130

Ver .1.0
8-color mode setting
[ 260K Colors Æ 8 Colors ] [ 8 Colors Æ 260K Colors ]
Display off Display off

GON = 1 GON = 1
DTE = 1 DTE = 1
D1-0 = 11 D1-0 = 11
Wait(more then 2 frames) Wait(more then 2 frames)

GON = 1 GON = 1
DTE = 1 DTE = 1
D1-0 = 00 D1-0 = 00
Wait(more then 2 frames) Wait(more then 2 frames)

GON = 0 GON = 0
DTE = 0 DTE = 0
D1-0 = 00 D1-0 = 00
RAM Data Setting RAM Data Setting
CL = 1 CL = 0
Wait(more then 40ms) Wait(more then 40ms)
Display on Display on
GON = 1 GON =1
DTE = 1 DTE = 1
D1-0 = 00 D1-0 = 00
Wait for at least 2H periods Wait for at least 2H periods
Display on Display on
GON = 1 GON = 1
DTE = 1 DTE = 1
D1-0 = 11 D1-0 = 11
8 color display 260K color display
TOMATO LSI Inc. 131

Ver .1.0
10. SPECIFICATIONS
Absolute Maximum Ratings
Item Symbol Unit Value Note*

Power supply voltage (1) VCC V -0.3 ~ +3.6 1,2
Power supply voltage (2) IOVCC V -0.3 ~ +3.6 1,2
Power supply voltage for step-up circuit VCI V -0.3 ~ +3.6 1,2
Power supply voltage for regulator circuit VCIF V -0.3 ~ +3.6 1,2
LCD Power supply voltage range | VGH – VGL | V -0.3 ~ +35 1,2
Input voltage range Vin V -0.5 ~ VCC+0.5 1
Operating temperature Topr °C -40 ~ +85 1,3
Storage temperature Tstg °C -55 ~ +110 1
Notes: 1. If the LSI is used above these absolute maximum ratings, it may become permanently damaged.
Using the LSI within the following electrical characteristic limit is strongly recommended for normal
operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction
and cause poor reliability.
2. Indicate the voltage form VSS = 0V
3. DC characteristics and AC characteristics of shipping chips and shipping wafer are guaranteed
at 85°C.
TOMATO LSI Inc. 132

Ver .1.0
DC Characteristics
DC Characteristics (VCC = 2.4 to 3.3V, IOVCC = 1.7 to 3.3V, Ta = +25°C)

Item Symbol Condition Min. Typ. Max. Unit Note
IOVCC - 1.7 - 3.3 V *1
VCC - 2.4 - 3.3 V *1
Operating voltage
VCI - 2.5 - 3.3 V *1
VCIF - 2.5 - 3.3 V *1
High VIH - 0.8xIOVCC - IOVCC V *2
Logic input voltage
Low VIL - -0.2 - 0.2xIOVCC V *2
High VOH IOH = -0.1mA 0.8xIOVCC - IOVCC V *3
Logic output voltage
Low VOL IOL = 0.1mA -0.2 - 0.2xIOVCC V *3
Input leakage current IIL Vin = VSS or IOVCC -1.0 - 1.0 uA
Output leakage current IOL Vin = VSS or IOVCC -3.0 - 3.0 uA
Operating frequency Fosc Rf = 80 KΩ, VCC=2.8V 450 500 550 KHz *4
Notes : 1. VSS = 0V
2. Applied pins : IM3-0, CSB, RS, E_WRB, RW_RDB, DB0 to DB17, RESETB
3. Applied pins : DB0 to DB17
4. Target frame frequency = 70Hz, Display line = 320, Back porch = 8, Front porch = 8
Internal register, NL5-0 = “101000000”, RTN3-0 = “0000”, DIV1-0 = “00”
TOMATO LSI Inc. 133

Ver .1.0
DC Characteristics for LCD driver outputs (VCC = 2.4 to 3.3V, IOVCC = 1.7 to 3.3V, Ta = +25°C)
Item Symbol Condition Min. Typ. Max. Unit Note
VGH - VGL = 30V

LCD gate driver output on
Ron VGH = 18V - 1 1.5 KΩ *1
resistance
VGL = -12V
Output voltage deviation

DVO VSO - - ±10 mV *2
(pin to pin)
VLO = 5.6V,
LCD source driver delay tSD - - 10 uS *3
VREG1 = 4.0V,
Current consumption during Standby mode, Ta = +25°C

Istby - 6 10 uA *4
standby mode VCC=IOVCC=VCI=VCIF= 2.8V
IVCC No Load, Ta = +25°C

Current consumption during
VCC=IOVCC=VCI=VCIF= 2.8V - - 7 mA *5
normal operation
IVCI 260k color black data display
Notes : 1. VGO is the output voltage of analog output pins G1 to G320.

2. VSO the output voltage of analog output pins S1 to S720
VRGE1 = 4.9V
3. VLO = 5.6V, VREG1 = 4.0V, Ffr= 60HZ, Ta=25℃,
Same change in all node, same gray scales ±35mV arrival time in VCOM polarity change.
4. VCC = IOVCC = VCI = VCIF = 2.8V, VGS = VSS and standby mode.
5. VCC = IOVCC = VCI = VCIF = 2.8V, VGS = VSS
Fosc = 443KHz(320 display line),
Internal register, NL8-0 = “101000000”, RTN3-0 = “0000”, DIV1-0 = “00”
Internal power registers, VC2-0 = “001”, BT3-0 = “0011”, VRH3-0 = “1011”,
VCM5-0 = “111000”, VDV4-0 = “10000”
TOMATO LSI Inc. 134

Ver .1.0
AC Characteristics
● 68/80 mode bus interface timing characteristics
VIH VIH
RS
VIL VIL
tAS tAH
VIH
CSB
VIL
tPWLW, tPWLR tPWHW, tPWHR
WRB VIH VIH VIH

VIL VIL
RDB
tF tR
tCYCW, tCYCR
tDSW tDHW
VIH VIH
DB17~0 Write data
VIL VIL
tDDR tDHR
VOH VOH
DB17~0 Read data
VOL VOL
80-system AC Timing
RS VIH VIH
R/W VIL VIL
tAS tAH
VIH
CSB
VIL
tPWHW, tPWHR tPWLW, tPWLR
VIH VIH
E VIL VIL VIL
tR tF
tCYCW, tCYCR
tDSW tDHW
VIH VIH
DB17~0 Write data
VIL VIL
tDDR tDHR
VOH VOH
DB17~0 Read data
VOL VOL
68-system AC Timing
TOMATO LSI Inc. 135

Ver .1.0
● 68/80 mode bus interface (18bit / 16bit transmission mode)
IOVCC = 1.7 to 3.3V, VCC = 2.4 to 3.3V, Ta = +25°C

Item Symbol Min. Max. Unit
Write tCYCW 100 -
System cycle time
Read tCYCR 250 -
Write tPWHW 40 -
Enable high pulse width
Read tPWHR 70 -
Write tPWLW 40 -
Enable low pulse width
Read tPWLR 100 -
Write/Read pulse rise/fall time tR, tF - 25 ns
Address setup time tAS 10 -
Address hold time tAH 5 -
Write data setup time tDSW 25 -
Write data hold time tDHW 5 -
Read data delay time tDDR - 100
Read data hold time tDHR 5 -
● 68/80 mode bus interface (9 bit / 8 bit / 6 bit transmission mode)

Write tCYCW 80 -
System cycle time
Read tCYCR 250 -
Write tPWHW 30 -
Enable high pulse width
Read tPWHR 70 -
Write tPWLW 30 -
Enable low pulse width
Read tPWLR 100 -
Write/Read pulse rise/fall time tR, tF - 25 ns
Address setup time tAS 10 -
Address hold time tAH 5 -
Write data setup time tDSW 25 -
Write data hold time tDHW 5 -
Read data delay time tDDR - 100
Read data hold time tDHR 5 -
TOMATO LSI Inc. 136

Ver .1.0
● Clock synchronous serial interface timing characteristics
Transfer Start Transfer End
CSB VIH
VIL VIL
tSCYCW
tSCYCR
tCSS tR tSCHW tSCLW
tCSH
tSCHR tSCLR
tF
SCL VIH VIH VIH
VIH
VIL VIL VIL
VIL
tSIDS tSIDH
SDI VIH VIH

Input data VIL Input data
VIL
tSOD tSOH
SDO
VOH VOH
Output data Output data
VOL VOL
Clock Synchronized Serial Interface AC Timing
Clock synchronous serial interface

Write tSCYCW 100 -

Serial clock cycle time
Read tSCYCR 250 -
Serial clock high pulse Write tSCHW 40 -
width Read tSCHR 110 -
Serial clock low pulse Write tSCLW 40 -
width Read tSCLR 110 -
Serial clock rise/fall time tR, tF - 20 ns
Chip select setup time tCSS 20 -
Chip select hold time tCSH 60 -
Serial input data setup time tSIDS 30 -
Serial input data hold time tSIDH 30 -
Serial output data delay time tSOD - 130
Serial output data hold time tSOH 5 -
TOMATO LSI Inc. 137

Ver .1.0
● RGB interface timing characteristics

tR
tF tSYNCS
VSYNC VIH VIH
HSYNC VIL VIL
tENS tENH
VIH VIH
ENABLE
VIL VIL
tF tR
tPWDL tPWDH
VIH VIH VIH
DOTCLK
VIL VIL VIL
tCYCD
tPDS tPDH
VIH VIH
DB17-0 Input Data
VIL VIL
RGB Interface AC Timing
18/16 bit RGB interface, IOVCC = 1.7 to 3.3V, VCC = 2.4 to 3.3V, Ta = +25°C
DOTCLK cycle time tCYCD 100 -
DOTCLK high pulse width tPWDH 40 -
DOTCLK low pulse width tPWDL 40 -
DOTCLK, VSYNC, HSYNC
trgbr, trgbf - 20
rising, falling time
ns
VSYNC / HSYNC set up time tSYNCS 10 -
ENABLE setup time tENS 30 -
ENABLE hold time tENH 20 -
Data setup time tPDS 30 -
Data hold time tPDH 20 -
6 bit RGB interface, IOVCC = 1.7 to 3.3V, VCC = 2.4 to 3.3V, Ta = +25°C
DOTCLK cycle time tCYCD 60 -
DOTCLK high pulse width tPWDH 25 -
DOTCLK low pulse width tPWDL 25 -
DOTCLK, VSYNC, HSYNC
trgbr, trgbf - 20
rising, falling time
VSYNC / HSYNC set up time tSYNCS 10 - ns
ENABLE setup time tENS 20 -
ENABLE hold time tENH 10 -
Data setup time tPDS 20 -
Data hold time tPDH 10 -
TOMATO LSI Inc. 138

Ver .1.0
● Reset timing characteristics
tRES trRES
VIH
RESETB
VIL VIL
IOVCC = 1.7 to 3.3V, VCC = 2.4 to 3.3V

Reset low-level width tRES 1 - Ms
Reset rise time trRES - 10 Us
● LCD driver output
VCOM
tDD
Gray scale voltage +-35mV
S1-S720
Gray scale voltage +-35mV
TOMATO LSI Inc. 139

Ver .1.0
11. CHIP FORMAT
C J J J J
C
1307
331
D D
1308 330
G G
H H
G I I I I I I I I I I I I G
Y
X Top View
TL1763 (0,0) (Bump View)
G G
H H
G G
1350 E F E* E F 288
287
B 1 B
A A
F*
Pad Dimensions <Basis of Bump Pad> [unit : um]

Pad name Pad number X Y
Chip Size (without S/L) - 21390 1390
Chip Size (with S/L) - 21500 1500
Input Pad 1 ~ 287 44 100
Output Pad 288 ~ 1350 21 100
Bumped Pad Height 1 ~ 1350 15um ± 3um
Chip Thickness - 400um ± 20um
Chip Outline Dimensions <Basis of Bump Pad> [unit : um]

Symbol Dimension Symbol Dimension
A 619 B 126.5
C 436.5 D 234.5
E 70 F 26
E* 78 F* 34
G 24 H 3
I 21 J 0
Note) E*, F* is for only Pad number of 199,201,202,206,207,238~243.
TOMATO LSI Inc. 140

Ver .1.0
DUMMY29
DUMMY26
234.5um
G69
G73
G77
G1
G5
G9
126.5um
DUMMY28
DUMMY27
G71
G75
G3
G7
436.5um
619um
DUMMY25
DUMMY24
G79
G81
DUMMY1 1
1
G83
DUMMY2 2
G85
DUMMY3 3
G87
VCOM 4 : G89
VCOM 5 :
VCOM 6
: :
30
VCOM : :
(31ea) 32
VCOM
VCOM 33
VCOM 34
DUMMYR1 DUMMYR1 35
DUMMYR2 DUMMYR2 36
VGH 37
VGH 38
VGH VGH 39
40
VGH 40
C21P 41
C21P C21P 42
C21M 43
C21M 44
C21M
45
C22P C22P
C22P 46
C22M C22M 47
C22M 48
C23P C23P 49
50
C23P 50
C23M 51
C23M C23M 52
VGL 53
VGL VGL 54
VGL 55
VGL 56
VLO 57
VLO 58
VLO 59
60
VLO VLO 60
VLO 61
TL1763
VLO 62
VLO 63
G309
VLO 64
G311
C11P 65
G313
C11P 66
G315
C11P 67
C11P G317
C11P 68
G319
C11P 69
70
DUMMY23
C11P 70
DUMMY22
C11M 71
DUMMY21
C11M 72
C11M 73 DUMMY20
C11M C11M 74 S1
C11M 75 S2
C11M 76 S3
C12P 77 S4
C12P 78 S5
C12P 79 S6
C12P
80
C12P 80
C12P 81
C12P 82
C12M 83
C12M 84
C12M 85
C12M 86
C12M
C12M 87
C12M 88
89
C31P
90
90
C31P
C31P 91
C31P 92
C31P
C31P 93
C31P 94
C31M 95
C31M 96
C31M C31M 97
C31M 98
C31M 99
100
C31M 100
VCL 101
VCL 102
VCL VCL 103

VCL 104
VCL 105
VCL 106
VREG1 107
VREG1 108
VREG1 VREG1 109
110
VREG1 110
VREG2 111
VREG2 112
VREG2 113
VREG2 114
VREG2 VREG2 115
VREG2 116
VREG2 117
VREG2 118
VCIF 119
120
TL1763 Pad configuration

VCIF VCIF 120
VCI 121
VCI 122
VCI 123
VCI 124
VCI 125
VCI 126
VCI 127
VCI 128
VCI 129
130
VCI 130
VCI 131
VCI VCI 132
VCI 133
VCI 134
VCI 135
VCI 136
VCI 137
VCI 138
VCI 139
S356
140
VCI 140 S357

VCI 141 S358
VCI 142 S359
VCC 143 S360
VCC 144 DUMMY19
VCC 145 DUMMY18
VCC VCC 146 DUMMY17
VCC 147
Y
S361
(0,0)
VCC 148
S362
IOVCC 149
S363
IOVCC
150
IOVCC 150
S364
VCCL 151
S365
VCCL 152
VCCL 153
VCCL
VCCL 154
VCCL 155
VCCL 156
VSS1 157
VSS1 158
VSS1 159
160
VSS1 160
VSS1 161
VSS1 162
RAM/LOGIC VSS VSS1 163
VSS1 164
X
VSS1 165
VSS1 166
VSS1 167
VSS1 168
VSS1 169
170
VSS2 170
VSS2 171
I/O VSS VSS2 172
VSS2 173
VSS3 174
OSC VSS VSS3 175

VSS3 176
VSS3 177
VSS4 178
GRAY SCALE VSS
VSS4 179
180
VSS5 180
VSS5 181
VSS5 182
VSS5 183
VSS5 184
VSS5 185
ANALOG VSS VSS5 186
VSS5 187
VSS5 188
VSS5 189
190
VSS5 190
VSS5 191
VSS6 192
VSS6 193
VSS6 194
DRIVER VSS VSS6 195
VSS6 196
VSS6 197
VGS VGS 198
REGOFF REGOFF 199
200
RESETB RESETB 200

IOVCCDUM 201
IM0/ID IM0/ID 202
IM1 IM1 203
IM2 IM2 204
IM3 IM3 205
IOGNDDUM
(Bump View)
206
DB17 DB17 207
DB16 DB16 208 S715
DB15 DB15 209
Top View
S716
210
DB14 DB14 210

S717
DB13 DB13 211
S718
DB12 DB12 212
S719
DB11 DB11 213
S720
DB10 DB10 214
DUMMY16
DB9 DB9 215
DB8 DB8 216 DUMMY15
DB7 DB7 217 DUMMY14

DB6 DB6 218 DUMMY13
DB5 DB5 219 G320
220
DB4 DB4 220 G318

DB3 DB3 221 G316
DB2 DB2 222
G314
DB1 DB1 223 G312
DB0 DB0 224
G310
SDO SDO 225
SDI SDI 226
RW_RDB RW_RDB 227
E_WRB/SCL E_WRB/SCL 228
RS RS 229
230
CSB CSB 230
VSYNC VSYNC 231
HSYNC HSYNC 232
DOTCLK DOTCLK 233
ENABLE ENABLE 234

FLM FLM 235
M M 236
CL CL 237
OSCDUM1 238
OSC1 OSC1 239

240
OSCDUM2 240
OSC2 OSC2 241

OSCDUM3 242
VCOML 243
VCOML 244
VCOML VCOML 245
VCOML 246
VCOMH 247
VCOMH 248
VCOMH
VCOMH 249
250
VCOMH 250
VCOMR VCOMR 251
DUMMYR3 DUMMYR3 252
DUMMYR4 DUMMYR4 253
VCOM 254 :
VCOM 255 :
VCOM 256
: :
280
VCOM : :
(31ea)
VCOM 282
VCOM 283
VCOM 284
G90
DUMMY4 285 G88
DUMMY5 286
G86
DUMMY6 287
G84
G82
G80
DUMMY12
DUMMY11
619um
436.5um
DUMMY8
DUMMY9
G72
G76
G4
G8
126.5um 234.5um
DUMMY7
DUMMY10
G10
G70
G74
G78
G2
G6
TOMATO LSI Inc. 141

Ver .1.0
12. BUMP
21 27 21
100
3 3
G1 ~ G78 140 40
100
S = 2,100um2
24 24
Unit : um
21 21 21
100
G79 ~ G320
0 0
140 40
S1 ~ S720
100
S = 2,100um2
21 21
Unit : um
44 26
I/O pins
100
S = 4,400um2
Min. 70
Unit : um
TOMATO LSI Inc. 142

Ver .1.0
13. ALIGN KEY
100
50
30
100 40 50 50 50
40
50
30
Left & Down (-10464 , -602) Right & Down (10464 , -602)
30 40 30
Left & Up (-10464 , 563.8)

Right & Up (10464 , 563.8)
Output
Y
(-10464 , 563.8) (10464 , 563.8)
Top View X
(Bump View) (0,0)
(-10464 , -602) (10464 , -602)
Input
TOMATO LSI Inc. 143

Ver .1.0
14. PAD CENTER COORDINATES

Pad center coordinates [Unit: um]
Pad No Pad Name X Y Pad No Pad Name X Y
1 DUMMY1 -10054 -627 51 C23M -6554 -627
2 DUMMY2 -9984 -627 52 C23M -6484 -627
3 DUMMY3 -9914 -627 53 VGL -6414 -627
4 VCOM -9844 -627 54 VGL -6344 -627
5 VCOM -9774 -627 55 VGL -6274 -627
6 VCOM -9704 -627 56 VGL -6204 -627
7 VCOM -9634 -627 57 VLO -6134 -627
8 VCOM -9564 -627 58 VLO -6064 -627
9 VCOM -9494 -627 59 VLO -5994 -627
10 VCOM -9424 -627 60 VLO -5924 -627
11 VCOM -9354 -627 61 VLO -5854 -627
12 VCOM -9284 -627 62 VLO -5784 -627
13 VCOM -9214 -627 63 VLO -5714 -627
14 VCOM -9144 -627 64 VLO -5644 -627
15 VCOM -9074 -627 65 C11P -5574 -627
16 VCOM -9004 -627 66 C11P -5504 -627
17 VCOM -8934 -627 67 C11P -5434 -627
18 VCOM -8864 -627 68 C11P -5364 -627
19 VCOM -8794 -627 69 C11P -5294 -627
20 VCOM -8724 -627 70 C11P -5224 -627
21 VCOM -8654 -627 71 C11M -5154 -627
22 VCOM -8584 -627 72 C11M -5084 -627
23 VCOM -8514 -627 73 C11M -5014 -627
24 VCOM -8444 -627 74 C11M -4944 -627
25 VCOM -8374 -627 75 C11M -4874 -627
26 VCOM -8304 -627 76 C11M -4804 -627
27 VCOM -8234 -627 77 C12P -4734 -627
28 VCOM -8164 -627 78 C12P -4664 -627
29 VCOM -8094 -627 79 C12P -4594 -627
30 VCOM -8024 -627 80 C12P -4524 -627
31 VCOM -7954 -627 81 C12P -4454 -627
32 VCOM -7884 -627 82 C12P -4384 -627
33 VCOM -7814 -627 83 C12M -4314 -627
34 VCOM -7744 -627 84 C12M -4244 -627
35 DUMMYR1 -7674 -627 85 C12M -4174 -627
36 DUMMYR2 -7604 -627 86 C12M -4104 -627
37 VGH -7534 -627 87 C12M -4034 -627
38 VGH -7464 -627 88 C12M -3964 -627
39 VGH -7394 -627 89 C31P -3894 -627
40 VGH -7324 -627 90 C31P -3824 -627
41 C21P -7254 -627 91 C31P -3754 -627
42 C21P -7184 -627 92 C31P -3684 -627
43 C21M -7114 -627 93 C31P -3614 -627
44 C21M -7044 -627 94 C31P -3544 -627
45 C22P -6974 -627 95 C31M -3474 -627
46 C22P -6904 -627 96 C31M -3404 -627
47 C22M -6834 -627 97 C31M -3334 -627
48 C22M -6764 -627 98 C31M -3264 -627
49 C23P -6694 -627 99 C31M -3194 -627
50 C23P -6624 -627 100 C31M -3124 -627
TOMATO LSI Inc. 144

Ver .1.0

101 VCL -3054 -627 151 VCCL 446 -627
102 VCL -2984 -627 152 VCCL 516 -627
103 VCL -2914 -627 153 VCCL 586 -627
104 VCL -2844 -627 154 VCCL 656 -627
105 VCL -2774 -627 155 VCCL 726 -627
106 VCL -2704 -627 156 VCCL 796 -627
107 VREG1 -2634 -627 157 VSS1 866 -627
108 VREG1 -2564 -627 158 VSS1 936 -627
109 VREG1 -2494 -627 159 VSS1 1006 -627
110 VREG1 -2424 -627 160 VSS1 1076 -627
111 VREG2 -2354 -627 161 VSS1 1146 -627
112 VREG2 -2284 -627 162 VSS1 1216 -627
113 VREG2 -2214 -627 163 VSS1 1286 -627
114 VREG2 -2144 -627 164 VSS1 1356 -627
115 VREG2 -2074 -627 165 VSS1 1426 -627
116 VREG2 -2004 -627 166 VSS1 1496 -627
117 VREG2 -1934 -627 167 VSS1 1566 -627
118 VREG2 -1864 -627 168 VSS1 1636 -627
119 VCIF -1794 -627 169 VSS1 1706 -627
120 VCIF -1724 -627 170 VSS2 1776 -627
121 VCI -1654 -627 171 VSS2 1846 -627
122 VCI -1584 -627 172 VSS2 1916 -627
123 VCI -1514 -627 173 VSS2 1986 -627
124 VCI -1444 -627 174 VSS3 2056 -627
125 VCI -1374 -627 175 VSS3 2126 -627
126 VCI -1304 -627 176 VSS3 2196 -627
127 VCI -1234 -627 177 VSS3 2266 -627
128 VCI -1164 -627 178 VSS4 2336 -627
129 VCI -1094 -627 179 VSS4 2406 -627
130 VCI -1024 -627 180 VSS5 2476 -627
131 VCI -954 -627 181 VSS5 2546 -627
132 VCI -884 -627 182 VSS5 2616 -627
133 VCI -814 -627 183 VSS5 2686 -627
134 VCI -744 -627 184 VSS5 2756 -627
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201 IOVCCDUM 3962 -627 251 VCOMR 7534 -627
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TOMATO LSI Inc. 146

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301 G24 10479 -246 351 G116 9828 619
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401 G216 8778 619 451 G316 7728 619
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501 S677 6678 619 551 S627 5628 619
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601 S577 4578 619 651 S527 3528 619
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650 S528 3549 479 700 S478 2499 479
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701 S477 2478 619 751 S427 1428 619
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TOMATO LSI Inc. 151

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801 S377 378 619 851 S330 -672 619
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901 S280 -1722 619 951 S230 -2772 619
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1001 S180 -3822 619 1051 S130 -4872 619
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1101 S80 -5922 619 1151 S30 -6972 619
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1113 S68 -6174 619 1163 S18 -7224 619
1114 S67 -6195 479 1164 S17 -7245 479
1115 S66 -6216 619 1165 S16 -7266 619
1116 S65 -6237 479 1166 S15 -7287 479
1117 S64 -6258 619 1167 S14 -7308 619
1118 S63 -6279 479 1168 S13 -7329 479
1119 S62 -6300 619 1169 S12 -7350 619
1120 S61 -6321 479 1170 S11 -7371 479
1121 S60 -6342 619 1171 S10 -7392 619
1122 S59 -6363 479 1172 S9 -7413 479
1123 S58 -6384 619 1173 S8 -7434 619
1124 S57 -6405 479 1174 S7 -7455 479
1125 S56 -6426 619 1175 S6 -7476 619
1126 S55 -6447 479 1176 S5 -7497 479
1127 S54 -6468 619 1177 S4 -7518 619
1128 S53 -6489 479 1178 S3 -7539 479
1129 S52 -6510 619 1179 S2 -7560 619
1130 S51 -6531 479 1180 S1 -7581 479
1131 S50 -6552 619 1181 DUMMY20 -7602 619
1132 S49 -6573 479 1182 DUMMY21 -7623 479
1133 S48 -6594 619 1183 DUMMY22 -7644 619
1134 S47 -6615 479 1184 DUMMY23 -7665 479
1135 S46 -6636 619 1185 G319 -7686 619
1136 S45 -6657 479 1186 G317 -7707 479
1137 S44 -6678 619 1187 G315 -7728 619
1138 S43 -6699 479 1188 G313 -7749 479
1139 S42 -6720 619 1189 G311 -7770 619
1140 S41 -6741 479 1190 G309 -7791 479
1141 S40 -6762 619 1191 G307 -7812 619
1142 S39 -6783 479 1192 G305 -7833 479
1143 S38 -6804 619 1193 G303 -7854 619
1144 S37 -6825 479 1194 G301 -7875 479
1145 S36 -6846 619 1195 G299 -7896 619
1146 S35 -6867 479 1196 G297 -7917 479
1147 S34 -6888 619 1197 G295 -7938 619
1148 S33 -6909 479 1198 G293 -7959 479
1149 S32 -6930 619 1199 G291 -7980 619
1150 S31 -6951 479 1200 G289 -8001 479
TOMATO LSI Inc. 155

Ver .1.0

1201 G287 -8022 619 1251 G187 -9072 619
1202 G285 -8043 479 1252 G185 -9093 479
1203 G283 -8064 619 1253 G183 -9114 619
1204 G281 -8085 479 1254 G181 -9135 479
1205 G279 -8106 619 1255 G179 -9156 619
1206 G277 -8127 479 1256 G177 -9177 479
1207 G275 -8148 619 1257 G175 -9198 619
1208 G273 -8169 479 1258 G173 -9219 479
1209 G271 -8190 619 1259 G171 -9240 619
1210 G269 -8211 479 1260 G169 -9261 479
1211 G267 -8232 619 1261 G167 -9282 619
1212 G265 -8253 479 1262 G165 -9303 479
1213 G263 -8274 619 1263 G163 -9324 619
1214 G261 -8295 479 1264 G161 -9345 479
1215 G259 -8316 619 1265 G159 -9366 619
1216 G257 -8337 479 1266 G157 -9387 479
1217 G255 -8358 619 1267 G155 -9408 619
1218 G253 -8379 479 1268 G153 -9429 479
1219 G251 -8400 619 1269 G151 -9450 619
1220 G249 -8421 479 1270 G149 -9471 479
1221 G247 -8442 619 1271 G147 -9492 619
1222 G245 -8463 479 1272 G145 -9513 479
1223 G243 -8484 619 1273 G143 -9534 619
1224 G241 -8505 479 1274 G141 -9555 479
1225 G239 -8526 619 1275 G139 -9576 619
1226 G237 -8547 479 1276 G137 -9597 479
1227 G235 -8568 619 1277 G135 -9618 619
1228 G233 -8589 479 1278 G133 -9639 479
1229 G231 -8610 619 1279 G131 -9660 619
1230 G229 -8631 479 1280 G129 -9681 479
1231 G227 -8652 619 1281 G127 -9702 619
1232 G225 -8673 479 1282 G125 -9723 479
1233 G223 -8694 619 1283 G123 -9744 619
1234 G221 -8715 479 1284 G121 -9765 479
1235 G219 -8736 619 1285 G119 -9786 619
1236 G217 -8757 479 1286 G117 -9807 479
1237 G215 -8778 619 1287 G115 -9828 619
1238 G213 -8799 479 1288 G113 -9849 479
1239 G211 -8820 619 1289 G111 -9870 619
1240 G209 -8841 479 1290 G109 -9891 479
1241 G207 -8862 619 1291 G107 -9912 619
1242 G205 -8883 479 1292 G105 -9933 479
1243 G203 -8904 619 1293 G103 -9954 619
1244 G201 -8925 479 1294 G101 -9975 479
1245 G199 -8946 619 1295 G99 -9996 619
1246 G197 -8967 479 1296 G97 -10017 479
1247 G195 -8988 619 1297 G95 -10038 619
1248 G193 -9009 479 1298 G93 -10059 479
1249 G191 -9030 619 1299 G91 -10080 619
1250 G189 -9051 479 1300 G89 -10101 479
TOMATO LSI Inc. 156

Ver .1.0

Pad No Pad Name X Y
1301 G87 -10122 619
1302 G85 -10143 479
1303 G83 -10164 619
1304 G81 -10185 479
1305 G79 -10206 619
1306 DUMMY24 -10227 479
1307 DUMMY25 -10248 619
1308 DUMMY26 -10619 450
1309 DUMMY27 -10479 426
1310 G77 -10619 402
1311 G75 -10479 378
1312 G73 -10619 354
1313 G71 -10479 330
1314 G69 -10619 306
1315 G67 -10479 282
1316 G65 -10619 258
1317 G63 -10479 234
1318 G61 -10619 210
1319 G59 -10479 186
1320 G57 -10619 162
1321 G55 -10479 138
1322 G53 -10619 114
1323 G51 -10479 90
1324 G49 -10619 66
1325 G47 -10479 42
1326 G45 -10619 18
1327 G43 -10479 -6
1328 G41 -10619 -30
1329 G39 -10479 -54
1330 G37 -10619 -78
1331 G35 -10479 -102
1332 G33 -10619 -126
1333 G31 -10479 -150
1334 G29 -10619 -174
1335 G27 -10479 -198
1336 G25 -10619 -222
1337 G23 -10479 -246
1338 G21 -10619 -270
1339 G19 -10479 -294
1340 G17 -10619 -318
1341 G15 -10479 -342
1342 G13 -10619 -366
1343 G11 -10479 -390
1344 G9 -10619 -414
1345 G7 -10479 -438
1346 G5 -10619 -462
1347 G3 -10479 -486
1348 G1 -10619 -510
1349 DUMMY28 -10479 -534
1350 DUMMY29 -10619 -558
TOMATO LSI Inc. 157

Ver .1.0
TL1763 Specification Revision History
Version Content Date
0.0 1. New documentation. Jan. 25. 2006
0.1 1. Modification of Power setting flow (Insertion of COM setting) Jul. 06. 2006
1. Modify Gate Scan position (change max limit of scan start position)
0.2 Sep.12. 2006
2. Modify Scan mode setting (delete sm function)
1. Add Source Driver Control Instruction. Page68
2. Modify Display ON/OFF flow, Page129
1.0 3. Modify Standby, Sleep mode set/release. Page130 Dec. 1. 2006
4. Modify Chip Outline Dimensions of E,F,I,J items. Page140
5. Modify power seq and Input voltage range. Page 127, 6
TOMATO LSI Inc. 158

TL1763 - Spec V1 (1) (1) .0 - 200612

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LCD driver IC

Tomato LSI Inc.

TOMATO LSI Inc. 2

6-7. Source Driver Control Instruction…...............................................................................................67

TOMATO LSI Inc. 3

z Moving picture display interface

z On-chip display data RAM capacity

z High performance RAM writing function

z Various display function

TOMATO LSI Inc. 4

z Low power consumption architecture

z Power supply circuit for LCD operation

z Incorporated LCD power-supply start-up sequence

z Cst structure (Common VCOM method)

z H/W reset function

TOMATO LSI Inc. 5

TL1763 LCD Power Supply

1 Number of driver circuit for TFT source line 720

2 Structure for TFT-display retention volume Cst (Common to VCOM method)

S1 ~ S720 V0 to V63 grayscale level

VGH 7.4 to 21.52V

VGH - VGL 13.6 to 32V

Note 1) When internal logic regulator is in used.

TOMATO LSI Inc. 6

LCD Driving Circuit

LCD Driving Level Generation Circuit

TOMATO LSI Inc. 7

Power supply pin

Supply with the power supply voltage for interface pins

TOMATO LSI Inc. 8

Power supply pin

TOMATO LSI Inc. 9

TOMATO LSI Inc. 10

TOMATO LSI Inc. 11

TOMATO LSI Inc. 12

5-1. System interface

The TL1763 has eleven high-speed system interfaces : an 6800/8080-system 18-bit/16-bit/9-bit/8-bit/6-bit

Register selection (6-bit/8-bit/9-bit/16-bit/18-bit parallel interface)

Register selection (SPI)

TOMATO LSI Inc. 13

5-2. External Display Interface (RGB interface, VSYNC interface)

5-3. Address Counter (AC)

5-4. Graphic RAM (GRAM)

5-5. Gray Scale Voltage Generation Circuit

5-6. LCD Operating Voltage Circuit

5-7. Timing Generation Circuit

5-8. Oscillation Circuit

5-9. Source Driver Circuit

5-10. Gate Driver Circuit

5-11. Internal Logic Power Supply Regulator

TOMATO LSI Inc. 14

5-12. GRAM Address Map

Relation between GRAM address and Screen position (SS = 0, BGR = 0)

G1 G320 “00000”H “00001”H “00002”H “00003”H …… “000EC”H “000ED”H “000EE”H “000EF”H

TOMATO LSI Inc. 15

Relation between GRAM data and Display data (SS = 0, BGR = 0)

■ 68/80 mode 18-bit interface (one time transfer/pixel), TRI = *, DFM = *

Output pin S(3n+1) S(3n+2) S(3n+3)

■ 68/80 mode 16-bit interface (one time transfer/pixel) 1, TRI = 0, DFM = *

Output pin S(3n+1) S(3n+2) S(3n+3)

■ 68/80 mode 16-bit interface (two times transfer/pixel) 2, TRI = 1, DFM = 0

Output pin S(3n+1) S(3n+2) S(3n+3)

■ 68/80 mode 16-bit interface (two times transfer/pixel) 3, TRI = 1, DFM = 1

■ 68/80 mode 18-bit interface (one time transfer/pixel), TRI = , DFM =

■ 68/80 mode 9-bit interface (two times transfer/pixel), TRI = , DFM =

■ 68/80 mode 18-bit interface (one time transfer/pixel), TRI = , DFM =

■ 68/80 mode 9-bit interface (two times transfer/pixel), TRI = , DFM =

■ 18-bit RGB interface (one time transfers/pixel), TRI = , DFM =

■ 16-bit RGB interface (one time transfer/pixel), TRI = , DFM =

■ 6-bit RGB interface (three times transfer/pixel), TRI = , DFM =