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  • Clocks Using FSM

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    Lalithambika Patted
    10 views8 pages
    The document describes three finite state machine (FSM) implementations: 1. A divide by 2 clock that uses two states (S0 and S1) to toggle the output clock between 1 and 0. 2. A 33% duty cycle clock that uses three states (S0, S1, S2) to set the output clock to 1, 0, and 0 respectively in a repeating pattern. 3. A divide by 3 clock that combines two FSMs, one for each clock output, to divide the input clock by 3.

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    Fsm

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    clocks using FSM

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    The document describes three finite state machine (FSM) implementations: 1. A divide by 2 clock that uses two states (S0 and S1) to toggle the output clock between 1 and 0. 2. A 33% duty cycle clock that uses three states (S0, S1, S2) to set the output clock to 1, 0, and 0 respectively in a repeating pattern. 3. A divide by 3 clock that combines two FSMs, one for each clock output, to divide the input clock by 3.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    10 views8 pages

    Clocks Using FSM

    Uploaded by

    Lalithambika Patted
    The document describes three finite state machine (FSM) implementations: 1. A divide by 2 clock that uses two states (S0 and S1) to toggle the output clock between 1 and 0. 2. A 33% duty cycle clock that uses three states (S0, S1, S2) to set the output clock to 1, 0, and 0 respectively in a repeating pattern. 3. A divide by 3 clock that combines two FSMs, one for each clock output, to divide the input clock by 3.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 8

    @shraddha_pawankar Date: 1/8/2023

    Divide by 2 clock using FSM

    S0
    00 S1
    Clk_2=1 Clk_2=0

    // Divide by 2 clock using FSM//

    module clk_divide_2(clk,rst,clk_2);

    input clk,rst;
    output reg clk_2;

    parameter s0=0,s1=1;

    reg p_state,n_state;
    //-------------Memory block--------------//

    always@(posedge clk)
    if(!rst)
    p_state <= s0;
    else
    p_state <= n_state;
    //--------Next state block-------------------//
    @shraddha_pawankar Date: 1/8/2023

    always@(p_state)
    case(p_state)
    s0 : n_state = s1;
    s1 : n_state = s0;
    default : n_state = s0;
    endcase
    //--------output block-------------------//
    always@(p_state)
    case(p_state)
    s0 : clk_2=1;
    s1 : clk_2=0;
    default : clk_2 = 0;
    endcase
    endmodule

    https://www.edaplayground.com/x/tGD5

    33% duty cycle using FSM


    @shraddha_pawankar Date: 1/8/2023

    S0
    S1
    Clk_out =1
    Clk_out=0

    S2

    Clk_out=0

    Program:

    module clk_33_duty_cycle(clk,rst,clk_out);

    input clk,rst;
    output reg clk_out;
    reg[1:0] p_state,n_state;
    parameter s0=2'b00,s1=2'b01,s2=2'b10;

    //--------------Memory block-------------//

    always@(posedge clk)
    begin
    @shraddha_pawankar Date: 1/8/2023

    if(!rst)
    p_state <= s0;
    else

    p_state<= n_state;
    end
    //---------Next state block-----------//

    always@(p_state)

    begin
    case(p_state)
    s0: n_state = s1;
    s1: n_state = s2;
    s2: n_state = s0;

    default: n_state = s0;


    endcase
    end

    //-------output block-------------//

    always@(p_state)
    begin
    case(p_state)
    s0 : clk_out=1;
    s1 : clk_out=0;

    s2 : clk_out=0;
    default : clk_out=0;
    endcase
    end
    endmodule

    https://www.edaplayground.com/x/uLkr
    @shraddha_pawankar Date: 1/8/2023

    DIVIDE BY 3 CLOCK USING FSM

    S0
    Clk_1 = 1 S1
    clk_2=1 Clk_1 = 0
    clk_2=0

    S2

    Clk_1 = 0
    clk_2=0

    //Divide by 3 clock using FSM//


    module clk_divide_3(clk,rst,clk_3);
    input clk,rst;
    output reg clk_3;
    reg[1:0] p_state_1,n_state_1,p_state_2,n_state_2;

    reg clk_1,clk_2;
    parameter s0=2'b00,s1=2'b01,s2=2'b10;
    @shraddha_pawankar Date: 1/8/2023

    //------Memory block for clk_1---------//

    always@(posedge clk)

    begin
    if(!rst)
    p_state_1 <= s0;
    else
    p_state_1 <= n_state_1;

    end
    //--------define next state block for clk_1--------//

    always@(p_state_1)
    begin

    case(p_state_1)
    s0 : n_state_1 = s1;
    s1 : n_state_1 = s2;
    s2 : n_state_1 = s0;
    default : n_state_1 = s0;

    endcase
    end
    //------output block for clk_1------------//

    always@(p_state_1)

    begin
    case(p_state_1)
    s0 : clk_1 = 1;
    s1 : clk_1 = 0;
    s2 : clk_1 = 0;
    default: clk_1 = 0;
    @shraddha_pawankar Date: 1/8/2023

    endcase
    end
    //------Memory block for clk_2---------//

    always@(posedge clk)
    begin
    if(!rst)
    p_state_2 <= s0;
    else

    p_state_2 <= n_state_2;


    end
    //---------Next state block clk_2--------//
    always@(p_state_2)
    begin

    case(p_state_2)
    s0 : n_state_2 = s1;
    s1 : n_state_2 = s2;
    s2 : n_state_2 = s0;
    default : n_state_2 = s0;

    endcase
    end
    //------output block for clk_2------------//
    always@(p_state_2)
    begin

    case(p_state_2)
    s0 : clk_2 = 1;
    s1 : clk_2 = 0;
    s2 : clk_2 = 0;
    default : clk_2=0;
    endcase
    @shraddha_pawankar Date: 1/8/2023

    // combining clk_1 and clk_2


    assign clk_3 = clk_1 | clk_2;

    end
    endmodule

    https://www.edaplayground.com/x/rgxM

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