SystemVerilog for Verification

Lab: Simulate and Debug a 1-bit Adder

 2016-2017 Mentor Graphics Corporation

All rights reserved.

This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its
licensors and is subject to license terms. No part of this document may be photocopied, reproduced, translated,
distributed, disclosed or provided to third parties without the prior written consent of Mentor Graphics.
This document is for information and instruction purposes. Mentor Graphics reserves the right to make
changes in specifications and other information contained in this publication without prior notice, and the
reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made.

The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in
written agreements between Mentor Graphics and its customers. No representation or other affirmation of
fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor
Graphics whatsoever.

MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.

MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR
CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS)
ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT,
EVEN IF MENTOR GRAPHICS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

U.S. GOVERNMENT LICENSE RIGHTS: The software and documentation were developed entirely at
private expense and are commercial computer software and commercial computer software
documentation within the meaning of the applicable acquisition regulations. Accordingly, pursuant to FAR
48 CFR 12.212 and DFARS 48 CFR 227.7202, use, duplication and disclosure by or for the U.S.
Government or a U.S. Government subcontractor is subject solely to the terms and conditions set forth in
the license agreement provided with the software, except for provisions which are contrary to applicable
mandatory federal laws.

TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of
Mentor Graphics Corporation or other parties. No one is permitted to use these Marks without the prior
written consent of Mentor Graphics or the owner of the Mark, as applicable. The use herein of a third-
party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to
indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics’
trademarks may be viewed at: www.mentor.com/trademarks.

The registered trademark Linux® is used pursuant to a sublicense from LMI, the exclusive licensee of
Linus Torvalds, owner of the mark on a world-wide basis.

End-User License Agreement: You can print a copy of the End-User License Agreement from:
www.mentor.com/eula.

Mentor Graphics
Corporation
8005 S.W. Boeckman Road, Wilsonville, Orego 97070-7777
Telephone:
503.685.7000
Toll-Free Telephone: 800.592.2210
Website:
www.mentor.com
SupportNet: supportnet.mentor.com/

Send Feedback on Documentation: supportnet.mentor.com/doc_feedback_form

If you would like to view different waveforms generated in the three cases, there are three run*.do
files which compile, simulate and open the wave window for each simulation.
To use these .do files:
1. cd to the lab02_adder directory, and open the Questa GUI by typing: vsim
2. At the prompt in the transcript window of the GUI, type the following command to run the first
simulation:
QuestaSim> do run_rtl.do

This .do file includes the following QuestaSim commands which will be all executed when you
execute the above command:

if ![file exists work] { vlib work }

vlog -f run_rtl.f
vsim -voptargs=+acc top
do wave_rtl.do
run 100
run –continue

The wave window will then contain the simulation waveforms. There are three .do files. you can
run each of them without exiting the GUI, just type the following command after each run.
QuestaSim>quit -sim
• NOTE: The run_*.f command files in this lab use the +define+ technique to set the
appropriate macro name
• It is not necessary to modify the source code when using these command files

An alternative way to select between implementations is to name all the adder modules
just adder and then pick the RTL / gate / bad version by the files that you choose to
compile. This eliminates the need for macros.
The +acc switch that you use with the vopt command will allow you to look at internal
signals if you wish to.
If you would like to view the different waveforms generated in the three cases, there are
three run*.do files which compile, simulate and open the wave window for each
simulation.
To use these, cd to the lab02_adder directory, and open the Questa GUI by typing:
vsim
Then go to the transcript window of the GUI and type at the prompt as shown here
QuestaSim> do run_rtl.do
At the end of the simulation, do not exit the GUI, simply type
QuestaSim>quit -sim
If you would like to view the different waveforms generated in the three cases, there are
three run*.do files which compile, simulate and open the wave window for each
simulation.
To use these, follow the next directions. If the Questa GUI is not open, at the shell prompt
simply type vsim
If the Questa GUI is still open from the last section of the lab, go to the transcript window
and type at the prompt as shown here
QuestaSim> do run_gate.do
At the end of the simulation, do not exit the GUI, simply type
quit -sim
You can edit the source files in the QuestaSim source window. You will need to make sure
the file is not read only by right-clicking in the source window and unchecking the “Read
Only” option. You can also use gedit or vi editor from the Linux shell.

If you would like to view the different waveforms generated in the three cases, there are
three run*.do files which compile, simulate and open the wave window for each
simulation.
To use these .do files, follow the next directions. If the Questa GUI is not open, at the shell
prompt simply type vsim
If the Questa GUI is still open from the last section of the lab, go to the transcript window
and type at the prompt as shown here
QuestaSim> do run_bad.do
At the end of the simulation, do not exit the GUI, simply type
quit -sim
What’s happening…
 SystemVerilog has the implicit data type to aid in the creation of large netlist models
 Undeclared signal names in a netlist default to wire
 But, an error in a net name just becomes a new wire in the design, instead of a
compilation error
 The `default_nettype none directive turns off implicit data types
 PROS: Typographical errors become compilation errors
 CONS: Must declare every connection in a design (might be hundreds of
connections)
 Implicit nets can be re-enabled as shown below:
`default_nettype none // turn off implicit wires
module cpu (data_bus, address, reset);
... // all signals must have an explicit data type declared
endmodule
`default_nettype wire // re-enable implicit nets

Adding the –lint switch performs additional checks such as undeclared names, and run-
time array bounds checking.