Tessent® TestKompress®

Lab 2.2
Tessent TestKompress Integration Flows
Post-Synthesis Internal Logic Flow

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 Table of Contents
Before you Begin ...............................................................................................................................4

Lab 2.2 Tessent TestKompress Integration Flows – Post-Synthesis Internal Flow ..................................6
Exercise 1: Post-Synthesis Internal Logic Creation .................................................................................. 8

Appendix: Answers to Questions ...................................................................................................... 19

Lab 2.2 .................................................................................................................................................... 19

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 Before you Begin

If this is the first time you are launching this VM (Virtual Machine), you must download and extract
the lab data as described in the "Obtaining Lab Data section below.

Caution
Whenever you are using the VM for lab exercises and are finished with your session, please use the
"Disconnect" feature of the Desktop Viewer before the VM times out to preserve the data from one
session to the next. Failure to do so will remove the VM, and its contents.

If the VM was removed, you will be presented with a new VM requiring you to follow the download
and extract process. This allows you to "refresh" the lab data so you can go through the labs again
with a new database.

Setting Environment Variables

The environment uses bash and is ready to use for the labs with all needed environment variables
already setup.

Obtaining Lab Data

If the tk_data directory, with lab subdirectories, is located in the home directory (e.g. cd ~), please
proceed to the lab exercises as you have already set up the lab database on this VM.

If this is the first time you are starting a session for this VM, the tk_data directory will not be in the
home directory and you will need to download and extract it using the following instructions.

1. Double click on the Desktop icon Download_lab_data, . This launches a web browser.

2. On the resulting web page, select the file named tessent_tk_data_v2020.1_20200818.tgz,

3. In the resultant window, select the Download button, enable the Save File button, then select the
OK button to download the file.

Move the file in the Downloads directory to the home directory. If you are using the terminal
(Applications>Favorites>Terminal) you can use the following command:

mv ./Downloads/tessent_tk_data_v2020.1_20200818.tgz .

4. In a terminal window, extract the files from the compressed tar file using the command:

tar xzvf ./tessent_tk_data_v2020.1_20200818.tgz

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 You should now have a directory named tk_data in your $HOME directory. That directory contains all
the files you need to perform the exercises, in this learning path.

You are now ready to proceed with lab exercises.

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 Lab 2.2
Tessent TestKompress Integration
Flows – Post-Synthesis Internal Flow

This lab introduces the TestKompress post-synthesis internal logic creation flow.

In this lab, you start with a gate-level, non-scan netlist, insert scan chains using Tessent Scan, create
Tessent TestKompress (EDT) IP, and then generate and verify test patterns for both compression and
(optional) bypass modes.

Notice that this exercise has its own subdirectory and common directories are used for netlists,
generated files, and transcripts.

Introduction

TestKompress Logic Generation Flows

In this lab, you step through the internal post-synthesis flow using pre-defined scripts. During EDT IP
creation, a dofile containing scan chain, EDT setup and test procedure files are automatically generated
Tessent Shell checks out a Tessent TestKompress license for pattern generation in the same manner as
Tessent® FastScan™. The flow for creating compressed pattern uses the same commands as the
uncompressed pattern flow.

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Design
In this lab, you use a Verilog gate level netlist for the Microchip PIC 16CCC5X micro controller. You go
through the design flow from scan insertion to simulation of compressed (EDT) test patterns.

Compression Results
Compression is described in using two terms The compression ratio is equal to
<number of external scan channels> : <number of internal scan chains> . The data compression is
calculated using the results of report_scan_volume for non-compressed patterns, and dividing that by
the results of report_scan_volume for the compressed pattern set. The design used for this lab is very
small; therefore, the compression will be relatively small.

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 Tessent TestKompress Integration Flows
Post Synthesis Internal Logic Creation

Exercise 1: Post-Synthesis Internal Logic Creation

This exercise describes how to create and insert EDT IP into an existing hierarchy. The design can be a
module hierarchy, or a chip level with or without pads.

Background
In the external flow that we looked at in Lab 2.1, a new level of hierarchy was created, and the EDT IP
connections were connected to newly created port definitions.

In the internal flow, the EDT IP will be inserted into an existing level of hierarchy, and EDT IP connections
can be specified to existing logic (i.e. pipelines) and for existing ports/pads/pins. Figure 2.2-1 shows a
block diagram of the results of the internal flow at both a module and top-level implementation.

Figure 2.2-1. Internal Tessent TestKompress Flow

These examples show that the EDT IP can be specified to connect to existing logic and existing pads.

The internal flow generates and inserts the EDT IP into the module hierarchy. This usually results in
shorter synthesis run times. Refer to Figure 2.2-2 and Figure 2.2-3 for an illustration of the default
Tessent TestKompress-based EDT Logic insertion flow and the Synopsys DC-based EDT Logic insertion
flow and the.

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 Tessent TestKompress Integration Flows
Post Synthesis Internal Logic Creation

Figure 2.2-2. TestKompress-Based EDT Logic Insertion

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 Tessent TestKompress Integration Flows
Post Synthesis Internal Logic Creation

Figure 2.2-3. Synopsys DC-Based TestKompress Logic Insertion

Step 1: Scan Insertion

In this step, you insert 20 scan chains, and in addition, you will define connections to internal nodes for
scan enable and test enable. These signals will be connected to the existing pads.

Instructions
You will use the Tessent Scan on the non-scan synthesized netlist and insert 20 scan chains.

1. Go to the directory 1_insert_scan for this lab and review the files in this directory.:

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Post Synthesis Internal Logic Creation

$ cd $TK_LABS/Lab2.2/Exercise1/1_insert_scan
2. Examine the scan.do setup script. Notice how the internal nodes are specified for connection of
test enable. The scan chain inputs and outputs by default will be connected temporarily to new
input and output pins. These connections are removed during synthesis of the EDT IP, and
connected to the output of the decompressor and input of the compressor.

3. Use to invoke Tessent Shell and run the Tessent Scan dofile to insert scan chains.

$ ./insert_scan
4. Examine the transcript or logfile and verify that the netlist, dofile, and test procedure files were
written.

Step 2: Logic Creation Phase

In this step, you specify an internal logic location as well as pin names and connection to the I/O cells.

Instructions
1. Go to the directory 2_edt_ip for this lab:

$ cd $TK_LABS/Lab2.2/Exercise1/2_edt_ip
2. Invoke Tessent TestKompress:

$ tessent -shell -log ../logfiles/edt_ip_creation.log \

-replace

3. Set the context to dft -edt, read in the Verilog file and cell library file, and set the top of the
design.

SETUP> set_context dft -edt

SETUP> read_verilog ../design/gate_scan_20.v
SETUP> read_cell_library ../../../libs/tessent/adk.tcelllib
SETUP> set_current_design
4. Read the dofile created by Tessent Scan to define clocks, scan chains and read the test procedure
file & execute the Tcl procedures.

SETUP> dofile ../results/atpg.dofile

SETUP> tessent_scan_setup

5. Set up the EDT configuration:

SETUP> set_edt_options -channels 4 -location internal

This design has 20 scan chains. You set up the Tessent TestKompress logic with four scan
channels. The -location internal switch is used to indicate that the Tessent
TestKompress logic is placed internal to existing hierarchy.

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Post Synthesis Internal Logic Creation

6. From the command line, define the following pin naming:

Alternately, you can run a dofile to set up this pin naming:

SETUP> dofile edt_pin.do
Note

SETUP> set_edt_pins scan_en scan_en /ibuf72/Z

SETUP> set_edt_pins clock my_edt_clock /ibuf71/Z
SETUP> set_edt_pins update opa[0] /ibuf7/Z
SETUP> set_edt_pins bypass opa[1] /ibuf8/Z

SETUP> set_edt_pins input 1 opb[0] /ibuf39/Z

SETUP> set_edt_pins input 2 opb[1] /ibuf40/Z
SETUP> set_edt_pins input 3 opb[2] /ibuf41/Z
SETUP> set_edt_pins input 4 bidi1 /bidibuf1/data_out

SETUP> set_edt_pins output 1 empty_out1 /obuf41/A

SETUP> set_edt_pins output 2 inf /obuf33/A
SETUP> set_edt_pins output 3 qnan /obuf35/A
SETUP> set_edt_pins output 4 bidi2 /bidibuf2/data_in

Notice that two names are specified per pin: the top-level pin name, as well as the connection of
the pad where the internal signal is connected.

7. Verify the settings are correct:

SETUP> report_edt_pins
Correct any errors before moving on to the next step.

8. Run DRC and if it runs without errors the mode will be changed to ANALYSIS.

SETUP> check_design_rules
Notice the messages describing the EDT rules in the transcript.

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 Tessent TestKompress Integration Flows
Post Synthesis Internal Logic Creation

Figure 2.2-4. EDT Messages

You should be somewhat familiar with E5 and D5 violations from using Tessent FastScan.
However, if you are not familiar with DRC violations, you should look in the Tessent Shell
Reference Manual to find out what these violations are.

K rules are DRC rules specific to Tessent TestKompress. K rule violations are discussed in more
detail in another module.

9. Report on the K8 violation:

SETUP> report_drc_rules k8
What does the K8 rule report?
______________________________________________________________________________
____________________________________________

The warning about the bi-directional channel input pin warns us to ensure this pin is in input
mode when scan enable is active.

10. Verify the configuration and create the Tessent TestKompress logic:

ANALYSIS> report_edt_configurations
ANALYSIS> write_edt_files ../results/created -verilog \
-replace -insertion ts

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Post Synthesis Internal Logic Creation

The following files are written:

created_edt.v — Tessent TestKompress circuitry (Verilog RTL)

created_dc_script.scr — Design Compiler synthesis script

created_edt.dofile — Dofile for Tessent TestKompress (Pattern Generation Phase)

created_edt.testproc — Enhanced Procedure File (Pattern Generation Phase)

created_bypass.dofile — Dofile for bypass mode

created_bypass.testproc — Procedure File for bypass mode

created_edt.icl — EDT logic ICL

created_edt.pdl — EDT logic PDL

created_fpu_top_edt.tcd — The Design TCD file

Notice that the tool now sits at the INSERTION prompt.

11. Enter exit at the prompt to exit the tool.

INSERTION> exit

Step 3: Synthesize Tessent TestKompress Logic

This step discusses the generation of the synthesized netlist:

created_edt_top_gate.v

Instructions
Although you do not synthesize the design in this step, you should understand what files are used in
synthesis and how they interact.

1. Go to the results directory for this lab:

$ cd $TK_LABS/Lab2.2/Exercise1/results
2. Examine the synthesis script created_dc_script.scr generated by Tessent TestKompress.

3. Verify that the synthesized netlist is available:

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Post Synthesis Internal Logic Creation

$ ls
$TK_LABS/Lab2.2/Exercise1/design/created_edt_top_gate.v
This netlist is used in the next step.

Step 4: Tessent TestKompress Pattern Generation Phase (ATPG)

Generate test patterns for the design with Tessent TestKompress logic.

Instructions
Use the same method used in Lab2.1 to generate test patterns for the design. You can use the dofile and
invocation script available in the directory for this step.

1. Go to the 4_edt_pattern directory.

$ cd $TK_LABS/Lab2.2/Exercise1/4_edt_pattern
Examine the edt_pattern_gen.do file and note its similarities and differences to
edt_pattern_gen.do for Step 4 of Lab2.1/Exercise 1.

2. Invoke Tessent TestKompress, add faults, and create patterns.

$ tessent -shell -dofile edt_pattern_gen.do \

-log ../logfiles/edt_pattern_gen.log -replace
The edt_pattern_gen.do file invokes /results/created_edt.dofile, which adds the scan chains, pin
constraints and EDT settings.

3. Examine the log file ../logfiles/edt_pattern_gen.log.

After Tessent TestKompress has finished, open the log file or look at the transcript and answer
the following:

How many scan cells does the longest chain have? ____________________

How many memory elements were identified as INIT-X gates? __________

How many transparent latches (TLA) are there? ______________________

What is an E5 violation? _________________________________________

_____________________________________________________________

4. Examine the EDT configuration and fill in Table 2.2-1 and Table 2.2-2

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 Tessent TestKompress Integration Flows
Post Synthesis Internal Logic Creation

Table 2.2-1. EDT Configuration

Config. Value

IP version

Shift cycles

External scan channels

Internal scan chains

Masking bits

Decompressor size

Compactor type

Scan cells

Compression per pattern

Clocking

Compactor pipelining

Table 2.2-2. Scan Volume Report

Pattern type # test patterns # scan loads volume (cell-

loads/unloads)

chain_test

basic

total

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Step 5: Bypass Pattern Generation

Generate patterns for bypass mode. When Tessent Shell processes the dofile and test procedure file
that was created for the bypass mode, it will setup for non-EDT pattern generation.

Instructions
This is the same method used for the Bypass Mode Pattern Generation in Step 5 of Lab 2.1. Change to
the directory 5_bypass_pattern. You can use the dofile and invocation script available in the directory
for this step.

1. Go to the 5_bypass_pattern directory.

$ cd $TK_LABS/Lab2.2/Exercise1/5_bypass_pattern
2. Examine the script file run_tk_bypass. This script performs ATPG in bypass mode.

The file run_tk_bypass file invokes the dofile bypass_pattern_gen.do. Open this dofile and make
sure you understand what it does.

3. Run the script run_tk_bypass.

$ ./run_tk_bypass

4. Examine the ATPG results and fill in Table 2.2-3.

Scan Chains: ____________

Shift Cycles: ____________

Table 2.2-3. Scan Volume Report

Pattern type # test patterns scan loads volume (cell

loads/unloads)

Chain_test

basic

total

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Using the Total Volume data from Table 2.2-2 and 2.2-3 calculate the data compression for this design.
The equation to use is:

Data Volume Bypass / Data Volume EDT =___________

Step 6: Simulate EDT and Bypass Mode Test Patterns (Optional)

Normally, you would verify that the test patterns, the EDT circuitry, and the bypass circuitry operate
correctly, simulating all test patterns with full timing. For this exercise, the simulation files are setup,
and it is your option if you choose to perform, this step.

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Tessent TestKompress – Lab Answers

Appendix: Answers to Questions

Lab 2.2

Exercise 1: Post-Synthesis Internal Logic Creation

Step 2: Logic Creation Phase

Step 9

Q. What does the K8 rule report?

Warning: Bidirectional channel input or EDT control pin (/bidi1)

Step 4: Tessent TestKompress Pattern Generation Phase (ATPG)

Step 3

Q. How many scan cells does the longest chain have?

36

Q. How many memory elements were identified as INIT-X gates?

82

Q. How many transparent latches (TLA) are there?

21

Q. What is an E5 violation?

When the application places constrained states on constrained pins and binary states
on PIs and scan cells, X states must not propagate to an observable point. Failure to
satisfy this rule will result in the risk of X states propagating to an observable point.

Here there are 19 gates that may have an observable X-state.

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Tessent TestKompress – Lab Answers

Step 4

Table 2.2-1. EDT Configuration

Config. Value

IP version 7

Shift cycles 46

External scan channels 4

Internal scan chains 20

Masking bits 21

Decompressor size 16

Compactor type Xpress

Scan cells 715

Compression per pattern 3.91x

Clocking edge-sensitive

Compactor pipelining 1 stage

Table 2.2-2. Scan Volume Report

Pattern type # test patterns scan loads volume (cell

loads/unloads)

chain_test 12 12 2208

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Tessent TestKompress – Lab Answers

basic 173 173 31832

total 185 185 34040

Step 5: Bypass Pattern Generation

Step 4

Q. Scan Chains : 4

Q. Shift Cycles : 180

Table 2.2-3. Scan Volume Report

Pattern type # test patterns scan loads volume (cell

loads/unloads)

chain_test 1 1 720

basic 177 177 127440

total 178 178 128160

Data Volume Bypass / Data Volume EDT = 128160/34040= 3.76

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