Release Notes For ModelSim Altera 10.

1d

Nov 01 2012
Copyright 1991-2012 Mentor Graphics Corporation
All rights reserved.
This document contains information that is proprietary to Mentor
Graphics
Corporation. The original recipient of this document may duplicate this
document in whole or in part for internal business purposes only,
provided
that this entire notice appears in all copies. In duplicating any part
of
this document the recipient agrees to make every reasonable effort to
prevent the unauthorized use and distribution of the proprietary
information.
TRADEMARKS: The trademarks, logos and service marks ("Marks") used
herein
are the property of Mentor Graphics Corporation or other third parties.
No one is permitted to use these Marks without the prior written
consent
of Mentor Graphics or the respective third-party owner. The use herein
of a third-party Mark is not an attempt to indicate Mentor Graphics as
a
source of a product, but is intended to indicate a product from, or
associated with, a particular third party. The following are trademarks
of
of Mentor Graphics Corporation: Questa, ModelSim, JobSpy, and Signal
Spy.
A current list of Mentor Graphics trademarks may be viewed at
www.mentor.com/terms_conditions/trademarks.cfm.
End-User License Agreement: You can print a copy of the End-User
License
Agreement from: www.mentor.com/terms_conditions/enduser.cfm.
_______________________________________________________________________

* How to Get Support

ModelSim Altera is supported by Altera Corporation
+ World-Wide-Web Support
[1]http://www.altera.com/mySupport
_______________________________________________________________________

Index to Release Notes

* [2]Key Information
* [3]Compatibility Issues with Release 10.1d
* [4]User Interface Defects Repaired in 10.1d
* [5]SystemVerilog Defects Repaired in 10.1d
* [6]VHDL Defects Repaired in 10.1d
* [7]SystemC Defects Repaired in 10.1d
* [8]SVA/PSL Defects Repaired in 10.1d
* [9]Mixed Language Defects Repaired in 10.1d
* [10]Verification Management Defects Repaired in 10.1d
* [11]Defects repaired in WLF and VCD logging in 10.1d
* [12]User Interface Enhancements in 10.1d
* [13]SystemVerilog Enhancements in 10.1d
_______________________________________________________________________

Key Information
* The following lists the supported platforms:
 + win32aloem - Windows XP, Vista, Windows 7
+ sunos5aloem - Solaris 10 (Starting 10.1 release, support for
solaris has discontinued.)
+ hp700aloem - HP-UX 11
+ linuxaloem - RedHat 9 and higher, RedHat Enterprise Linux 3,
4, 5 and 6, SUSE Linux Enterprise Server 9.0, 9.1, 10 and 11.
(Starting 10.2 release, support for RedHat 3 and 4 and SUSE
9.0 and 9.1 will be discontinued)
* The following platform will be discontinued as of the 6.3 release:
+ HPUX Platform - hp700aloem
_______________________________________________________________________

Compatibility Issues with Release 10.1d

User Interface Defects Repaired

* dvt26930 - (results) The Expanded time mode was using too much
memory for long simulations and was crashing on 32 bit machines.
The crash is now fixed, and now we display an error message which
specifies we were not able to complete the operation and gives a
work around for the user to achieve the expanded time mode for the
region which the user is interested.
* dvt34048 - (results) There has been a 30K-character limit for
values returned in the list window or list report. The limit has
been lifted if the user uses the "-width" option to the [add list]
command.

SystemVerilog Defects Repaired

* dvt33341 - (results) A variable indexed multi-dimension packed
array within a for-loop produced incorrect results in some cases if
the array was a field of a packed structure.
* dvt34160 - (source,results) Fixed foreach issue where previously
defined variables were incorrectly being used as fixed index
values.

VHDL Defects Repaired

* [nodvtid] - (results) Commands registered with mti_AddCommand() and
mti_AddTclCommand() would not show related FLI calls when
-trace_foreign was in effect.
* dvt33957 - (source) -check_synthesis would generate an internal
error if the any of the name attributes, PATH_NAME, SIMPLE_NAME, or
INSTANCE_NAME, was used on a subelement of are record or array
object. Use of these attributes on subelements of records or arrays
in not LRM compliant. The use continues to be accepted by default
but a warning is now issued.

Mixed Language Defects Repaired

* dvt33217 - (results) The signal_force and signal_release operations
of the signal spy facility were not fully converted to the wire
model for force and release when the force command and the foreign
language interface (FLI) were converted. This release completes
that integration. If you need these signal spy operations to
operate in the same manner they did in the 10.1b and 10.1c
releases, you can run vsim with the -spy10_1b and the -spy10_c
command options respectively. Using the wire model for force means
that instead of giving the 3456 error about not being able to force
a port mapped at higher level and not doing the force, signal spy
force now uses the wire model used by the force command to find the
root signal or net and force it. This conversion removes the
restriction that bits of registers could not be forced in signal
 spy force.

Coverage Defects Repaired

* dvt33456 - (source) Empty task and function scopes are not stored
in UCDB now as those do not contribute any coverage.
* dvt33367 - (results) Using '//coverage on/off' pragma with '-item
s' option to exclude a continuous assignment statement would not
work. This has been fixed. This fix can change statement coverage
percentage if an existing '//coverage on/off -item s' pragma on a
continuous assignment statement was not getting applied earlier due
to this bug gets correctly applied now.

SystemVerilog Enhancements
* dvt16281 - (source) Changes have been made to how non-positive
replication multipliers are handled, in order to be compliant with
the LRM:
Warnings are no longer issued for 0, if the replication is inside a
concatenation.
It is a suppressible error (8602) if a multiplier of 0 is used for
a replication that is outside a concatenation.
It is a suppressible error (8607) if the multiplier is less than 0.
These same two errors, 8602 and 8607, are used in vsim, vlog and
vopt.

Verification Management Defects Repaired

* dvt33233 - (results) The ranktest "contrib" and "noncontrib"
information has been changed to report the original UCDB filename
of the test rather than the merge UCDB filename. In addition,
missing tests are now written out.

User Interface Enhancements

* [nodvtid] - (results) Formerly, users required the 'txanalysis'
license for viewing all transaction data. This has changed. The
license is needed only if trying to debug transactions in a
post-simulation WLF file using 'vsim -view', 'dataset open', etc.
Transactions in the current simulation are always debuggable solely
with the simulation and viewer license.

Defects repaired in WLF and VCD logging

* dvt32591 - (results) The wlf2vcd utility would output "$scope
module" instead of "$scope begin" for generate blocks when
converting WLF files to VCD. This "$scope begin" output now matches
the output from Questa when generating VCD directly from simulation
for these generates.
* dvt28967 - (results) When run on WLF files created from VHDL
designs, the wlf2vcd utility would output stdlogic values (i.e.
'U', '0', '1', 'X', 'Z', 'W', 'L', 'H', '-') into the output VCD
file instead of only '0', '1', 'x' or 'z'.
_______________________________________________________________________

User Interface Defects Repaired in 10.1d

* [nodvtid] - Wave balloon value was missing an element thanks to
NULL characters and ASCII radix. The original display was a grid of
characters, each row prefixed with the starting index of the first
character. This is a standard memory-debug display. In this case,
the NULL characters were eliminated from the display, causing a
misalignment of the data with the indexes. This has been corrected,
and unprintable characters are shown with '.' in the appropriate
positions.
 * [nodvtid] - When logging a design with many signals, if any
transactions were logged a large memory increase would occur. The
error has been corrected.
* dvt13796 - ModelSim could crash during 'profile clear' if the
design contained SystemC elements.
* dvt32218 - Add To Wave from Source window always adds to the end of
the Wave window. This issue is now fixed and items will be added at
position controlled by PrefWave(InsertMode).
* dvt32668 - Virtual Signal Builder will close unexpectedly after
using Drag and Drop. This issue is now fixed.
* dvt28159 - The add access flag dialog now works with VHDL design
units.
* dvt33418 - Compile dialog box sometimes put curly braces in the
File name text box. This issue is now fixed.
* dvt32698 - Drag and Drop into the last item in a Wave group is now
supported.
* dvt33999 - Under certain scenarios the wave windows grid and
timeline properties dialog would fail to display. The issue has
been fixed.
* dvt26930 - The Expanded time mode was using too much memory for
long simulations and was crashing on 32 bit machines. The crash is
now fixed, and now we display an error message which specifies we
were not able to complete the operation and gives a work around for
the user to achieve the expanded time mode for the region which the
user is interested.
* dvt33884 - Within the dataflow window, if the wave window
sub-window was also opened certain keyboard shortcuts would stop
working. These shortcuts were being overridden by the wave window.
This issue has been resolved.
* dvt34048 - There has been a 30K-character limit for values returned
in the list window or list report. The limit has been lifted if the
user uses the "-width" option to the [add list] command.
* dvt28990 - Creating a group when using Filter Contains box did not
work. This issue is now fixed.
_______________________________________________________________________

SystemVerilog Defects Repaired in 10.1d

* dvt32784 - Doing a cast from a net resulted in a memory leak.
* dvt33347 - Filename information in certain DPI related vlog/vopt
error messages was incorrect under certain circumstances.
* dvt33293 - Add more details in DPI error mesage vlog-7023 and
vopt-7023. The message number of the responsible warning/error
issued earlier are included. The following is an example:
** Warning: (vlog-7023) Cannot generate dpiheader file. Check the previous warn
ings or errors with the message numbers given below:
vlog-7016

* dvt33341 - A variable indexed multi-dimension packed array within a

for-loop produced incorrect results in some cases if the array was
a field of a packed structure.
* dvt33273 - An assignment to an out-of-bounds element of an indexed
vector or array within a for-loop corrupted simulation memory in
some cases, resulting in a crash or bad simulation values.
* dvt33422 - Fixed an internal error in compiler when Verilog system
function enable is part of the coverpoint expression.
* dvt33547 - vlog gave error when trying to reference a block inside
a task using dotted name.
* dvt34160 - Fixed foreach issue where previously defined variables
were incorrectly being used as fixed index values.
 * dvt34336 - Corrected a foreach issue where an error appeared when
both literals and variables are used to specify fixed indexes.
Example: foreach (my_array[0][my_var_fixed_index][loopvar1,
loopvar2])
* dvt33805 - SDF annotation to a timing check with a register as the
timing check condition failed. This has been fixed.
_______________________________________________________________________

VHDL Defects Repaired in 10.1d

* [nodvtid] - Commands registered with mti_AddCommand() and
mti_AddTclCommand() would not show related FLI calls when
-trace_foreign was in effect.
* [nodvtid] - An alias of a signal of a VHDL 2008 record type (not
fully constrained in the base type) would cause a simulator crash
if information about the alias was requested as happens for the
"show", "examine", and "describe" commands, as well as in several
of the GUI windows.
* dvt33393 - Elaboration crashes would occur if a VHDL architecture
is compiled with coverage, a SystemVerilog bind has a bind into
this VHDL architecture, and type is declared locally to the VHDL
architecture.
* dvt33455 - The simulator could crash while loading a design unit
containing a subprogram call with an output signal parameter that
is associated with an actual composite signal declared within an
uninstantiated package.
* dvt33519 - The simulator would crash while referencing a generic if
a conversion function applied to a port referenced a function
instance, an interface subprogram, or a function declared within a
package or subprogram instance.
* [nodvtid] - Unconstrained array in ports with an initialization
could rarely cause a random crash when instantiated with an array
actual larger than the one in the initialization.
* dvt33544 - In some cases, the simulator could terminate during
elaboration with the error "** Error: (vsim-3171) Could not find
machine code for 'xxx'" while loading an optimized design that
contains a recursively instantiated design unit, if the design unit
contains a conditional generate whose condition refers to generics.
* dvt33283 - A subprogram instance of a subprogram with a generic of
a record type that has an unconstrained subelement would sometimes
have that generic value be random garbage. This has been fixed.
* dvt33626 - Predefined attributes that retrieve information about
the subtype of the prefix would sometimes not be considered to be
locally static when they should have been. This could affect
related locally static determination causing, for example, a CASE
statement selector expression to be considered to be not locally
static (as it must be if it's of an array type) by mistake. This
has been fixed.
* dvt33950 - Instances of generic packages could not be referenced in
an external name. In prior releases external names that are package
relative names would report the package instance as not being a
package.
* dvt33957 - -check_synthesis would generate an internal error if the
any of the name attributes, PATH_NAME, SIMPLE_NAME, or
INSTANCE_NAME, was used on a subelement of are record or array
object. Use of these attributes on subelements of records or arrays
in not LRM compliant. The use continues to be accepted by default
but a warning is now issued.
* dvt33945 - Declaring a variable local to a subprogram, when the
variable's subtype is the 'SUBTYPE attribute of one of the
 subprogram's formal parameters, would cause a compiler crash. This
has been fixed.
* dvt33307 - Vopt will generate an internal error if a clocked
process is written
IF reset_condition THEN
statements
ELSE
IF some_function_call THEN
....

* dvt33392 - In rare instances logging a signal connected to a buffer

port would cause incorrect results in the port.
* dvt32540 - Fixed several problems with alias to external names.
Aliases in a subprogram could cause an internal error to be
generated on 64 bit platforms.
* dvt34435 - Driving a scalar element of a signal declared to be of a
constrained record subtype (where the base record type is not fully
constrained) would sometimes change the value of a different
element of the record. This has been fixed.
_______________________________________________________________________

SystemC Defects Repaired in 10.1d

* [nodvtid] - Fixed mti_GetTypeKind returning incorrect type_kind for
the sc_clock type.
_______________________________________________________________________

SVA/PSL Defects Repaired in 10.1d

* [nodvtid] - Fixed a bug where flags -assertdebug and -assertcover
were not getting restored while loading an elaborated design using
-load_elab option in vsim.
_______________________________________________________________________

Mixed Language Defects Repaired in 10.1d

* dvt33497 - Vopt would crash if a Verilog configuration contained a
design statement describing a VHDL design unit, but without a
library name.
* dvt33659 - An instance created in a VHDL architecture by a
SystemVerilog bind construct would not be found by a hierarchical
reference if the instance name was not all lower case.
* dvt33563 - A SystemVerilog module with a string parameter,
instantiating a VHDL entity with a generic of type STRING, and
associating that parameter with this generic, could sometimes
result in garbage characters in the VHDL generic value. This has
been fixed.
* dvt33490 - When -nodbgsym and -mixedsvvh were used together on the
same vlog/vcom command-line, -nodbgsym would get ignored and
debugging symbols would still be generated in the library for the
shared package. This has been fixed.
* dvt33217 - The signal_force and signal_release operations of the
signal spy facility were not fully converted to the wire model for
force and release when the force command and the foreign language
interface (FLI) were converted. This release completes that
integration. If you need these signal spy operations to operate in
the same manner they did in the 10.1b and 10.1c releases, you can
run vsim with the -spy10_1b and the -spy10_c command options
respectively. Using the wire model for force means that instead of
giving the 3456 error about not being able to force a port mapped
at higher level and not doing the force, signal spy force now uses
the wire model used by the force command to find the root signal or
 net and force it. This conversion removes the restriction that bits
of registers could not be forced in signal spy force.
* dvt34241 - Passing a hierarchical reference to a VHDL shared
variable of type STRING into a System Verilog task that would write
a string value (unsigned byte array actually) would sometimes
result in the VHDL string value being garbled on the receiving
side. This has been fixed.
_______________________________________________________________________

Verification Management Defects Repaired in 10.1d

* dvt33233 - The ranktest "contrib" and "noncontrib" information has
been changed to report the original UCDB filename of the test
rather than the merge UCDB filename. In addition, missing tests are
now written out.
_______________________________________________________________________

Defects repaired in WLF and VCD logging in 10.1d

* dvt32591 - The wlf2vcd utility would output "$scope module" instead
of "$scope begin" for generate blocks when converting WLF files to
VCD. This "$scope begin" output now matches the output from Questa
when generating VCD directly from simulation for these generates.
* dvt28967 - When run on WLF files created from VHDL designs, the
wlf2vcd utility would output stdlogic values (i.e. 'U', '0', '1',
'X', 'Z', 'W', 'L', 'H', '-') into the output VCD file instead of
only '0', '1', 'x' or 'z'.
* dvt34233 - Re-entrance into the Transaction engine is prevented to
avoid the corruption of transactions.
_______________________________________________________________________

User Interface Enhancements in 10.1d

* [nodvtid] - In vcom and vlog, with the -f filename option, the
filename file now treats a line beginning with the '#' character as
a comment. This in addition to other c-style comment delimiters
"//" and "/* ... */".
* [nodvtid] - Formerly, users required the 'txanalysis' license for
viewing all transaction data. This has changed. The license is
needed only if trying to debug transactions in a post-simulation
WLF file using 'vsim -view', 'dataset open', etc. Transactions in
the current simulation are always debuggable solely with the
simulation and viewer license.
* [nodvtid] - The "find" command, when given with the "instances"
argument, and when producing design unit name(s), has been enhanced
to provide the architecture name, when the new "-arch" switch is
present. When the design unit name is a VHDL entity, and when this
"-arch" switch is present, the applicable architecture name will be
present in the output of this command.
_______________________________________________________________________

SystemVerilog Enhancements in 10.1d

* dvt16281 - Changes have been made to how non-positive replication
multipliers are handled, in order to be compliant with the LRM:
Warnings are no longer issued for 0, if the replication is inside a
concatenation.
It is a suppressible error (8602) if a multiplier of 0 is used for
a replication that is outside a concatenation.
It is a suppressible error (8607) if the multiplier is less than 0.
These same two errors, 8602 and 8607, are used in vsim, vlog and
vopt.