Electrical & Electronics Engineering Institute, Paola Malta

Tutorial for P3 & M3 (Unit 35) – 2011:

1. The gates forming the following circuit operate as follows:

a. Gate (1) gives a logic 1 output only when both of its inputs are at logic 1.
b. Gate (2) gives a logic 0 output only when both of its inputs are at logic 0.
c. Gate (3) output is the inverse of Gate (1) output.

I. Define the names of the logic gates forming the circuit. For each gate, draw
the symbols in ANSI and IEC (BS3939) standards, the truth table, and write
down the Boolean expression. For each gate, consider inputs as A and B, and
the output as Y.

II. Draw the full circuit diagram using ANSI logic gates.

III. Evaluate the logic circuit drawn in step II. by producing a Boolean expression
and drawing a truth table.

IV. Minimize the truth table output using the Karnaugh Mapping Technique.
Write down the minimized equation resulting from the Karnaugh Map.

V. Draw the circuit of the minimized equation of step IV. using ANSI symbols.

VI. Convert the circuit of step V. into a circuit containing only NAND gates

VII. Convert the circuit of step V. into a circuit containing only NOR gates.

Digital Electronics Theory – NDE 1

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 Electrical & Electronics Engineering Institute, Paola Malta

2. The gates forming the following circuit operate as follows:

a. Gate (1) gives a logic 0 output only when both of its inputs are at logic 1
b. Gate (2) gives a logic 1 output when at least one of its inputs is at logic 1
c. Gate (3) gives a logic 1 output only when both of its inputs are at logic 1

I. Define the names of the logic gates forming the circuit. For each gate, draw
the symbols in ANSI and IEC (BS3939) standards, the truth table, and write
down the Boolean expression. For each gate, consider inputs as A and B, and
the output as Y.

II. Draw the full circuit diagram using ANSI logic gates.

III. Evaluate the logic circuit drawn in step II. by producing a Boolean expression
and drawing a truth table.

IV. Minimize the truth table output using the Karnaugh Mapping Technique.
Write down the minimized equation resulting from the Karnaugh Map.

V. Draw the circuit of the minimized equation of step IV. using ANSI symbols.

VI. Convert the circuit of step V. into a circuit containing only NAND gates

VII. Convert the circuit of step V. into a circuit containing only NOR gates.

Digital Electronics Theory – NDE 1

© Alfred Galea Page 2
 Electrical & Electronics Engineering Institute, Paola Malta

3. The gates forming the following circuit operate as follows:

a. Gate (1) gives a logic 0 output only when both of its inputs are at logic 0
b. Gate (2) gives a an output which is the opposite of the input
c. Gate (3) gives a logic 0 output only when both of its inputs are at logic 1
d. Gate (4) gives an output which the opposite of gate (3) output

I. Define the names of the logic gates forming the circuit. For each gate, draw
the symbols in ANSI and IEC (BS3939) standards, the truth table, and write
down the Boolean expression. For each gate, consider inputs as A and B, and
the output as Y.

II. Draw the full circuit diagram using ANSI logic gates.

III. Evaluate the logic circuit drawn in step II. by producing a Boolean expression
and drawing a truth table.

IV. Minimize the truth table output using the Karnaugh Mapping Technique.
Write down the minimized equation resulting from the Karnaugh Map.

V. Draw the circuit of the minimized equation of step IV. using ANSI symbols.

VI. Convert the circuit of step V. into a circuit containing only NAND gates

VII. Convert the circuit of step V. into a circuit containing only NOR gates.

Digital Electronics Theory – NDE 1

© Alfred Galea Page 3
 Electrical & Electronics Engineering Institute, Paola Malta

4. The gates forming the following circuit operate as follows:

a. Gate (1) gives a logic 1 output only when both of its inputs are at logic 0
b. Gate (2) gives a logic 1 output when the input is logic 0 or vice-versa.
c. Gate (3) gives a logic 0 output only when both of its inputs are at logic 1
d. Gate (4) gives a logic 1 output only when both of its inputs are at logic 1
e. Gate (5) gives a logic 1 output when at least one of its inputs is at logic 1.

I. Define the names of the logic gates forming the circuit. For each gate, draw
the symbols in ANSI and IEC (BS3939) standards, the truth table, and write
down the Boolean expression. For each gate, consider inputs as A and B, and
the output as Y.

II. Draw the full circuit diagram using ANSI logic gates.

III. Evaluate the logic circuit drawn in step II. by producing a Boolean expression
and drawing a truth table.

IV. Minimize the truth table output using the Karnaugh Mapping Technique.
Write down the minimized equation resulting from the Karnaugh Map.

V. Draw the circuit of the minimized equation of step IV. using ANSI symbols.

VI. Convert the circuit of step V. into a circuit containing only NAND gates

VII. Convert the circuit of step V. into a circuit containing only NOR gates.

Digital Electronics Theory – NDE 1

© Alfred Galea Page 4
 Electrical & Electronics Engineering Institute, Paola Malta

5. The gates forming the following circuit operate as follows:

a. Gate (1) gives a logic 1 output only when both of its inputs are at logic 0.
b. Gate (2) gives an output which is the opposite of the input.
c. Gate (3) gives a logic 1 output when the input is at logic 0, and vice-versa.
d. Gate (4) gives a logic 0 output only when both of its inputs are at logic 0
e. Gate (5) gives a logic 0 output when both of its inputs are at logic 1.
f. Gate (6) gives an output which is the opposite of that given by gate (5).

I. Define the names of the logic gates forming the circuit. For each gate, draw
the symbols in ANSI and IEC (BS3939) standards, the truth table, and write
down the Boolean expression. For each gate, consider inputs as A and B, and
the output as Y.

II. Draw the full circuit diagram using ANSI logic gates.

III. Evaluate the logic circuit drawn in step II. by producing a Boolean expression
and drawing a truth table.

IV. Minimize the truth table output using the Karnaugh Mapping Technique.
Write down the minimized equation resulting from the Karnaugh Map.

V. Draw the circuit of the minimized equation of step IV. using ANSI symbols.

VI. Convert the circuit of step V. into a circuit containing only NAND gates

VII. Convert the circuit of step V. into a circuit containing only NOR gates.

Digital Electronics Theory – NDE 1

© Alfred Galea Page 5