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Binder Cse Papers
Binder Cse Papers
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PA-1313 [Total No. of Pages : 2
ic-
[5925]-346
tat
S.E. (Robotics & Automation Engineering)
7s
CONTROL SYSTEM ENGINEERING
3:4
02 91
(2019 Pattern) (Semester - IV) (211509) (Theory)
3:4
0
31
Time : 2½ Hours] [Max. Marks : 70
7/0 13
Instructions to the candidates:
0
1) All questions are compulsory.
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.23 GP
8
C
23
5) Neat diagrams must be drawn wherever necessary.
ic-
16
tat
8.2
7s
.24
3:4
b) Sketch root Locus of unity feedback system with open loop transfer
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function G(S) = K/S ((S+1)((S+4).
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[9]
3:4
30
OR
31
01
[8]
1/2
8
ii) Investigate the stability of system with Characteristics equation
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.23
tat
8.2
7s
3:4
91
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[4]
30
[4]
01
02
OR
CE
80
Q4) a) Derive the expression for Resonant Frequency and Resonant Peak. [8]
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P.T.O.
49
[5925]-346 1
Q5) a) Define PLC? What are the necessity of PLC? Give advantages and
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disadvantages of PLC.
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[9]
ic-
b) Explain the selection criteria used for PLC. [9]
tat
OR
7s
3:4
Q6) a) Explain PLC interfacing with I/O devices? What are the different types
02 91
3:4
of command used in PLC. [9]
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31
b) State the sampling theorem explain the process of sampling and
7/0 13
quantization with waveform. [9]
0
1/2
.23 GP
Q7) a) Explain the procedure to design lead compensator using Bode diagram.
E
[8]
80
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C
23
b) Design a lead compensator for system with transfer function
ic-
G(S)=25/S(S+6) to meet following specifications. [10]
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tat
8.2
7s
i) mp = 5%
.24
3:4
ii) ts = 0.75 sec
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49
3:4
OR
30
31
Q8) a) Explain the procedure to design of lead compensator using root locus.
01
02
[6]
1/2
GP
7/0
b) Design lead compensator for the system with open loop transfer fucntion
CE
80
20
8
G(S )
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to meet followin specification. [12]
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S ( S 5)
ic-
16
tat
i) Steady state error for ramp input to be less than or equal to 0.025.
8.2
7s
3:4
91
49
3:4
30
31
01
02
1/2
GP
7/0
CE
80
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16
8.2
.24
49
[5925]-346 2
Total No. of Questions : 8] SEAT No. :
8
23
P715 [Total No. of Pages : 2
ic-
[5869]-387
tat
S.E. (Robotics & Automation Engineering)
6s
CONTROL SYSTEM ENGINEERING
0:5
02 91
(2019 Pattern) (Semester - IV)
8:3
0
20
Time : 2½ Hours] 3/0 13 [Max. Marks : 70
Instructions to the candidates:
0
6/2
.23 GP
1) All question are compulsory i.e. Solve Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q6, Q.7 or Q.8.
2) Assume suitable data if necessary.
E
82
8
3) Use of electronic pocket calculator is allowed.
C
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4) Neat diagrams must be drawn wherever necessary.
ic-
16
tat
8.2
6s
Q1) a) Find the range of K for stability unity feedback system with characteristic
.24
0:5
91
Equation. [9]
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8:3
G(S) = K/S (S+2) (S+4) (S+6).
30
20
Also define :
01
02
i) Pole
6/2
ii) Zero
GP
iii) S-plane
3/0
8
23
disadvantages of Routh’s criteria. [9]
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ic-
OR
16
tat
Q2) a) Draw root locus for the system G(S) H(S) = K/S (S+3) (S+6), obtain
8.2
[9]
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8:3
30
20
G H(S) = 1 / s3 (s+1)
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8.2
OR
.24
P.T.O.
49
Q4) a) Define phase margin and gain margin. Explain lead lag compensating
8
23
network. [8]
ic-
b) What are polar plots? Draw the polar plot for G (s) = 1 + as. [9]
tat
6s
0:5
Q5) a) Explain digital control system with block diagram. Enlist its advantages
02 91
8:3
and disadvantages. [8]
0
20
b) 3/0 13
Explain the architecture of PLC with neat diagram. [9]
0
6/2
.23 GP
OR
E
82
8
Q6) a) Explain input and output field devices used in PLC (any 8). [8]
C
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ic-
b) State sampling theorem, explain the process of sampling and digitization
16
tat
with waveform. [9]
8.2
6s
.24
0:5
91
Q7) a) Enlist phase lead design steps using bode diagram. [8]
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8:3
b) Design lead compensator for the system with OLTF, G(s) = 9/s (s+3) to
30
20
i) Steady state error for ramp input to be less than or equal to 0.05.
6/2
GP
OR
CE
82
Q8) a) What is compensator? Write the design steps of lead compensator using
8
23
root locus approach. [8]
.23
b) Design the lead compensator for a system with transfer function ic-
16
tat
G(s) = 2s/s (s+6) to meet following specifications [10]
8.2
6s
i) Mp = 5%
.24
0:5
8:3
30
20
01
02
6/2
GP
3/0
CE
82
.23
16
8.2
.24
49
[5869]-387 2