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Total No. of Questions : 8] SEAT No.

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PA-1313 [Total No. of Pages : 2

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S.E. (Robotics & Automation Engineering)

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CONTROL SYSTEM ENGINEERING

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(2019 Pattern) (Semester - IV) (211509) (Theory)

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Time : 2½ Hours] [Max. Marks : 70
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Instructions to the candidates:
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1) All questions are compulsory.
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2) Solve Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8.


3) Assume suitable data, if necessary.
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4) Use of electronic pocket calculator is allowed.


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5) Neat diagrams must be drawn wherever necessary.

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Q1) a) Give Properties of Root Locus. [8]

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b) Sketch root Locus of unity feedback system with open loop transfer
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function G(S) = K/S ((S+1)((S+4).
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[9]
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Q2) a) Explain Routh Hurwitz Stability Criteria.


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[8]
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b) i) The system with Characteristics Equation


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Q(S) = S3 + 2KS2 + (K+2)S + 4 = 0 find range of K for stability.[5]


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ii) Investigate the stability of system with Characteristics equation

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Q(S) = S5 + 5S4 + 10S3 + 10S2 + 5S + 1 = 0


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Q3) a) Sketch Polar Plot with Open loop transfer function.


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i) G(S)H(S)=1 – 2S/S(1 + 2S)


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[4]
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ii) G(S)H(S) = 1+ 2S/(S + 1) (1 – 2S)


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[4]
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b) Draw a typical frequency response of system and explain different


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frequency response specifications. [9]


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Q4) a) Derive the expression for Resonant Frequency and Resonant Peak. [8]
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b) For the system with open loop transfer functionG(S)H(S)=5/S(S+2)


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Sketch Nyquist plot and investigate stability. [9]


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P.T.O.
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Q5) a) Define PLC? What are the necessity of PLC? Give advantages and

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disadvantages of PLC.

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[9]

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b) Explain the selection criteria used for PLC. [9]

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Q6) a) Explain PLC interfacing with I/O devices? What are the different types

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of command used in PLC. [9]

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b) State the sampling theorem explain the process of sampling and
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quantization with waveform. [9]
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Q7) a) Explain the procedure to design lead compensator using Bode diagram.
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[8]
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b) Design a lead compensator for system with transfer function

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G(S)=25/S(S+6) to meet following specifications. [10]
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i) mp = 5%
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ii) ts = 0.75 sec
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OR
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Q8) a) Explain the procedure to design of lead compensator using root locus.
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b) Design lead compensator for the system with open loop transfer fucntion
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G(S ) 

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to meet followin specification. [12]
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S ( S  5)
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i) Steady state error for ramp input to be less than or equal to 0.025.
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ii) Phase Margin of at least 45º


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[5925]-346 2
Total No. of Questions : 8] SEAT No. :

8
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P715 [Total No. of Pages : 2

ic-
[5869]-387

tat
S.E. (Robotics & Automation Engineering)

6s
CONTROL SYSTEM ENGINEERING

0:5
02 91
(2019 Pattern) (Semester - IV)

8:3
0
20
Time : 2½ Hours] 3/0 13 [Max. Marks : 70
Instructions to the candidates:
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6/2
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1) All question are compulsory i.e. Solve Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q6, Q.7 or Q.8.
2) Assume suitable data if necessary.
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3) Use of electronic pocket calculator is allowed.
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4) Neat diagrams must be drawn wherever necessary.

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Q1) a) Find the range of K for stability unity feedback system with characteristic
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Equation. [9]
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G(S) = K/S (S+2) (S+4) (S+6).
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Also define :
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i) Pole
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ii) Zero
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iii) S-plane
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b) Explain Routh’s array with stability criteria, state advantages and


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disadvantages of Routh’s criteria. [9]
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Q2) a) Draw root locus for the system G(S) H(S) = K/S (S+3) (S+6), obtain
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the value of K When ε = 0.6 from root locus.


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[9]
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b) What is stability? Explain with diagram stable, unstable, marginally and


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conditionally stable system with locations of roots in s plane. [9]


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Q3) a) Define frequency response of a system & explain [8]


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i) Frequency Domain Analysis


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ii) Nyquist Stability Criteria


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b) Find the stability of following system using Nyquist plot. [9]


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G H(S) = 1 / s3 (s+1)
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Q4) a) Define phase margin and gain margin. Explain lead lag compensating

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network. [8]

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b) What are polar plots? Draw the polar plot for G (s) = 1 + as. [9]

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Q5) a) Explain digital control system with block diagram. Enlist its advantages

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and disadvantages. [8]

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Explain the architecture of PLC with neat diagram. [9]
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Q6) a) Explain input and output field devices used in PLC (any 8). [8]
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b) State sampling theorem, explain the process of sampling and digitization
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with waveform. [9]
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Q7) a) Enlist phase lead design steps using bode diagram. [8]
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b) Design lead compensator for the system with OLTF, G(s) = 9/s (s+3) to
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meet following Specifications. [10]


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i) Steady state error for ramp input to be less than or equal to 0.05.
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ii) Phase margin of at least 45 degree.


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Q8) a) What is compensator? Write the design steps of lead compensator using

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root locus approach. [8]
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b) Design the lead compensator for a system with transfer function ic-
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G(s) = 2s/s (s+6) to meet following specifications [10]
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i) Mp = 5%
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ii) Ts = 0.75 sec.


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