19ECE313 VLSI DESIGN

L15: INVERTERS _CMOS MULTIPLE

INPUTS-ANALYSIS
Dr Sreenidhi P R
Assistant Professor
ASE , Amrita Vishwavidyapeetham, Amritapuri
Objective
• Capacitance
• Transient analysis
• DC analysis
 Introduction
•

Capacitance for each input is proportional

Cu – unity
to its width . So Cin  W
capacitance
For inv, single input , hence Cg = 3 Cu
Cd = 3 Cu
NAND gate
• For input A => CgA =
2Cu+2Cu = 4 Cu
B => CgB = 4
Cu

For output ( consider the

drain capacitances attached
to output node) =>
2Cu+2Cu+2Cu = 6 Cu
NAND gate sizing
NAND gate sizing
NAND: Transient Analysis
NOR: Transient Analysis
NAND/NOR Performance
VTC NAND
VTC NAND
VTC NAND
VTC NAND
VTC NAND
Recap
•