A BRIEF REVIEW ON HARDWARE EFFICIENT
CASCADED INTEGRATOR COMB FILTERS
Akella Madhav1 , Hridya P.2 , Dasu Bharadwaj3 , M. Jaya Chandra4 , Returi Janaki Snigdha Roshni5 ,
Dr. Sreelekha K.R.6 , Dr. Ramesh B7
1
akella.madhav@outlook.com, 2 hridyap002@gmail.com, 3 bharadwaj.dasu@gmail.com, 4 jayachandramanchirala@gmail.com,
5
roshni.returi@gmail.com, 6 sreelekhakr@am.amrita.edu, 7 chidanandamrita@am.amrita.edu
Department of Electronics and Communication, Amrita Vishwa Vidyapeetham, Amritapuri, Kerala, India
Abstract—This article offers a summary of the approaches used
in the design of Cascaded-Integrator Comb (CIC) filters, focusing
on their implementation in Field Programmable Gate Arrays
(FPGAs). Because of its simplicity, computational efficiency,
flexibility for high-speed data handling, and features such as anti-
aliasing, interpolation, and noise reduction, CIC filters play an
essential role in multirate signal processing. This study examines
current research efforts aimed at improving the performance of
CIC filters, such as signal integrity, signal-to-noise ratio (SNR),
passband droop, and compensation designs. This paper also
portrays a comparative analysis of several parameters such as
adders, multipliers, registers utilized, and also Adders per output
sample (APOS) and minimum attenuation based on various
papers that have similar functionalities but vary in methodologies
employed, that affect the overall performance while implementing
in hardware.
Index Terms—CIC filter, Passband Droop, Compensator,
FPGA, Multirate Signal Processing.
I. I NTRODUCTION
IGNAL processing often deals with applications where
S the sample rate of the signals needs to be altered with
respect to the signal of interest in the application. As the need
for data conversion is increasing day by day, extraction of
the narrow band from the wide band sources and designing
narrow band filters with wideband signals are becoming more
decisive. For that purpose, multirate signal processing is essen-
tial in all those various real-time applications. Decimation and
interpolation are two types of multi-rate DSP, which involve
reducing and increasing the sampling rate. The conventional
way of implementing these interpolators and decimators is to
use a series of high-order FIR filters, which has the drawback
of having high hardware complexity due to the large number
of multiplications.
In 1981, Hogenauer [1] introduced a novel class of cost-
effective digital filters for decimation, known as Cascaded
Integrator Comb filters (CIC). These filters operate without
multipliers and do not require storage for filter coefficients.
CIC filters exhibit remarkable efficiency advantages over Fi-
nite Impulse Response (FIR) filters in terms of computation,
hardware resources, and reduced memory usage, albeit intro-
ducing latency through the integrator section. The primary
performance limitations of CIC filter response encompass high
passband droop, sharp transition bands, and large stopband
attenuation. To address these limitations in filter response,
additional combinations of filter blocks must be cascaded or
configured appropriately in conjunction with the basic CIC
filter, tailored to the specific application requirements.
The papers [3]–[5] have implemented modified design
methodologies for CIC decimation filters in high-performance
Analog to Digital Converters(ADCs). In the pursuit of lower
power consumption and reduced area utilization, [3] has
adopted a two-times frequency cascaded FIR algorithm and
CSD (Canonic Signed Digit) code filter coefficients, effec-
tively minimizing power consumption, reducing area require-
ments, and enhancing filter speed. Meanwhile, [5] has incor-
porated an FIR low-pass filter after each of the two-stage
decimation filters, effectively mitigating switching noise and
ensuring anti-aliasing. There is a clear imperative to enhance
the filter’s frequency response, and one pivotal approach in-
volves using sharpening techniques. The paper [6] introduced
a conventional design method grounded in amplitude change
functions, albeit with limitations that confine its application to
symmetric FIR filters featuring piecewise constant passbands
and stopbands. A combined structure of the CIC filter and
sharpening technique is presented in [6]–[8]. In [6], [17], a
fixed-coefficient filter is cascaded in place of a programmable-
coefficient filter to enhance throughput. In contrast, [8] cas-
cades a conventional CIC filter with a sharpened comb dec-
imator, employing polyphase decomposition to optimize the
structure for lower-rate operation. Both [7] and [9] focus on
replacing the programmable FIR filter in the second stage with
a fixed/constant coefficient FIR filter, an efficient approach
that, however, results in increased hardware resource con-
sumption. filter design, there’s a tradeoff between sharpening
the stopband and passband droop. To achieve a smoother
passband, one method is to cascade a sharpened CIC filter
with a compensator, as discussed in various studies ( [10], [11],
[16]). These approaches aim to design efficient compensators,
including multiplierless designs, tailored to specific applica-
tions. Additionally, innovative methods, such as a double-
sharpened decimation filter with a pre-droop compensator (
[19]), offer improved performance for multistandard wireless
applications. Other studies ( [20], [21], [22]) explore strategies
to enhance passband characteristics and stopband rejection
while considering specific application needs and constraints.
This paper investigates a range of design methodologies
targeted at improving various aspects of CIC filter design
and implementation, particularly focusing on real-time FPGA
applications. The latter section of the paper offers a concise
summary and comparative analysis of techniques used in
papers cited from [23] to [32]. The paper is structured as
follows: Section 1 introduces the concept of CIC filters and
outlines different design methodologies. Section III conducts
a comparative analysis of various parameters related to CIC
filter design and implementation. Finally, Section IV concludes
the paper.
II. CIC FILTER D ESIGN T ECHNIQUES
The fundamental CIC structure consists of three sequential
blocks: the integrator, comb, and rate change block. An
integrator in a CIC filter is essentially a digital accumulator.
It sums (or integrates) the input samples over time. The comb
section is a differencing operation. It subtracts a delayed ver-
sion of the signal from the current signal. The delay is typically
equal to the decimation factor in a decimation application. Fig.
1 illustrates the basic configuration of a CIC filter. During
the decimation process, the integrator stage accumulates and
averages M input samples to reduce the sample rate, while the
comb stage downsamples the signal by pruning every D output
sample, where M and D are integers. In contrast, during
interpolation, the integrator stage accumulates and replicates
M input samples to increase the sample rate, and the comb
stage selects every R output sample. The cascading of these
stages allows for achieving interpolation by a factor R. By
cascading multiple stages of basic CIC filters, wide range of
rate changes can be acheived with different combinations of
decimation or interpolation factors at each stage. This provides
flexibility that is crucial for systems that require dynamic rate
changes. Fig. 2 shows the comparision between CIC filter’s
response for different number of stages.
Fig. 1. Single Stage CIC filters used for decimation and interpolation [2]
The transfer fuction of the CIC filter is given by,
1 − z −RM N
H(z) = ( ) (1)
1 − Z −1
where, R is the decimation or interpolation ratio, M is the
number of samples per stage, and N is the order or the number
of comb-integrator pairs.
In reference [23], a three-stage cascaded structure for a digital
decimation filter is introduced, aiming to reduce the number of
cascaded digital filters by increasing the down-sample rate of
the CIC filter. This work introduces a sine compensation filter
as an alternative to the traditional FIR compensator to address
passband droop. Additionally, the multipliers in the half-band
filter are designed using time division multiplexing techniques
to optimize spectrum utilization efficiently. Comparison of
effective bits for different bandwidths (10kHz, 20kHz) and
downsampling rates (128, 256), as well as an evaluation of
multipliers, adders, and registers, is performed in conjunction
with references [3]–[5].
Fig. 2. Frequency response of N-stage CIC filter [37]
An application of the CIC filter is implemented in [24] in
which the authors presented a repeater design, which works
in accordance with a specific radio standard developed for
better communication among radio frequency repeaters in
Europe. From the work [24], it should be noted that con-
ventional FPGA-based repeaters have limitations in handling
multiple channels simultaneously. These designs necessitate
the utilization of numerous DSP slices and involve high
computational demands due to their low decimation rates.
To address the passband droop issue, Interpolated Second
Ordered Polynomials (ISOP) filters are cascaded with CIC
filters, effectively serving as compensators. This approach
offers greater efficiency in filter design, as it requires fewer
resources such as LUTs, LUT RAM, slice registers, BUFG,
and other vital parameters.
CIC filters used in real-time critical applications must
minimize the transition width between passband and stopband.
Hence, sharpening techniques are often applied to enhance
their efficiency in isolating specific frequency ranges while
attenuating others. In [25], a two-stage cascaded CIC deci-
mation filter is introduced, employing Kaiser-Hamming (KH)
sharpening in the first stage and Saramaki-Ritoniemi (SR)
sharpening with linear programming in the second stage.
A modified second-stage decimator structure is proposed to
improve the alias rejection of the first stage. In this methodol-
ogy, the first stage utilizes a KH-sharpened transfer function,
reducing the sampling rate by M1 and increasing the tangency
order near zero to N = 2 for improved alias rejection. The
second stage employs SR sharpening, reducing the sampling
rate by M2, and determines sharpening coefficients and taps
using linear programming in MATLAB, optimizing to min-
imize passband droop or ripple. The final decimation factor
is M = M1 * M2. The second-stage decimator structure is a
modified version of the first, increasing the order of tangency
to 4 in the KH structure and performing two passes of the
SR structure in the second stage. These changes enhance
alias rejection and stopband attenuation but increase passband
droop. Therefore, the first proposed structure is more suitable
for applications requiring minimized passband droop. FPGA
implementations of these structures exhibit improved slice
utilization and maximum operating frequencies. Performance
in ADCs and modulators is simulated, verified, and compared
to other existing architectures in these applications, consider-
ing passband droop and worst-case alias rejection relative to
references [6]–[12].
CIC filters play a vital role in digital receivers, particularly
in software-defined radio (SDR) and other RF applications.
SDR is a reconfigurable piece of digital electronic used in
transmitting and receiving RF signals. It’s a software where
digital-down counter (DDC) and digital up-counter (DUC) are
used for decimation and interpolation. The CIC filter shifts the
bandwidth of interest to baseband which allows for better fre-
quency selectivity and resolution without the interference from
other frequencies. An application based on SDR and receivers
in the fielf of communication is cited in [26]which presents
a filter structure suitable for digital wireless receivers, where
ADC sampling rates must align with specific communication
standards. The authors have designed, simulated, and imple-
mented multistage, multi-rate architectures with reduced cost
functions, exploring three key architectures: [a] Multi-Standard
Decimation Filter (MSDF), [b] a modified MSDF structure,
and [c] a polyphase CIC-based decimation filter. [a] is tailored
for WiMAX and GSM wireless communication specifications,
initially incorporating a CIC filter with a comb section to
meet multi-standard requirements. Subsequently, Half-Band
(HB) filters are employed to reduce the decimation rate further
and enhance performance in terms of passband droop and
noise rejection while reducing implementation costs. This
design typically consists of three filter stages and four HB
stages. [b] represents a modified structure where the first three
CIC filter stages of [a] are replaced with polynomial-based
CIC filters. For FPGA implementation, the digital equivalent
circuit includes register arrays and accumulators, with register
arrays used to realize delay-units in the filter design. In
[b], multiplication is achieved using Canonical Signed Digit
(CSD), an elegant method for implementing digital multipliers,
especially in cases with numerous multipliers. An adder at the
end sums all the products from CSD multipliers to produce the
final output. The third architecture is a simplified polyphase
implementation of [b], enabling parallel computation and
enhancing design speed.
CIC filters offer significant simplicity, efficiency, and recon-
figurability advantages, making them versatile across various
applications. However, they do encounter limitations that need
addressing. In reference [27], a common challenge faced
by CIC filters—namely, passband droop leading to spectral
distortion and aliasing—is tackled. The paper introduces a
two-stage comb decimator filter with improved magnitude
characteristics, explicitly focusing on enhancing passband per-
formance and attenuation in folding bands. Key filter specifica-
tions include reducing the filter rate, maintaining a low order,
ensuring a multiplier-less design, and enabling flexibility for
various decimation factor (M) values given a certain number
of stages (K). The authors propose a method that employs
five multiplier-less corrector filters, customized for different
K values (ranging from 1 to 5) and arbitrary M values, simul-
taneously reducing passband droop, enhancing attenuation in
odd folding bands, and operating at lower rates. To address
the sole drawback of the corrector filter, which is inadequate
even folding band attenuation, a cascading approach with a
modified structure is introduced. The paper concludes with a
comparative analysis, comparing the proposed method with
existing techniques, including compensator filters, sharpening
methods, and alternative CIC filter designs. The evaluation
covers parameters such as multipliers used, alias rejection, and
passband compensation relative to references [13]–[19]. Ulti-
mately, the paper underscores the advantages of the proposed
corrector filters, highlighting their simplicity, multiplier-less
design, and adaptability to various decimation factors.
Another notable contribution worth highlighting is presented
in [28], which focuses on utilizing polynomial sharpening
techniques to enhance the folding band response of CIC
filters. While sharpening the frequency response can lead to
undesired passband droop, this work addresses the issue by
cascading a symmetric FIR compensator filter with the SCIC
structure. This approach flattens the passband while preserving
the sharpened folding band characteristics. The compensator’s
design is guided by the maximally flat error criterion, aiming
for a flat and optimized passband response. Compensators in
filter design aim to rectify passband droop while retaining
improved folding band response characteristics. In this study,
the compensator is designed based on the maximally flat error
criterion, with coefficients derived from real values through
linear system equations. However, the authors demonstrate that
for SCIC filters with integer or Specific Power-of-Two (SPT)
polynomial coefficients and decimation factors expressed as
powers of two, the compensator coefficients can also be inte-
gers or SPT representable. The effectiveness in passband droop
reduction, computational complexity, and resource utilization
is compared with similar methodologies, as seen in references
[20]–[22]
In addition to addressing filter response parameters and
their improvements, it’s essential to carefully manage com-
plexity and resource utilization, minimizing them without
compromising the desired response. In [31], the authors in-
troduce a multiplier-less decimation filter designed to reduce
complexity, enhance aliasing rejection, and provide effective
passband compensation. This filter’s simplicity lies in its use of
symmetric polynomials, introducing four additional zeros into
specific comb folding bands, thereby widening these bands
for improved aliasing suppression. To reduce computational
complexity, polyphase decomposition is employed, shifting
filtering operations to a lower rate while maintaining desired
filtering characteristics, measured in terms of the number of
adders per output sample (APOS). Further passband quality
improvement is achieved by incorporating a compensator
operating at a reduced rate. The authors optimized compen-
sator parameters using particle swarm optimization (PSO)
and represented these parameters in a signed power-of-two
(SPT) format, enabling a multiplier-less design. This approach
offers flexibility to balance the number of required adders
with compensation quality. To validate their proposed filter’s
effectiveness, the authors conducted a comparative analysis
against recent methods in the literature, demonstrating superior
performance across these critical aspects.
In [32], the authors propose a CIC decimation structure
featuring the bit-pruning technique. This bit-pruning approach
significantly reduces the required bit period for the system and
optimizes the critical path period by subdividing the decimator
element. The modified CIC architecture is implemented using
Verilog HDL and validated on an FPGA board within a com-
munication receiver. The primary focus of this work centers on
a re-configurable CIC decimator with pruning characteristics
aimed at reducing hardware resources. In this context, the
FPGA-based CIC filter offers high flexibility, lower cost, and
superior overall performance compared to other DSP and
microprocessors. The study analyzes performance concerning
the number of stages and decimation factors. This three-stage
CIC decimator yields savings of up to 39.84% in slice registers
and 16.17% in power compared to similar architectures. Key
parameters, such as Adders per Output Sample (APOS), Min-
imum Attenuation in dB, and Maximum Passband Deviation
in dB, are also compared.
III. C OMPARATIVE A NALYSIS
Across these studies, the methodologies employed and the
results they presented offer compelling reasons to consider
tailored designs for specific applications. Expanding upon
this foundation, further modifications should be explored to
achieve optimal expected outcomes while minimizing dynamic
power and delay. In this section, a comparative evaluation
and analysis of critical parameters, including resource utiliza-
tion, minimum attenuation, power consumption, delay, LUT
count, and more, drawing from noteworthy prior researches
are conducted. Fig. 3 illustrates a comparison of resource
consumption in [3]–[5], [23]. It is evident that some archi-
tectures consume fewer multipliers, adders, and registers than
others. Reducing complexity and resource consumption in CIC
filter design is often about making trade-offs between perfor-
TABLE I
I MPLEMENTATION COMPLEXITY AND POWER COMPARISON
Parameter No. of slice registers Slice LUTs Power
Jayaprakasan V. et. al. [36] 418 764 0.041W
Han M et. al. [24] 256 263 0.030W
Datta D. et. al. [32] 154 136 0.036W
mance and efficiency. One of the primary reasons for reduced
complexity in [23] is the use of a novel sine compensation
filter, which replaces the conventional FIR compensation filter.
Another contributing factor is the utilization of multipliers in
the half-band filter with Time Division Multiplexing (TDM)
technology, further reducing complexity. Half-band filters have
the property that exactly half of their coefficients are zero
(except for the center tap). This symmetry means that only
half of the multipliers need to be implemented. This, in turn,
results in improved speed as there is lesser computational load.
A comparison is presented in the above Table I. In im-
plementing a CIC filter on an FPGA, the number of slice
registers and slice LUTs significantly affect the design and
performance. Slice registers are used to store the data at
various points along the pipeline. The number of slice registers
determines the depth of the pipeline, which affects the latency
of the filter. A deeper pipeline may result in lower latency
but also consumes more resources. Slice LUTs, on the other
hand, are used to implement the combinational logic functions
within the CIC filter, which include mathematical operations
required for filtering. The complexity of the CIC filter, such
as the number of filter stages, the decimation factor, and the
filter order, impacts the number of slice LUTs needed. A more
complex filter with higher decimation may require more LUTs.
The authors in [32] ensured that their architecture occupies
minimal area compared to the literature they reference. It is
observed that the more hardware-efficient choice among the
compared works is [32], which requires fewer slices and LUTs.
This reduction also leads to a decrease in IOBs. Furthermore,
the authors support their claim by demonstrating the imple-
mentation of the filter’s frequency responses in comparison to
Fig. 3. Resource utilization comparison
the other referenced works in the paper.
Fig. 4. Comparison of APOS and Min. attenuation
Fig. 4 presents a chart comparing Adder per Output Sample
(APOS) and minimum attenuation in [33]–[35] across various
values of R (decimation factor) and N (number of stages).
APOS is a vital metric to monitor when implementing a
CIC filter. Real-time architectures typically comprise multi-
ple stages of comb and integrator sections, each involving
adders for their operations. Monitoring APOS is essential
to keep track of the total number of adders required for
each output sample, a critical consideration in FPGA and
ASIC implementations with limited resources. Furthermore,
the number of APOS affects the filter implementation’s critical
path and timing constraints. The other parameter examined is
the minimum attenuation (in dB). From the chart, it is evident
that [35] offers an architecture with reduced complexity, which
is highly advantageous.
IV. C ONCLUSION
This article has provided a brief review of the various
methodologies employed in the design of CIC filters, with
a specific focus on their implementation using FPGA. The
choice of FPGA could be Virtex-7 board FPGA family as it is
Xilinx’s high performance device, consisting of 2 million logic
cells. This board can be chosen for DSP operations due to its
optimization for system performance and integration at 28nm,
which offers superior performance per watt, exceptional DSP
performance, and high I/O bandwidth. The exploration of cur-
rent research endeavors showcased in this study has shed light
on various aspects of CIC filter performance enhancement, in-
cluding complexity reduction, passband droop mitigation, and
compensator designs. Additionally, the paper has conducted a
comprehensive comparative analysis of multiple works across
several crucial parameters, contributing valuable insights to the
field of multirate signal processing and CIC filter optimization.
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