2010 Asia Pacific Conference on Circuits and Systems (APCCAS 2010)

6 - 9 December 2010, Kuala Lumpur, Malaysia

Space Vector PWM for PMSM Simulation using

Matlab Simulink
Anas Mohd Nazlee∗ , Nor Hisham Hamid† , Fawnizu Azmadi Hussin‡ and Noohul Basheer Zain Ali§
Electrical and Electronics Engineering Department
Universiti Teknologi PETRONAS
Tronoh, Perak Darul Ridzuan
Malaysia
∗ anas_g01319@utp.edu.my
† hishmid@petronas.com.my
‡ fawnizu@petronas.com.my
§ noohulbasheer_zainali@petronas.com.my

Abstract—Space Vector PWM (SVPWM) model is often built This paper presents high-level behavioral SVPWM model
based on high-level functions and verified based on the output that able to predict the usage of resources for hardware im-
of the inverter or the model of the electrical motor with best plementation. In most cases [2]–[5], conventional model does
possible accuracy. However, SVPWM implementation on digital
hardware such as Field Programmable Gate Array (FPGA) not reflect the true hardware requirement for implementation.
and Application-specific Integrated Circuit (ASIC) is constrained The proposed high-level behavioral model was developed to
by the limited resources and computation accuracy in these give early estimation of the resources used and provide early
digital hardware compared to the mathematical model. The paper analysis of the accuracy needed based on the number of
proposed a method that utilizes Matlab Simulink and Fixed-Point bits specified to be used. The information from the model
Toolbox to construct hardware-amenable SVPWM model. Using
the proposed model, it is possible to estimate the digital hardware could be used in drafting microarchitecture specification since
resources used and analyze the accuracy of the system before the model is built as the most accurate hardware amenable
the actual designing process takes place. The model has been mathematical functions.
simulated and verified with signal switching patterns and output
signals from the model of the electrical motor. Based on functional II. R EALIZATION OF SVPWM
comparisons, it was found that the outputs of the SVPWM model The concept of SVPWM for implementation is explained in
are almost identical to the digital hardware implementation.
this section. The mathematical equations model the behavior
Index Terms—Digital control, simulation model, field pro-
grammable gate arrays (FPGA), space vector pulse-width mod- of SVPWM, thus it is important to realize the role of each
ulation (SVPWM) equation.
A. SVPWM Control
I. I NTRODUCTION The basic principle of SVPWM is based on the eight switch
combinations for three-phase inverter. The switch combina-
Space Vector Pulse Width Modulation (SVPWM) is a form
tions can be represented as binary codes that corresponds
of Pulse Width Modulation (PWM) proposed in mid-1980s
to the top switch transistors (S1, S3 and S5) of the inverter
which was claimed to be more efficient compared to natural
as shown in Fig. 1. The combinations are used to represent
and regular sampled PWM [1]. SVPWM has been the subject
voltage vectors that are V~0 (000), V~1 (100), V~2 (110), V~3 (010),
research interest in further the efficiency, hence, many works
V~4 (011), V~5 (001), V~6 (101) and V~7 (111), where 1 indicate the
have been done especially in improving the algorithm and
upper switch (e.g. S1) is ’open’ while at the same time the
hardware implementation.
lower switch (e.g. S2) is ’close’.
For hardware implementation to have a better efficiency, the
Six of the voltage vectors (V~1 − V~6 ) are working states that
computation accuracy for the hardware has to be within the
form stationary vectors in the αβ frame and divide the plane
acceptable range to produce the needed output. The resources
in hardware is normally limited such as in Field Programmable
Gate Array (FPGA) and Application-specific Integrated Circuit
(ASIC), thus the usage of resources for the implementation
must be optimum. The hardware must be part of a complete
system that utilizes the efficiency of the hardware. SVPWM
is normally implemented as part of Field-Oriented Control
(FOC) to efficiently control the PMSM based on the reference
speed. Before the SVPWM is implemented in hardware,
simulation is done to understand the behavioral model. Fig. 1. Switches configuration of three-phase inverter
 2010 Asia Pacific Conference on Circuits and Systems (APCCAS 2010)
6 - 9 December 2010, Kuala Lumpur, Malaysia

C. SVPWM Dwelling Time Calculation

~ is derived based on the stationary
As explained in II-A, Vref
voltage vectors that are adjacent (V~k and V
~k+1 ) to the Vref
~ .
The dwelling time for the voltage vectors are computed based
~ angle (θ) with respect to the α axis and the sector
on the Vref
~ resides at the given time. The angle, θ is defined
in which Vref
in trigonometric function as
Vβ
θ = tan−1 ( ) (4)
Vα
The angle value is used to determine the sector (k) in which
~ is located at the given time. The values |V
Vref ~ref |, θ and k
Fig. 2. Voltage vectors and sectors in αβ frame
are then used to calculate the dwelling time for the voltage
vectors in each sector. The dwelling time can be evaluated
using the equations:
 
into six sectors with each having an angle of 60 degree, while k k
two of the voltage vectors (V~0 and V~7 ) are zero states and TV~k = C · sin π · cos θ − cos π · sin θ (5)
3 3
considered as null vectors situated at the origin of the plane.
Based on the stationary vectors and null vectors, a reference  
~ ) is formed as shown in Fig. 2 using geometry k−1 k−1
vector (Vref TV~k+1 = C· − cos θ · sin π + sin θ · cos π (6)
3 3
summation and can be expressed mathematically as
TV~k TV~k+1 TV~0 ,V~7 = TS − TV~k − TV~k+1 (7)
~ref =
V ~k +
V ~k+1
V (1)
TS TS
√
~ref | · TS
3 · |V
~k is selected
where in (1), TV~k is the time for which the vector V C= (8)
VDC
(referred as ’dwelling time’), k + 1 is referred as the next
voltage vector and TS is the switching period. The switches The dwelling times calculated based on (5), (6) and (7) are
of the inverter are then controlled according to the voltage applied to the switches to produce SVPWM switching patterns
vector at the given time with respect to the switching period. based on the sector [1] as shown in Table I. The switching
time is arranged according to the first half of the switching
B. Balanced Three-phase to Stationary Reference Frame period (TS /2) with the other half as the reflection forming
symmetrical pattern.
In SVPWM, αβ frame is used instead of the three-phase
axis a − b − c as shown in Fig. 2. The transformation involved III. P ROPOSED HIGH - LEVEL BEHAVIORAL SVPWM
is known as the Clarke Transformation. For balanced three- MODEL
phase system, the sum of the three currents (ia , ib and ic ) In order to construct a simulation model for hardware
adds up to zero since the loads do not have a neutral return implementation, the proposed model has to be functional and
path thus it is possible to project a reference frame rather than suited as a hardware reference model. The components have to
using the a − b − c axes as reference. In the case of the αβ be compatible as to describe the digital hardware itself such as
frame is stationary, the projection of the phase a axis forms the inputs, outputs, global clock pulses, storages, arithmetic logic
reference α axis and the second axis (β) is defined as being operations, datapath, and control unit.
orthogonal to the α axis. The transformation is represented as A conventional model is built based on [6] as a reference

va
 platform. The conventional model is constructed in modular
1 1 #
1 − −
" # "
Vα 2 2 2 form for it to be replaced module-by-module with the proposed
= · √ √ ·  vb  (2)
 
Vβ 3 0 3
− 3 model and for debugging purposes. The proposed model of
2 2 vc SVPWM shown as in Fig. 3 consists of a few modules:
• Coefficient module is used to compute C as in (8).
The value of Vα and Vβ becomes the input for the SVPWM • Triangle Wave Generator module is used to generate
in dwelling time calculation. The voltage inputs (Vα and Vβ ) symmetrical triangle signal as reference based on global
are normally required to compute the scalar value of reference clock and counters.
~ref | using the formula
voltage, |V • Trigonometric Function module is a trigonometric mod-
ule based on either Look-Up Table (LUT) method or
~ref | = 2 · Mi · V 2 + V 2
q
|V α β (3) Coordinate Rotation Digital Computer (CORDIC) algo-
3
rithm.
As the maximum value for |V ~ref | is 2 VDC and Mi is the • Dwelling Time Calculation module is a computation
3
modulation index to avoid overmodulation. module for (5), (6) and (7).
 2010 Asia Pacific Conference on Circuits and Systems (APCCAS 2010)
6 - 9 December 2010, Kuala Lumpur, Malaysia

TABLE I
S WITCHING T IME C ALCULATION FOR E ACH S ECTOR [1]

Sector, n Upper Switches (S1,S3,S5) Lower Switches (S2,S4,S6)

S1 = TV~ + TV~ + TV~ /2 S2 = TV~ /2

1 2 7 0

1 S3 = TV~ + TV~ /2 S4 = TV~ /2 + TV~

2 7 0 1

S5 = TV~ /2 S6 = TV~ /2 + TV~ + TV~ Fig. 4. Simulation model of Coefficient block

7 0 1 2

S1 = TV~ + TV~ /2 S2 = TV~ /2 + TV~

2 7 0 3

2 S3 = TV~ + TV~ + TV~ /2 S4 = TV~ /2

3 2 7 0 to estimate the accuracy needed for the design. An example
S5 = TV~ /2
7
S6 = TV~ /2 + TV~ + TV~
0 3 2
of one of the modules is illustrated in Fig. 4.
S1 = TV~ /2 S2 = TV~ /2 + TV~ + TV~ All the blocks in Fig. 4 have output attribute based on the
7 0 3 4
Fixed-Point Toolbox. The numbers of bits that are specified
3 S3 = TV~ + TV~ + TV~ /2 S4 = TV~ /2 in the fixed-point format are word length and fraction length.
3 4 7 0

S5 = TV~ + TV~ /2 S6 = TV~ /2 + TV~ The computation is then constrained to the specified fixed-
4 7 0 3
point format. The module is built with discrete mathematical
S1 = TV~ /2 S2 = TV~ /2 + TV~ + TV~ operators to estimate the resources used at the given time.
7 0 5 4

4 S3 = TV~ + TV~ /2 S4 = TV~ /2 + TV~

After all of the modules are configured with the same output
4 7 0 5
attribute, the functionality of the model is then tested with
S5 = TV~ + TV~ + TV~ /2 S6 = TV~ /2 specific configuration to the system.
5 4 7 0

S1 = TV~ + TV~ /2 S2 = TV~ /2 + TV~ The functionality of the proposed model is validated in
6 7 0 5
Field-Oriented Control (FOC) system. The input of the FOC
5 S3 = TV~ /2 S4 = TV~ /2 + TV~ + TV~
7 0 5 6 system is the speed reference for the motor in rotation per
S5 = TV~ + TV~ + TV~ /2 S6 = TV~ /2 minute (rpm) and the PMSM model used is based on Matlab
5 6 7 0
Simulink preset. The FOC model and SVPWM model are
S1 = TV~ + TV~ + TV~ /2 S2 = TV~ /2 configured according to the variables:
1 6 7 0

6 S3 = TV~ /2 S4 = TV~ /2 + TV~ + TV~

7 0
S5 = TV~ + TV~ /2
6 7
S6 = TV~ + TV~ /2
1 0
• Switching Time module implemented equation as in Table
I with triangle wave signal as reference.
The proposed model make use of Matlab Fixed-Point Tool-
box to format the output of computation as fixed-point with the
specified number of bits. In the case of SVPWM, the number
of bits determines the accuracy of dwelling time calculation.
The proposed model is constructed as such for the developer
1 6 • Speed reference, ωref = 3000 rpm
• PMSM preset model = 01: 0.8 Nm 300 Vdc 3000 rpm
• Load torque, Tm = 0 Nm
• Global clock frequency, FCLK = 50 MHz
• Switching frequency, FS = 10 KHz
• Modulation index, Mi = 0.6
• Voltage supply, VDC = 300 V
• Fraction length = 16 bits
The results of the simulation are observed and recorded using
the component Scope in Matlab Simulink. The detail of the
results are presented and discussed further in the Section IV.

Fig. 3. Simulation model of SVPWM

 2010 Asia Pacific Conference on Circuits and Systems (APCCAS 2010)
Fig. 5. (a)SVPWM signal switching pattern (b)PMSM model output
IV. R ESULTS AND D ISCUSSIONS
The proposed model is verified based on the output of
the SVPWM signal switching pattern, stator currents, rotation
speed and electromechanical torque as shown in Fig. 5. In
Fig. III, the Scope output has displayed from the top triangle
reference signal, signals to the upper switches (S1, S3 and S5)
and at the bottom is the sector in which V ~ref located. While
in Fig. III, the Scope output has displayed from the top stator
currents, rotation speed and at the bottom is electromechanical
torque.
As explained earlier in Section II-A, the voltage vectors
correspond to a switch combination and the value 1 indicates
the switch is open or in other word turned off. The switches
in ’Universal Bridge’ component in Simulink are turned off
by sending a low signal or logical 0. As shown in Fig. III,
the switches timing is dependent on the triangle wave signal.
Whenever the value of the triangle wave counter more than
the value of calculated switch time, the signal for the switch is
changed from high to low. The signal generated is according
to the respective sector.
The stator currents in Fig. III shows a coarse sinusoidal
waveform as a result from a system with no filter to counteract
the PWM switching feedback. It is also affected by the limited
accuracy of the fixed-point format in the SVPWM computa-
tion. This is proven as the digital design model computed the
value 3.4641e − 004 for the dwelling time as 3.3570e − 004
because of the limited fraction length in the fixed-point format.
Regardless, the system was able to produce a good response
with the ability to reach the reference speed in less than 0.005
second. The electromechanical torque remained at zero as
there is no load torque provided on the motor.
Based on the proposed model, the conventional algorithm
used the majority resources in multipliers and dividers for
the computation to maximize the adaptivity. Some of the
processes could be done in parallel, such as computing the
coefficient and running trigonometric function at the same
time. In the initial attempt in constructing the model, Triangle
Wave Generator module was built using up-down counter to
produce the triangle signal. As a result, the simulation took
a long time to finish. It is then replaced with up-down ramp
signal to provide much faster time in simulation.
6 - 9 December 2010, Kuala Lumpur, Malaysia
V. C ONCLUSION AND F UTURE W ORK
To maximize the usage of Matlab in modeling and simu-
lation, a high-level behavioral model is proposed to benefit
digital design simulation when implementing a theory. The
proposed model has been successfully constructed and veri-
fied according to the signal pattern and the motor response.
Even though the proposed model is a bit more tedious to
be built compared to the conventional model, the proposed
model provided more information and analysis for hardware
implementation compared to the conventional model based
on [6]. The simulation results provided early estimation and
expectation of the design, thus some of the issues in hardware
implementation might be solved earlier in the design phase.
The research would proceed with in-depth analysis of the
proposed model such as varying the fraction length to study the
effect on the proposed model, comparing the Total Harmonic
Distortion with the conventional model and the output with
the hardware implementation.
ACKNOWLEDGMENT
This research project is funded by Malaysia Ministry of Sci-
ence, Technology and Innovation through TechnoFund grant
TF1008C130.
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