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Abstract-In practice, SVPWM technique has the advantages of Take current CLARKE transforms for example, the
high utilization rate of DC voltage, small loss of FFT, and easy-to conversion process is as follows:
realize through Digital Controls, so this paper applied it to the
single-phase inverter controlled by DSC (digital controller). By
querying the data table, DSC generates single-phase SVPWM
signals with dead-time control, which modulate H-bridge inverter
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to output AC through the high voltage driver chip-IR2113. The
apply of the high-speed operation characteristic which make DSC i 0 is zero vector, after coordinate transformation, we can
be able to carry out PID feedback regulation and the eQEP
(enhanced quadrature encoder pulse) which track and regulation calculate the reference voltage vector U in the a-� coordinate
out
the phase, make the system basically achieve the purpose of the
according to three-phase voltage, and its amplitude is the
instantaneous steady-state regulation of self-adaptive.
effective value of the line voltage in the a-� coordinates.
Keywords-SVPWM; Single-Phase Inverter; DSC; IR2113; In the three-phase inverter, SVPWM technique through the
CSA-IV; dead-time control appropriate combination of switching status of basic space
vector approximates the reference voltage U to simulate the
I. INTRODUCTION
out
and its uncontrolled feature is not conducive to the output of the duration of the closed state of the upper arm U x and lower
grid-connected inverter. Some products are also using SPWM
(sinusoidal pulse width modulation) to control output, but the arm U X+60 in the same-phase power switch.
high-frequency switching signal leads to the output voltage
with high frequency harmonics, and the inverter switches have Compared with three-phase inverter, single-phase bridge
great loss. inverter lacks a pair of power switches. vab is the output
To solve the above problem, the design will introduce single-phase AC power, a and b are two control signals on H
SVPWM (space vector pulse width modulation) technology bridge higher arm The following is shown by matrix form:
.
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U <I> is the output effective value; u ab is the instantaneous Under the same carrier frequency, single-phase SVPWM
modulation wave after switch-mode optimization is similar to
output voltage vector. SPWM waveform on the same frequency judging from the
observed waveform, because SVPWM algorithm is the results
Take 0) t E [0, n] for example, we analyze the fitting
that SPWM phase modulation using a regular sampling method
formula of the single-phase voltage vector outputted by digital is added zero sequence, so they're roughly similar in the
controller. harmonic direction.
Three-phase inverter modulates output of three-phase In order to improve the stability of the system in bridge
voltage by the combination of any two pairs of power switches, inverter circuit (Figure 2), we use IR2113 chip to indirectly
while the single-phase bridge inverter by two independent drive power switch. IR2113 chip is a dedicated driver of high
power switches to modulates the output of one phase voltage, speed and high-voltage power-type MOSFET, IGBT, it has two
so the degree of freedom has been greatly improved. But the mutually independent high and low drive channels, using its
voltage output waveform of three-phase inverter are two pulses
with the same width which are symmetrical to the PWM cycle,
in practical applications in order to reduce loss of switching
devices in single-phase inverter bridge, we introduce switch
mode optimization, we combine two pulses in the same cycle
to eliminate the falling edge of the previous pulse, and the
rising edge of a later pulse. In the operation, T 1 = T l' To =
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high-voltage output can stability control the conduction and the program memory space to obtain the current pulse time. We
tum-off of FET in a high potential of the bridge arm. The set T to 200IlS, T a ' T b determine To' T l' eventually we
maximum drive voltage of IR2 113 is up to 600V, for a wide
range jump of DC voltage it has good adaptability. MOS uses modify the duty cycle of the output waveform to determine the
IRFS40N FET, the DC input resistance RGS is 77mfJ., and the effective value of voltage vector v ab ' It operates data loading
model under the same conditions has a smaller switching losses to compare registers (CMPA, CMPB) CMPA, CMPB of
which help to improve inverter efficiency. ePWM, and sets register TBPRD periodically on increasing or
We use CSA-IV (Programmable Hall sensor chip) detect reducing counting mode, Compared with the TBPRD by the
current. The chip is produced using conventional CMOS CMPA, when CMPA overflows, EPWMIA pins have level
technology, the ferromagnetic layer in its silicon chip, detects change accordingly to adjust the duty cycle of final output
electromagnetic signal, computes gain of magnetic flux, and pulse. In the end, single-phase SVPWM waveform was shown
outputs the analog voltage after amplification. When wiring, in Figure 6 (a). Take the first half cycle as an example to set
the source pins of two lower bridge arms MOSFET (Q2, Q4) main registers of the ePWM:
are grounded, copper line with 2.5mm width comes from the TBPRD=T/4
bottom of the chip (Figure 3). The voltage signal outputs by
differential form, which is enlarged by the differential amplifier CMPA= T 1/2 (6)
circuit composed by LM324, linked to ADCINBO pin of F2806 CMPB= TO=O
for analog-digital conversion to measure the DC current, then
according to step-up ,converted to AC-side current. The T1=Msinwt
method uses Hall Effect test large current flows through the
ground-side, without the need for opto-isolation and other Where, M (:S I) is the pulse width modulation, T 1 can be
measures; it helps reduce the cost and size. With this method gotten through querying the sine table burned on process
the accuracy of output current sampling theory can be achieved storage space of F2806.
lmA, the actual detection accuracy is steady SmA.
In order to prevent the break-over of two switches at the
same time of upper and lower arms with the same phase, the
system uses the programmable dead-time control unit
I contained by ePWM. The procedures is designed to set
DBCTL [OUT-MODE] control bit for output mode, and to
determine the edge delay processing of the output PWM signal.
To control the dead-time can prevent phenomenon of short
circuit caused by break-over at the same time and improve the
stability of the inverter.
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