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Design of Single-Phase Inverter controlled by DSC based on SVPWM technique

Ruian Liu Lei Wang Mimi Zhang Shengtao Ma


College of Physics and Electronic Information Science of Tianjin Normal University
Tianjin, China
e-mail: wdxylra@maiLtjnu.edu.cn

Abstract-In practice, SVPWM technique has the advantages of Take current CLARKE transforms for example, the
high utilization rate of DC voltage, small loss of FFT, and easy-to­ conversion process is as follows:
realize through Digital Controls, so this paper applied it to the
single-phase inverter controlled by DSC (digital controller). By
querying the data table, DSC generates single-phase SVPWM
signals with dead-time control, which modulate H-bridge inverter
[:i:o]=%[11�2 ���112 --;;112�2-[:ic�] ( 1)
to output AC through the high voltage driver chip-IR2113. The
apply of the high-speed operation characteristic which make DSC i 0 is zero vector, after coordinate transformation, we can
be able to carry out PID feedback regulation and the eQEP
(enhanced quadrature encoder pulse) which track and regulation calculate the reference voltage vector U in the a-� coordinate
out

the phase, make the system basically achieve the purpose of the
according to three-phase voltage, and its amplitude is the
instantaneous steady-state regulation of self-adaptive.
effective value of the line voltage in the a-� coordinates.
Keywords-SVPWM; Single-Phase Inverter; DSC; IR2113; In the three-phase inverter, SVPWM technique through the
CSA-IV; dead-time control appropriate combination of switching status of basic space
vector approximates the reference voltage U to simulate the
I. INTRODUCTION
out

output of sine wave. In practice, in one period (T) of a smaller


The inverter is the design which aims at the requirements of carrier PWM, the digital controller calculates the duration of
the grid-connected photovoltaic contravariant system, the switch-level generated by inverter, and the actual values are
system requires that low-voltage direct current ( 120r24V) obtained through the integral computation to be fitted to
produced by photovoltaic cells is transformed into a single­ average as the average reference voltage value.
phase 220V AC with the same frequency of the city grid. The
generated waveforms of existing small and medium-power -
1 fn+1)T Uout(t)d(t) =-(
1
T,ux + TPX+6o)
T T T (2)
inverter are mostly square waves or modified sine waves, so it
can not supply power for the inductive or capacitive loads and
precision instruments, it easily causes errors or even damage, U is the reference voltage, T I and T 2' respectively, is
out

and its uncontrolled feature is not conducive to the output of the duration of the closed state of the upper arm U x and lower
grid-connected inverter. Some products are also using SPWM
(sinusoidal pulse width modulation) to control output, but the arm U X+60 in the same-phase power switch.
high-frequency switching signal leads to the output voltage
with high frequency harmonics, and the inverter switches have Compared with three-phase inverter, single-phase bridge
great loss. inverter lacks a pair of power switches. vab is the output
To solve the above problem, the design will introduce single-phase AC power, a and b are two control signals on H
SVPWM (space vector pulse width modulation) technology bridge higher arm The following is shown by matrix form:
.

into the single-phase inverter controlled by DSC (digital signal


controller). SVPWM technique has the advantages of high
utilization rate of DC voltage, small loss of FFT, and easy-to­ (3)
realize through digital controls, which can effectively improve T
the conversion efficiency of the inverter and the effect of the Voltage vector v= (vab' V b
a) forms four discrete
output waveform. We use the PID algorithm and phase voltage vector in the uniaxial space, but the effective values of
detection to realize instantaneous adjustment of the system two voltage vectors are always zero. The process is similar to
output, and improve the inverter's real-time response capacity. three-phase SVPWM, single-phase SVPWM determines the
effective value of remaining two discrete voltage vectors to
II. ANALYSIS AND IMPLEMENTATION OF SINGLE-PHASE obtain the corresponding pulse voltage through the modulation
SPACE VECTOR PWM to PWM duty cycle of the two pairs of switches, and then we
will obtain the actual sine wave voltage after Integral filtering.
A. The principle ofsingle-phase SVPWM In order to analyze the space voltage vector, we specially
introduce line voltage reference form of single-phase sinusoidal
Single-phase SVPWM technology originates from the
power:
space vector control technology of three-phase motor. Three­
phase SVPWM becomes a two-phase orthogonal vectors by Uab =.J3uoJ)sin wt
transformation from three-phase A-B-C coordinate to a-� (4)
coordinate after CLARKE.

978-1-4244-6585-9/10/$26.00 ©2010 IEEE

649
U <I> is the output effective value; u ab is the instantaneous Under the same carrier frequency, single-phase SVPWM
modulation wave after switch-mode optimization is similar to
output voltage vector. SPWM waveform on the same frequency judging from the
observed waveform, because SVPWM algorithm is the results
Take 0) t E [0, n] for example, we analyze the fitting
that SPWM phase modulation using a regular sampling method
formula of the single-phase voltage vector outputted by digital is added zero sequence, so they're roughly similar in the
controller. harmonic direction.

r.J3U¢sinwtd(lOt) NVdctlToi -7;bl =


III. SYSTEM HARDWARE STRUCTURE
;=1 (5)
N is the step-up ratio of the high-frequency transformer in A. Digital Control Module
inverter, n is the pulse number of PWM within half cycle of The system uses TMS320F2806-type DSC (digital signal
AC, V de is expressed as input DC voltage, T ia and T ib are the controller) of the C2000 series of TI (Texas Instruments) as the
core of digital control, the DSC chip has a wealth of hardware
conduction time of two pairs of switches in each PWM cycle.
resources, their internal 20KB of RAM and 64KB of flash
space make the rurming speed up to 100MIPS. Compared to
B. Implementation and Improvement of Single-phase
DSP (digital signal processor) it has advantages of low cost,
SVPWM algorithm
small peripheral devices and more multi-function modules.
The timer in DSC can use the incremental and decrease
counting mode, a and b synchronously output bilateral The processor has eQEP (enhanced quadrature encoder
symmetrical waveforms. The PWM period (T) is fixed, by pulse) module, the inverter uses the integrated edge detection
unit to detect the phase and frequency of AC output. The
modifying the compare registers T a ' T b to determine the process is as follows: the secondary coil of the high-frequency
To' T l' which was shown on Figure 1 (a), eventually we step-up transformer produces high-frequency weak AC signals
modify the pulse duty cycle of output waveform to determine filtered by the LC circuit, becomes AC signal whose V p_p less
the effective value of voltage vector. than 3V by the sampling resistor divider, it is compared with
zero potential by LM393 (Voltage Comparator device) to
T.,t4 T,!2 T.,t2 T,/2 T.,t4 Io/2 T, Io/2 generate the pulse signal which is sent to the EQEPIA pin of
Tb /""- T V� F2806 for phase and frequency detection. Capture Timer
T• . . / i""" (QCTMR) runs according to the clock frequency signal, when
to capture the signal rising level (or falling level), the system
T / i"" will latch the value of timer to capture period register
(QCPRD), then reset capture timer and flag bit of QERSTS
b t---t----! .......... i . . . . +-+--i bi---;:===:::;--i - [UPEVNT] to let CPU read periodic signal latched by QCPRD
V,b '--� r--
,.. ,.,...".,' '-- !:ob'--_---'_
............1'--_---' register and adjust the phase accordingly. Using real-time
monitoring and tracking phase may adaptively adjust the output
(a)Bilateral symmetrical (b) Switch pattern optimized
AC phase, and benefit for output of the inverter.
SVPWM wavefonn SVPWM wavefonn
Figure I. Single-phase SVPWM wavefonn analysis
B. inverter bridge structure

Three-phase inverter modulates output of three-phase In order to improve the stability of the system in bridge
voltage by the combination of any two pairs of power switches, inverter circuit (Figure 2), we use IR2113 chip to indirectly
while the single-phase bridge inverter by two independent drive power switch. IR2113 chip is a dedicated driver of high­
power switches to modulates the output of one phase voltage, speed and high-voltage power-type MOSFET, IGBT, it has two
so the degree of freedom has been greatly improved. But the mutually independent high and low drive channels, using its
voltage output waveform of three-phase inverter are two pulses
with the same width which are symmetrical to the PWM cycle,
in practical applications in order to reduce loss of switching
devices in single-phase inverter bridge, we introduce switch­
mode optimization, we combine two pulses in the same cycle
to eliminate the falling edge of the previous pulse, and the
rising edge of a later pulse. In the operation, T 1 = T l' To =

To, PWM cycle (T) is fixed, the relatively register T b is


always set to zero in the half-cycle, T a = TII2, the final wave
was shown on Figure 1 (b). From the waveform analysis that
the losses of the optimized switching devices can be reduced by
50%. Figure 2. inverter drive circuit

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high-voltage output can stability control the conduction and the program memory space to obtain the current pulse time. We
tum-off of FET in a high potential of the bridge arm. The set T to 200IlS, T a ' T b determine To' T l' eventually we
maximum drive voltage of IR2 113 is up to 600V, for a wide
range jump of DC voltage it has good adaptability. MOS uses modify the duty cycle of the output waveform to determine the
IRFS40N FET, the DC input resistance RGS is 77mfJ., and the effective value of voltage vector v ab ' It operates data loading
model under the same conditions has a smaller switching losses to compare registers (CMPA, CMPB) CMPA, CMPB of
which help to improve inverter efficiency. ePWM, and sets register TBPRD periodically on increasing or
We use CSA-IV (Programmable Hall sensor chip) detect reducing counting mode, Compared with the TBPRD by the
current. The chip is produced using conventional CMOS CMPA, when CMPA overflows, EPWMIA pins have level
technology, the ferromagnetic layer in its silicon chip, detects change accordingly to adjust the duty cycle of final output
electromagnetic signal, computes gain of magnetic flux, and pulse. In the end, single-phase SVPWM waveform was shown
outputs the analog voltage after amplification. When wiring, in Figure 6 (a). Take the first half cycle as an example to set
the source pins of two lower bridge arms MOSFET (Q2, Q4) main registers of the ePWM:
are grounded, copper line with 2.5mm width comes from the TBPRD=T/4
bottom of the chip (Figure 3). The voltage signal outputs by
differential form, which is enlarged by the differential amplifier CMPA= T 1/2 (6)
circuit composed by LM324, linked to ADCINBO pin of F2806 CMPB= TO=O
for analog-digital conversion to measure the DC current, then
according to step-up ,converted to AC-side current. The T1=Msinwt
method uses Hall Effect test large current flows through the
ground-side, without the need for opto-isolation and other Where, M (:S I) is the pulse width modulation, T 1 can be
measures; it helps reduce the cost and size. With this method gotten through querying the sine table burned on process
the accuracy of output current sampling theory can be achieved storage space of F2806.
lmA, the actual detection accuracy is steady SmA.
In order to prevent the break-over of two switches at the
same time of upper and lower arms with the same phase, the
system uses the programmable dead-time control unit
I contained by ePWM. The procedures is designed to set
DBCTL [OUT-MODE] control bit for output mode, and to
determine the edge delay processing of the output PWM signal.
To control the dead-time can prevent phenomenon of short­
circuit caused by break-over at the same time and improve the
stability of the inverter.

B. Introduction of PID Control Algorithm


Figure 3. PCB wiring in current detection methods
The inverter uses PID (proportional integral differential
operation) algorithm to achieve the regulation of digital closed­
C. System hardware block diagram(Figure 4) loop, and utilizes the characteristic of high-speed operation on
DSC to achieve a real-time feedback control, which improve
the load capacity of the inverter.
TMS320F2806

High-frequency weak AC generated by vice secondary coil


of the becomes SOHz weak AC electrical signal which has the
same phase with the load after the filter through LC circuit,
then is connected to AO pin of ADCIN, the internal sample and
hold circuit of DSC makes it stability, last, the programmable
A I D conversion unit converts the analog voltage into digital
voltage. The data generated is treated as the instantaneous
Figure 4. System hardware block diagram
feedback of AC voltage output by the main and secondary coils
of transformer to make further PID adjustment and get
IV. SOFTWARE DESIGNTMTTT optimum output of sinusoidal voltage waveform. When the
inverter is powered up and the load power mutates, the output
A. Single-phase SVPWM output on the TMS320F2806 is uncertainty that causes the voltage feedback value is
The inverter uses two ePWM (Enhanced PWM) channels instability, DSC adopts PID control algorithm with separate
on the TMS320F2806 to output PWM signal. The main switch integral to solve the voltage oscillation. When the system
frequency of SVPWM is designed to S kHz, in the control output is stable, the introduction of integral can reduce the
algorithm, a disruption and load operation occurs on DSC over steady-state error, and also avoid the larger de-saturation and
each PWM cycle. First, it collects the results of output voltage overclocking to improve the system response and quality
through ADC conversion, and then performs the proportional control. Where the integral separation PID control algorithm:
operations compared to the datum on the sine table stored in

651
k
""k)=��k)+K/<;Lf(jT)+�[�k)-�k-l)] •• " '0 ' • • • • •• • _ . •• •• •• •• • •• . •• •• • • •• •• . • • •• ••

j=<J . . . . . . . . .
(7) : ; : : . : : : :

When the load mutates, the adjustment time of the output


voltage is short, the dynamic characteristics of a inverter is
:/.\v
. .: n\c
.... :: :
b·· ··· ·· · ····· ·· · · ····· ·· ··· ···;· ··,···
. ., . , . ., . , . ....
, , .
. , ... -; ., .
. . , . ..
:

J" I.." ··.,�.,, .I_.···[� · ..·,.""


· ·
good, F2806 uses PID to regulate that can effectively reduce . .

the situation of the output voltage waveform distortion caused


by non-linear changes of the load. The system software flow (a)single-phase SVPWM (b) Load voltage waveform
chart is shown on Figure 5. signal v ab waveform after 100 times attenuation

Figure 6. Experimental waveform

The modulation and generation of Single-phase SVPWM


wave and PID feedback regulation are the key to the design of
single-phase inverter system. DSC achieves the loop control
regulated by the PID algorithm because of the high-speed
operation, and makes the system get the purpose of
instantaneous steady state and improve the dynamic
characteristics of the inverter. EQEP module realizes the phase
tracking, the inverter has the adaptive capacity, it improves its
intelligence and facilitates for the output of the inverter.
SVPWM inverter after optimization of switch mode has the
Call ADC to detect advantages of a higher utilization rate and lower loss of
curren t an d va I tage switching devices compared to the traditional inverter; it
significantly enhances the conversion efficiency of the invert.

Carry on PID adjustment and


ACKNOWLEDGMENT
modify the data table
Tianjin Natural Science Foundation, China, under Grant No.
09JCYBJCOOI00, supports this work.
Tianjin Normal University Doctor Foundation, China,
under Grant No. 52LX32, supports this work.
Technology Correspondent Foundation of Tianjin Binhai
New Area, China, under Grant No. SB20080079, supports this
work.

Figure 5. System Software Flow Chart REFERENCES


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V. EXPERIMENTS AND CONCLUSION
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In the experimental circuit, the parameters are: filter (references)
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max
York: Academic, 1963, pp. 271-350.
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