EC806 DDFPGA

Review of Digital System Design

Sumam David S.
sumam@nitk.edu.in

DDFPGA

Objectives

• At the end of the lecture the student must be

able to
– Design combinational circuits and implement using
gates/mux/decoder, given a set of specifications
– Draw state diagram/ASM chart to describe a FSM
– Design a simple sequential circuit using DFF

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Review of combinational circuit design

• Number systems
• Logic Minimisation
– Karnaugh maps, Quine McCluskey, Variable entered maps
• Implementation using gates
– AND-OR (Sum of products) NAND-NAND
– OR- AND (Product of sums) NOR-NOR
– Two level realisation
• tcomb  area 
– Multilevel realisation
• Multiple output systems – reuse terms
• area  tcomb 

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Example – Karnaugh map

f(a,b,c,d) =  (1, 6, 7, 9. 10, 11, 14, 15)

g(a,b,c,d) =  (1, 3, 6, 9, 10, 11, 14)

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Example – 2 level realisation

f(a,b,c,d) =  (1, 6, 7, 9. 10, 11, 14, 15)

= ac + bc + b’c’d
g(a,b,c,d) =  (1, 3, 6, 9, 10, 11, 14)
= acd’ +bcd’ + b’d

Assume inverted literals are available

Delay = 2 units
Area  no of literals = 21 units

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Example – multi level realisation

Look for common terms

f(a,b,c,d) = ac + bc + b’c’d = c(a+b) +b’c’d
g(a,b,c,d) = acd’ +bcd’ + b’d = cd’(a+b) + b’d

u = (a+b) v = u.c w = b’d

f = v +c’w g = vd’ + w

Delay = 4 units
Area = 14 units

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Decoder based implementation

• Implement using 3:8 decoder

– f (x,y,z) =  (0, 3, 4, 6, 7)

– Multiple outputs
• Single decoder
• Multi input NAND for each output

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Mux based implementation

• Implement using 4:1 mux

– f (x,y,z) =  (0, 2, 3, 5, 7)

– Multiple outputs
• Multiple mux required
• Shannon’s expansion
– f(…..x……) = x’. f(…..0……) +x. f(…..1……)
– f = x’.fx’ + x.fx = (x’ + fx) (x + fx’ )
– fx = f(…..1……) is co factor of f with respect to x
– Principle of duality - swap 0 and 1, AND and OR
– f’ = x. f’x + x’. f’x’

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Sequential circuit design

Finite state machine FSM

inputs

Next Next state present state Output output

Flip
state
Decoder flops decoder

clock

Mealy FSM - output = f(present state, input)

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Sequential circuit design

inputs

Next Next state present state Output output

Flip
state
Decoder flops decoder

clock

Moore FSM - output = f(present state)

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FSM

inputs outputs
NSD
&
OD
Present
next
state
state

FF

NSD and OD are combinational circuits

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Mealy vs Moore FSM

• Mealy FSM could respond to glitches in input

– Better to have outputs which are synchronised with clock
– Mealy FSM with registered outputs or Moore FSM
• Moore FSM could have more number of states

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State diagram

• Draw the state diagram for a Mealy FSM to detect the

sequence “101” in a continuous stream of data

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State diagram

• Draw the state diagram for a Mealy FSM to detect the

sequence “101” in a continuous stream of data

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State diagram

• Draw the state diagram for a Moore FSM to detect

the sequence “101” in a continuous stream of data

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State diagram

• Draw the state diagram for a Moore FSM to detect

the sequence “101” in a continuous stream of data

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State assignment

• Binary assignment
– Minimum number of FF
– INIT – 000 or 111 for ease of reset
• Gray code assignment
• One hot encoding
– Only one bit is one in the statecode
• Modified one hot encoding
• Unused states
– Minimum cost – don’t care
– Minimum risk – force to INIT in next clock

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ASM charts

• Better for complex systems

• if … then …. else/elsif ….

Conditional
State box output
Decision

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ASM chart example

S0

0 1
X1

Z1 Z2

S1
1 0
X2 Z3

0 1
Z3 X3 X2

1 0
S2
Z1

1
X1

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Exercise – Sequential design

• Implement the Mealy and Moore FSM for sequence

detector using DFF

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Exercise – Combinational circuit

• Design a leading zeros counter to be used in the

normalization stage of an 8 bit floating point
arithmetic unit. (ie. counts the number of zeros from
msb side before the first 1 is found in the 8 bit
input). System has 8 bit data input, 3 bit count
output and one “all-zeros” output.
– Example
• Input 00010101 Output 011 allzero 0
• Input 01010101 Output 001 allzero 0
• Input 00000001 Output 111 allzero 0
• Input 00000000 Output 111 allzero 1

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